diff --git a/js/src/assembler/assembler/ARMAssembler.h b/js/src/assembler/assembler/ARMAssembler.h index b10940576a5..f807eebf37e 100644 --- a/js/src/assembler/assembler/ARMAssembler.h +++ b/js/src/assembler/assembler/ARMAssembler.h @@ -41,7 +41,24 @@ #include "AssemblerBufferWithConstantPool.h" #include "assembler/wtf/Assertions.h" -// TODO: We don't print the condition code in our spew lines. Doing this +#include "methodjit/Logging.h" +#define IPFX " %s" +#define ISPFX " " +#ifdef JS_METHODJIT_SPEW +# define MAYBE_PAD (isOOLPath ? "> " : "") +# define FIXME_INSN_PRINTING \ + do { \ + js::JaegerSpew(js::JSpew_Insns, \ + IPFX "FIXME insn printing %s:%d\n", \ + MAYBE_PAD, \ + __FILE__, __LINE__); \ + } while (0) +#else +# define MAYBE_PAD "" +# define FIXME_INSN_PRINTING ((void) 0) +#endif + +// TODO: We don't print the condition code in our JaegerSpew lines. Doing this // is awkward whilst maintaining a consistent field width. namespace js { namespace ion { @@ -126,9 +143,16 @@ namespace JSC { return (FPRegisterID)(d / 2); } } // namespace ARMRegisters - class ARMAssembler : public GenericAssembler { + class ARMAssembler { public: - + +#ifdef JS_METHODJIT_SPEW + bool isOOLPath; + // Assign a default value to keep Valgrind quiet. + ARMAssembler() : isOOLPath(false) { } +#else + ARMAssembler() { } +#endif typedef ARMRegisters::RegisterID RegisterID; typedef ARMRegisters::FPRegisterID FPRegisterID; typedef AssemblerBufferWithConstantPool<2048, 4, 4, ARMAssembler> ARMBuffer; @@ -469,14 +493,16 @@ namespace JSC { void movw_r(int rd, ARMWord op2, Condition cc = AL) { ASSERT((op2 | 0xf0fff) == 0xf0fff); - spew("%-15s %s, 0x%04x", "movw", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, 0x%04x\n", MAYBE_PAD, "movw", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000)); m_buffer.putInt(static_cast(cc) | MOVW | RD(rd) | op2); } void movt_r(int rd, ARMWord op2, Condition cc = AL) { ASSERT((op2 | 0xf0fff) == 0xf0fff); - spew("%-15s %s, 0x%04x", "movt", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, 0x%04x\n", MAYBE_PAD, "movt", nameGpReg(rd), (op2 & 0xfff) | ((op2 >> 4) & 0xf000)); m_buffer.putInt(static_cast(cc) | MOVT | RD(rd) | op2); } #endif @@ -525,7 +551,8 @@ namespace JSC { void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) { - spew("%-15s %s, %s, %s, %s", "mull", nameGpReg(rdlo), nameGpReg(rdhi), nameGpReg(rn), nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s, %s\n", MAYBE_PAD, "mull", nameGpReg(rdlo), nameGpReg(rdhi), nameGpReg(rn), nameGpReg(rm)); m_buffer.putInt(static_cast(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm)); } @@ -534,7 +561,8 @@ namespace JSC { { char mnemonic[16]; snprintf(mnemonic, 16, "ldr%s", nameCC(cc)); - spew("%-15s %s, =0x%x @ (%d) (reusable pool entry)", mnemonic, nameGpReg(rd), imm, static_cast(imm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, =0x%x @ (%d) (reusable pool entry)\n", MAYBE_PAD, mnemonic, nameGpReg(rd), imm, static_cast(imm)); m_buffer.putIntWithConstantInt(static_cast(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm, true); } @@ -542,7 +570,8 @@ namespace JSC { { char mnemonic[16]; snprintf(mnemonic, 16, "ldr%s", nameCC(cc)); - spew("%-15s %s, =0x%x @ (%d)", mnemonic, nameGpReg(rd), imm, static_cast(imm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, =0x%x @ (%d)\n", MAYBE_PAD, mnemonic, nameGpReg(rd), imm, static_cast(imm)); m_buffer.putIntWithConstantInt(static_cast(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm); } @@ -566,9 +595,10 @@ namespace JSC { break; } char const * off_sign = (posOffset) ? ("+") : ("-"); - spew("%sr%s%s %s, [%s, #%s%u]", - mnemonic_act, mnemonic_sign, mnemonic_size, - nameGpReg(rd), nameGpReg(rb), off_sign, offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%sr%s%s %s, [%s, #%s%u]\n", + MAYBE_PAD, mnemonic_act, mnemonic_sign, mnemonic_size, + nameGpReg(rd), nameGpReg(rb), off_sign, offset); if (size == 32 || (size == 8 && !isSigned)) { /* All (the one) 32 bit ops and the unsigned 8 bit ops use the original encoding.*/ emitInst(static_cast(cc) | DTR | @@ -603,8 +633,9 @@ namespace JSC { break; } char const * off_sign = (posOffset) ? ("+") : ("-"); - spew("%sr%s%s %s, [%s, #%s%s]", mnemonic_act, mnemonic_sign, mnemonic_size, - nameGpReg(rd), nameGpReg(rb), off_sign, nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%sr%s%s %s, [%s, #%s%s]\n", MAYBE_PAD, mnemonic_act, mnemonic_sign, mnemonic_size, + nameGpReg(rd), nameGpReg(rb), off_sign, nameGpReg(rm)); if (size == 32 || (size == 8 && !isSigned)) { /* All (the one) 32 bit ops and the signed 8 bit ops use the original encoding.*/ emitInst(static_cast(cc) | DTR | @@ -628,8 +659,8 @@ namespace JSC { void dtr_u(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldr") : ("str"); - spew("%-15s %s, [%s, #+%u]", - mnemonic, nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, offset); } @@ -639,8 +670,8 @@ namespace JSC { void dtr_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldr") : ("str"); - spew("%-15s %s, [%s, +%s]", - mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); emitInst(static_cast(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm); } @@ -650,8 +681,8 @@ namespace JSC { void dtr_d(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldr") : ("str"); - spew("%-15s %s, [%s, #-%u]", - mnemonic, nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | DTR | (isLoad ? DT_LOAD : 0), rd, rb, offset); } @@ -661,8 +692,8 @@ namespace JSC { void dtr_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldr") : ("str"); - spew("%-15s %s, [%s, -%s]", - mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, -%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); emitInst(static_cast(cc) | DTR | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm); } @@ -672,8 +703,8 @@ namespace JSC { void dtrb_u(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldrb") : ("strb"); - spew("%-15s %s, [%s, #+%u]", - mnemonic, nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, offset); } @@ -683,8 +714,8 @@ namespace JSC { void dtrsb_u(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldrsb") : ("strb"); - spew("%-15s %s, [%s, #+%u]", - mnemonic, nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | DTRH | HDT_S | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, offset); } @@ -694,8 +725,8 @@ namespace JSC { void dtrb_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldrb") : ("strb"); - spew("%-15s %s, [%s, +%s]", - mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); emitInst(static_cast(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm); } @@ -705,8 +736,8 @@ namespace JSC { void dtrb_d(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldrb") : ("strb"); - spew("%-15s %s, [%s, #-%u]", - mnemonic, nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0), rd, rb, offset); } @@ -717,8 +748,8 @@ namespace JSC { { ASSERT(isLoad); /*can only do signed byte loads, not stores*/ char const * mnemonic = (isLoad) ? ("ldrsb") : ("strb"); - spew("%-15s %s, [%s, #-%u]", - mnemonic, nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | DTRH | HDT_S | (isLoad ? DT_LOAD : 0), rd, rb, offset); } @@ -728,65 +759,65 @@ namespace JSC { void dtrb_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL) { char const * mnemonic = (isLoad) ? ("ldrb") : ("strb"); - spew("%-15s %s, [%s, -%s]", - mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, -%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); emitInst(static_cast(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm); } void ldrh_r(int rd, int rb, int rm, Condition cc = AL) { - spew("%-15s %s, [%s, +%s]", - "ldrh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, "ldrh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); emitInst(static_cast(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rb, rm); } void ldrh_d(int rd, int rb, ARMWord offset, Condition cc = AL) { - spew("%-15s %s, [%s, #-%u]", - "ldrh", nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, "ldrh", nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | LDRH | HDT_UH | DT_PRE, rd, rb, offset); } void ldrh_u(int rd, int rb, ARMWord offset, Condition cc = AL) { - spew("%-15s %s, [%s, #+%u]", - "ldrh", nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, "ldrh", nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rb, offset); } void ldrsh_d(int rd, int rb, ARMWord offset, Condition cc = AL) { - spew("%-15s %s, [%s, #-%u]", - "ldrsh", nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, "ldrsh", nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | LDRH | HDT_UH | HDT_S | DT_PRE, rd, rb, offset); } void ldrsh_u(int rd, int rb, ARMWord offset, Condition cc = AL) { - spew("%-15s %s, [%s, #+%u]", - "ldrsh", nameGpReg(rd), nameGpReg(rb), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, "ldrsh", nameGpReg(rd), nameGpReg(rb), offset); emitInst(static_cast(cc) | LDRH | HDT_UH | HDT_S | DT_UP | DT_PRE, rd, rb, offset); } void strh_r(int rb, int rm, int rd, Condition cc = AL) { - spew("%-15s %s, [%s, +%s]", - "strh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, "strh", nameGpReg(rd), nameGpReg(rb), nameGpReg(rm)); emitInst(static_cast(cc) | STRH | HDT_UH | DT_UP | DT_PRE, rd, rb, rm); } void push_r(int reg, Condition cc = AL) { - spew("%-15s {%s}", - "push", nameGpReg(reg)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s {%s}\n", MAYBE_PAD, "push", nameGpReg(reg)); ASSERT(ARMWord(reg) <= 0xf); m_buffer.putInt(cc | DTR | DT_WB | RN(ARMRegisters::sp) | RD(reg) | 0x4); } void pop_r(int reg, Condition cc = AL) { - spew("%-15s {%s}", - "pop", nameGpReg(reg)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s {%s}\n", MAYBE_PAD, "pop", nameGpReg(reg)); ASSERT(ARMWord(reg) <= 0xf); m_buffer.putInt(cc | (DTR ^ DT_PRE) | DT_LOAD | DT_UP | RN(ARMRegisters::sp) | RD(reg) | 0x4); } @@ -814,7 +845,8 @@ namespace JSC { void bkpt(ARMWord value) { #if WTF_ARM_ARCH_VERSION >= 5 - spew("%-15s #0x%04x", "bkpt", value); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s #0x%04x\n", MAYBE_PAD, "bkpt", value); m_buffer.putInt(BKPT | ((value & 0xfff0) << 4) | (value & 0xf)); #else // Cannot access to Zero memory address @@ -825,7 +857,9 @@ namespace JSC { void bx(int rm, Condition cc = AL) { #if WTF_ARM_ARCH_VERSION >= 5 || defined(__ARM_ARCH_4T__) - spew("bx%-13s %s", nameCC(cc), nameGpReg(rm)); + js::JaegerSpew( + js::JSpew_Insns, + IPFX "bx%-13s %s\n", MAYBE_PAD, nameCC(cc), nameGpReg(rm)); emitInst(static_cast(cc) | BX, 0, 0, RM(rm)); #else mov_r(ARMRegisters::pc, RM(rm), cc); @@ -836,7 +870,9 @@ namespace JSC { { #if WTF_CPU_ARM && WTF_ARM_ARCH_VERSION >= 5 int s = m_buffer.uncheckedSize(); - spew("blx%-12s %s", nameCC(cc), nameGpReg(rm)); + js::JaegerSpew( + js::JSpew_Insns, + IPFX "blx%-12s %s\n", MAYBE_PAD, nameCC(cc), nameGpReg(rm)); emitInst(static_cast(cc) | BLX, 0, 0, RM(rm)); #else ASSERT(rm != 14); @@ -925,7 +961,7 @@ namespace JSC { JmpDst label() { JmpDst label(m_buffer.size()); - spew("#label ((%d))", label.m_offset); + js::JaegerSpew(js::JSpew_Insns, IPFX "#label ((%d))\n", MAYBE_PAD, label.m_offset); return label; } @@ -1010,24 +1046,27 @@ namespace JSC { static void linkPointer(void* code, JmpDst from, void* to) { - staticSpew("##linkPointer ((%p + %#x)) points to ((%p))", - code, from.m_offset, to); + js::JaegerSpew(js::JSpew_Insns, + "##linkPointer ((%p + %#x)) points to ((%p))\n", + code, from.m_offset, to); patchPointerInternal(reinterpret_cast(code) + from.m_offset, to); } static void repatchInt32(void* from, int32_t to) { - staticSpew("##repatchInt32 ((%p)) holds ((%#x))", - from, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##repatchInt32 ((%p)) holds ((%#x))\n", + from, to); patchPointerInternal(reinterpret_cast(from), reinterpret_cast(to)); } static void repatchPointer(void* from, void* to) { - staticSpew("##repatchPointer ((%p)) points to ((%p))", - from, to); + js::JaegerSpew(js::JSpew_Insns, + "##repatchPointer ((%p)) points to ((%p))\n", + from, to); patchPointerInternal(reinterpret_cast(from), to); } @@ -1064,24 +1103,27 @@ namespace JSC { ARMWord* insn = reinterpret_cast(code + from.m_offset); ARMWord* addr = getLdrImmAddressOnPool(insn, m_buffer.poolAddress()); - spew("##linkJump ((%#x)) jumps to ((%#x))", - from.m_offset, to.m_offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "##linkJump ((%#x)) jumps to ((%#x))\n", MAYBE_PAD, + from.m_offset, to.m_offset); *addr = to.m_offset; } static void linkJump(void* code, JmpSrc from, void* to) { - staticSpew("##linkJump ((%p + %#x)) jumps to ((%p))", - code, from.m_offset, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##linkJump ((%p + %#x)) jumps to ((%p))\n", + code, from.m_offset, to); patchPointerInternal(reinterpret_cast(code) + from.m_offset, to); } static void relinkJump(void* from, void* to) { - staticSpew("##relinkJump ((%p)) jumps to ((%p))", - from, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##relinkJump ((%p)) jumps to ((%p))\n", + from, to); patchPointerInternal(reinterpret_cast(from), to); } @@ -1093,16 +1135,18 @@ namespace JSC { static void linkCall(void* code, JmpSrc from, void* to) { - staticSpew("##linkCall ((%p + %#x)) jumps to ((%p))", - code, from.m_offset, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##linkCall ((%p + %#x)) jumps to ((%p))\n", + code, from.m_offset, to); patchPointerInternal(reinterpret_cast(code) + from.m_offset, to); } static void relinkCall(void* from, void* to) { - staticSpew("##relinkCall ((%p)) jumps to ((%p))", - from, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##relinkCall ((%p)) jumps to ((%p))\n", + from, to); patchPointerInternal(reinterpret_cast(from), to); } @@ -1341,7 +1385,8 @@ namespace JSC { char op2_fmt[48]; fmtOp2(op2_fmt, op2); - spew("%-15s %s, %s, %s", mnemonic, nameGpReg(rd), nameGpReg(rn), op2_fmt); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rn), op2_fmt); } void spewInsWithOp2(char const * ins, Condition cc, int r, ARMWord op2) @@ -1352,7 +1397,8 @@ namespace JSC { char op2_fmt[48]; fmtOp2(op2_fmt, op2); - spew("%-15s %s, %s", mnemonic, nameGpReg(r), op2_fmt); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s\n", MAYBE_PAD, mnemonic, nameGpReg(r), op2_fmt); } ARMWord RM(int reg) @@ -1510,9 +1556,10 @@ namespace JSC { void fmem_imm_off(bool isLoad, bool isDouble, bool isUp, int dest, int rn, ARMWord offset, Condition cc = AL) { char const * ins = isLoad ? "vldr.f" : "vstr.f"; - spew("%s%d %s, [%s, #%s%u]", - ins, (isDouble ? 64 : 32), (isDouble ? nameFpRegD(dest) : nameFpRegS(dest)), - nameGpReg(rn), (isUp ? "+" : "-"), offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%s%d %s, [%s, #%s%u]\n", MAYBE_PAD, + ins, (isDouble ? 64 : 32), (isDouble ? nameFpRegD(dest) : nameFpRegS(dest)), + nameGpReg(rn), (isUp ? "+" : "-"), offset); ASSERT(offset <= 0xff); emitVFPInst(static_cast(cc) | VFP_EXT | VFP_DTR | @@ -1529,9 +1576,10 @@ namespace JSC { ASSERT(srcType != dstType); ASSERT(isFloatType(srcType) || isFloatType(dstType)); - spew("vcvt.%s.%-15s, %s,%s", - nameType(dstType), nameType(srcType), - nameTypedReg(dstType,dest), nameTypedReg(srcType,src)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "vcvt.%s.%-15s, %s,%s\n", MAYBE_PAD, + nameType(dstType), nameType(srcType), + nameTypedReg(dstType,dest), nameTypedReg(srcType,src)); if (isFloatType(srcType) && isFloatType (dstType)) { // doing a float -> float conversion @@ -1549,11 +1597,13 @@ namespace JSC { void vmov64 (bool fromFP, bool isDbl, int r1, int r2, int rFP, Condition cc = AL) { if (fromFP) { - spew("%-15s %s, %s, %s", "vmov", - nameGpReg(r1), nameGpReg(r2), nameFpRegD(rFP)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vmov", + nameGpReg(r1), nameGpReg(r2), nameFpRegD(rFP)); } else { - spew("%-15s %s, %s, %s", "vmov", - nameFpRegD(rFP), nameGpReg(r1), nameGpReg(r2)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vmov", + nameFpRegD(rFP), nameGpReg(r1), nameGpReg(r2)); } emitVFPInst(static_cast(cc) | VFP_DXFER | VFP_MOV | (fromFP ? DT_LOAD : 0) | @@ -1562,8 +1612,9 @@ namespace JSC { void fcpyd_r(int dd, int dm, Condition cc = AL) { - spew("%-15s %s, %s", "vmov.f64", - nameFpRegD(dd), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s\n", MAYBE_PAD, "vmov.f64", + nameFpRegD(dd), nameFpRegD(dm)); // TODO: emitInst doesn't work for VFP instructions, though it // seems to work for current usage. emitVFPInst(static_cast(cc) | FCPYD, DD(dd), DM(dm), 0); @@ -1571,7 +1622,8 @@ namespace JSC { void faddd_r(int dd, int dn, int dm, Condition cc = AL) { - spew("%-15s %s, %s, %s", "vadd.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vadd.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); // TODO: emitInst doesn't work for VFP instructions, though it // seems to work for current usage. emitVFPInst(static_cast(cc) | FADDD, DD(dd), DN(dn), DM(dm)); @@ -1579,13 +1631,15 @@ namespace JSC { void fnegd_r(int dd, int dm, Condition cc = AL) { - spew("%-15s %s, %s", "fnegd", nameFpRegD(dd), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s\n", MAYBE_PAD, "fnegd", nameFpRegD(dd), nameFpRegD(dm)); m_buffer.putInt(static_cast(cc) | FNEGD | DD(dd) | DM(dm)); } void fdivd_r(int dd, int dn, int dm, Condition cc = AL) { - spew("%-15s %s, %s, %s", "vdiv.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vdiv.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); // TODO: emitInst doesn't work for VFP instructions, though it // seems to work for current usage. emitVFPInst(static_cast(cc) | FDIVD, DD(dd), DN(dn), DM(dm)); @@ -1593,7 +1647,8 @@ namespace JSC { void fsubd_r(int dd, int dn, int dm, Condition cc = AL) { - spew("%-15s %s, %s, %s", "vsub.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vsub.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); // TODO: emitInst doesn't work for VFP instructions, though it // seems to work for current usage. emitVFPInst(static_cast(cc) | FSUBD, DD(dd), DN(dn), DM(dm)); @@ -1601,13 +1656,15 @@ namespace JSC { void fabsd_r(int dd, int dm, Condition cc = AL) { - spew("%-15s %s, %s", "fabsd", nameFpRegD(dd), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s\n", MAYBE_PAD, "fabsd", nameFpRegD(dd), nameFpRegD(dm)); m_buffer.putInt(static_cast(cc) | FABSD | DD(dd) | DM(dm)); } void fmuld_r(int dd, int dn, int dm, Condition cc = AL) { - spew("%-15s %s, %s, %s", "vmul.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s, %s\n", MAYBE_PAD, "vmul.f64", nameFpRegD(dd), nameFpRegD(dn), nameFpRegD(dm)); // TODO: emitInst doesn't work for VFP instructions, though it // seems to work for current usage. emitVFPInst(static_cast(cc) | FMULD, DD(dd), DN(dn), DM(dm)); @@ -1615,7 +1672,8 @@ namespace JSC { void fcmpd_r(int dd, int dm, Condition cc = AL) { - spew("%-15s %s, %s", "vcmp.f64", nameFpRegD(dd), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s\n", MAYBE_PAD, "vcmp.f64", nameFpRegD(dd), nameFpRegD(dm)); // TODO: emitInst doesn't work for VFP instructions, though it // seems to work for current usage. emitVFPInst(static_cast(cc) | FCMPD, DD(dd), 0, DM(dm)); @@ -1623,7 +1681,8 @@ namespace JSC { void fsqrtd_r(int dd, int dm, Condition cc = AL) { - spew("%-15s %s, %s", "vsqrt.f64", nameFpRegD(dd), nameFpRegD(dm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "%-15s %s, %s\n", MAYBE_PAD, "vsqrt.f64", nameFpRegD(dd), nameFpRegD(dm)); // TODO: emitInst doesn't work for VFP instructions, though it // seems to work for current usage. emitVFPInst(static_cast(cc) | FSQRTD, DD(dd), 0, DM(dm)); diff --git a/js/src/assembler/assembler/AssemblerBuffer.h b/js/src/assembler/assembler/AssemblerBuffer.h index 180c49b1502..86699d21e31 100644 --- a/js/src/assembler/assembler/AssemblerBuffer.h +++ b/js/src/assembler/assembler/AssemblerBuffer.h @@ -39,20 +39,6 @@ #include "assembler/jit/ExecutableAllocator.h" #include "assembler/wtf/Assertions.h" -#include -#include "jsopcode.h" - -#include "methodjit/Logging.h" -#include "ion/IonSpewer.h" - -#define PRETTY_PRINT_OFFSET(os) (((os)<0)?"-":""), (((os)<0)?-(os):(os)) - -#define FIXME_INSN_PRINTING \ - do { \ - spew("FIXME insn printing %s:%d", \ - __FILE__, __LINE__); \ - } while (0) - namespace JSC { class AssemblerBuffer { @@ -248,81 +234,6 @@ namespace JSC { bool m_oom; }; - class GenericAssembler - { - js::Sprinter *printer; - - public: - - bool isOOLPath; - - GenericAssembler() - : printer(NULL) - , isOOLPath(false) - {} - - void setPrinter(js::Sprinter *sp) { - printer = sp; - } - - void spew(const char *fmt, ...) -#ifdef __GNUC__ - __attribute__ ((format (printf, 2, 3))) -#endif - { - if (printer || - js::IsJaegerSpewChannelActive(js::JSpew_Insns) || - js::ion::IonSpewEnabled(js::ion::IonSpew_Codegen)) - { - // Buffer to hold the formatted string. Note that this may contain - // '%' characters, so do not pass it directly to printf functions. - char buf[200]; - - va_list va; - va_start(va, fmt); - int i = vsnprintf(buf, sizeof(buf), fmt, va); - va_end(va); - - if (i > -1) { - if (printer) - printer->printf("%s\n", buf); - - // The assembler doesn't know which compiler it is for, so if - // both JM and Ion spew are on, just print via one channel - // (Use JM to pick up isOOLPath). - if (js::IsJaegerSpewChannelActive(js::JSpew_Insns)) - js::JaegerSpew(js::JSpew_Insns, "%s %s\n", isOOLPath ? ">" : " ", buf); - else - js::ion::IonSpew(js::ion::IonSpew_Codegen, "%s", buf); - } - } - } - - static void staticSpew(const char *fmt, ...) -#ifdef __GNUC__ - __attribute__ ((format (printf, 1, 2))) -#endif - { - if (js::IsJaegerSpewChannelActive(js::JSpew_Insns) || - js::ion::IonSpewEnabled(js::ion::IonSpew_Codegen)) - { - char buf[200]; - - va_list va; - va_start(va, fmt); - int i = vsnprintf(buf, sizeof(buf), fmt, va); - va_end(va); - - if (i > -1) { - if (js::IsJaegerSpewChannelActive(js::JSpew_Insns)) - js::JaegerSpew(js::JSpew_Insns, " %s\n", buf); - else - js::ion::IonSpew(js::ion::IonSpew_Codegen, "%s", buf); - } - } - } - }; - } // namespace JSC #endif // ENABLE(ASSEMBLER) diff --git a/js/src/assembler/assembler/AssemblerBufferWithConstantPool.h b/js/src/assembler/assembler/AssemblerBufferWithConstantPool.h index cab80574de6..d85942e9b99 100644 --- a/js/src/assembler/assembler/AssemblerBufferWithConstantPool.h +++ b/js/src/assembler/assembler/AssemblerBufferWithConstantPool.h @@ -333,8 +333,8 @@ private: // optionally place a jump to ensure we don't start executing the pool. void flushConstantPool(bool useBarrier = true) { - GenericAssembler::staticSpew(" -- FLUSHING CONSTANT POOL WITH %d CONSTANTS --\n", - m_numConsts); + js::JaegerSpew(js::JSpew_Insns, " -- FLUSHING CONSTANT POOL WITH %d CONSTANTS --\n", + m_numConsts); if (m_numConsts == 0) return; m_flushCount++; diff --git a/js/src/assembler/assembler/MIPSAssembler.h b/js/src/assembler/assembler/MIPSAssembler.h index f2e3db37397..b73952c3205 100644 --- a/js/src/assembler/assembler/MIPSAssembler.h +++ b/js/src/assembler/assembler/MIPSAssembler.h @@ -40,8 +40,17 @@ #define ISPFX " " #ifdef JS_METHODJIT_SPEW # define MAYBE_PAD (isOOLPath ? "> " : "") +# define PRETTY_PRINT_OFFSET(os) (((os)<0)?"-":""), (((os)<0)?-(os):(os)) +# define FIXME_INSN_PRINTING \ + do { \ + js::JaegerSpew(js::JSpew_Insns, \ + ISPFX "FIXME insn printing %s:%d\n", \ + __FILE__, __LINE__); \ + } while (0) #else # define MAYBE_PAD "" +# define FIXME_INSN_PRINTING ((void) 0) +# define PRETTY_PRINT_OFFSET(os) "", 0 #endif namespace JSC { @@ -153,7 +162,7 @@ typedef enum { } // namespace MIPSRegisters -class MIPSAssembler : public GenericAssembler { +class MIPSAssembler { public: typedef MIPSRegisters::RegisterID RegisterID; typedef MIPSRegisters::FPRegisterID FPRegisterID; @@ -161,6 +170,13 @@ public: unsigned char *buffer() const { return m_buffer.buffer(); } bool oom() const { return m_buffer.oom(); } +#ifdef JS_METHODJIT_SPEW + bool isOOLPath; + MIPSAssembler() : isOOLPath(false) { } +#else + MIPSAssembler() { } +#endif + // MIPS instruction opcode field position enum { OP_SH_RD = 11, diff --git a/js/src/assembler/assembler/SparcAssembler.h b/js/src/assembler/assembler/SparcAssembler.h index 4e3d5b14559..0d08afdefe8 100644 --- a/js/src/assembler/assembler/SparcAssembler.h +++ b/js/src/assembler/assembler/SparcAssembler.h @@ -22,8 +22,17 @@ #define ISPFX " " #ifdef JS_METHODJIT_SPEW # define MAYBE_PAD (isOOLPath ? "> " : "") +# define PRETTY_PRINT_OFFSET(os) (((os)<0)?"-":""), (((os)<0)?-(os):(os)) +# define FIXME_INSN_PRINTING \ + do { \ + js::JaegerSpew(js::JSpew_Insns, \ + ISPFX "FIXME insn printing %s:%d\n", \ + __FILE__, __LINE__); \ + } while (0) #else # define MAYBE_PAD "" +# define FIXME_INSN_PRINTING ((void) 0) +# define PRETTY_PRINT_OFFSET(os) "", 0 #endif namespace JSC { @@ -109,13 +118,20 @@ namespace JSC { } // namespace SparcRegisters - class SparcAssembler : public GenericAssembler { + class SparcAssembler { public: typedef SparcRegisters::RegisterID RegisterID; typedef SparcRegisters::FPRegisterID FPRegisterID; AssemblerBuffer m_buffer; bool oom() const { return m_buffer.oom(); } +#ifdef JS_METHODJIT_SPEW + bool isOOLPath; + SparcAssembler() : isOOLPath(false) { } +#else + SparcAssembler() { } +#endif + // Sparc conditional constants typedef enum { ConditionE = 0x1, // Zero diff --git a/js/src/assembler/assembler/X86Assembler.h b/js/src/assembler/assembler/X86Assembler.h index 93031f95575..3914993a277 100644 --- a/js/src/assembler/assembler/X86Assembler.h +++ b/js/src/assembler/assembler/X86Assembler.h @@ -30,8 +30,6 @@ #ifndef X86Assembler_h #define X86Assembler_h -#include - #include "assembler/wtf/Platform.h" #if ENABLE_ASSEMBLER && (WTF_CPU_X86 || WTF_CPU_X86_64) @@ -40,6 +38,25 @@ #include "assembler/wtf/Assertions.h" #include "js/Vector.h" +#include "methodjit/Logging.h" +#define IPFX " %s" +#define ISPFX " " +#ifdef JS_METHODJIT_SPEW +# define MAYBE_PAD (isOOLPath ? "> " : "") +# define PRETTY_PRINT_OFFSET(os) (((os)<0)?"-":""), (((os)<0)?-(os):(os)) +# define FIXME_INSN_PRINTING \ + do { \ + js::JaegerSpew(js::JSpew_Insns, \ + ISPFX "FIXME insn printing %s:%d\n", \ + __FILE__, __LINE__); \ + } while (0) +#else +# define MAYBE_PAD "" +# define FIXME_INSN_PRINTING ((void) 0) +# define PRETTY_PRINT_OFFSET(os) "", 0 +#endif + + namespace JSC { inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; } @@ -137,7 +154,7 @@ namespace X86Registers { } /* namespace X86Registers */ -class X86Assembler : public GenericAssembler { +class X86Assembler { public: typedef X86Registers::RegisterID RegisterID; typedef X86Registers::XMMRegisterID XMMRegisterID; @@ -339,6 +356,10 @@ private: class X86InstructionFormatter; public: +#ifdef JS_METHODJIT_SPEW + bool isOOLPath; +#endif + class JmpSrc { friend class X86Assembler; friend class X86InstructionFormatter; @@ -393,13 +414,21 @@ public: bool m_used : 1; }; + X86Assembler() +#ifdef JS_METHODJIT_SPEW + : isOOLPath(false) +#endif + { + } + size_t size() const { return m_formatter.size(); } unsigned char *buffer() const { return m_formatter.buffer(); } bool oom() const { return m_formatter.oom(); } void nop() { - spew("nop"); + js::JaegerSpew(js::JSpew_Insns, + IPFX "nop\n", MAYBE_PAD); m_formatter.oneByteOp(OP_NOP); } @@ -407,28 +436,32 @@ public: void push_r(RegisterID reg) { - spew("push %s", nameIReg(reg)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "push %s\n", MAYBE_PAD, nameIReg(reg)); m_formatter.oneByteOp(OP_PUSH_EAX, reg); } void pop_r(RegisterID reg) { - spew("pop %s", nameIReg(reg)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "pop %s\n", MAYBE_PAD, nameIReg(reg)); m_formatter.oneByteOp(OP_POP_EAX, reg); } void push_i32(int imm) { - spew("pushl %s$0x%x", - PRETTY_PRINT_OFFSET(imm)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "pushl %s$0x%x\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(imm)); m_formatter.oneByteOp(OP_PUSH_Iz); m_formatter.immediate32(imm); } void push_m(int offset, RegisterID base) { - spew("push %s0x%x(%s)", - PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "push %s0x%x(%s)\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_PUSH, base, offset); } @@ -456,15 +489,17 @@ public: void addl_rr(RegisterID src, RegisterID dst) { - spew("addl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_ADD_EvGv, src, dst); } void addl_mr(int offset, RegisterID base, RegisterID dst) { - spew("addl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(4,base), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(4,base), nameIReg(4,dst)); m_formatter.oneByteOp(OP_ADD_GvEv, dst, base, offset); } @@ -476,7 +511,8 @@ public: void addl_ir(int imm, RegisterID dst) { - spew("addl $0x%x, %s", imm, nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addl $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(4,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst); m_formatter.immediate8(imm); @@ -488,8 +524,9 @@ public: void addl_im(int imm, int offset, RegisterID base) { - spew("addl %d, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(8,base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addl %d, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(8,base)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset); m_formatter.immediate8(imm); @@ -508,7 +545,8 @@ public: void addq_ir(int imm, RegisterID dst) { - spew("addq $0x%x, %s", imm, nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addq $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(8,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst); m_formatter.immediate8(imm); @@ -520,8 +558,9 @@ public: void addq_im(int imm, int offset, RegisterID base) { - spew("addq $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(8,base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addq $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(8,base)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset); m_formatter.immediate8(imm); @@ -546,15 +585,17 @@ public: void andl_rr(RegisterID src, RegisterID dst) { - spew("andl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "andl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_AND_EvGv, src, dst); } void andl_mr(int offset, RegisterID base, RegisterID dst) { - spew("andl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(4,base), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "andl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(4,base), nameIReg(4,dst)); m_formatter.oneByteOp(OP_AND_GvEv, dst, base, offset); } @@ -566,7 +607,8 @@ public: void andl_ir(int imm, RegisterID dst) { - spew("andl $0x%x, %s", imm, nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "andl $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(4,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, dst); m_formatter.immediate8(imm); @@ -591,28 +633,32 @@ public: #if WTF_CPU_X86_64 void andq_rr(RegisterID src, RegisterID dst) { - spew("andq %s, %s", - nameIReg(8,src), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "andq %s, %s\n", MAYBE_PAD, + nameIReg(8,src), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_AND_EvGv, src, dst); } void andq_mr(int offset, RegisterID base, RegisterID dst) { - spew("andq %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "andq %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_AND_GvEv, dst, base, offset); } void orq_mr(int offset, RegisterID base, RegisterID dst) { - spew("orq %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "orq %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_OR_GvEv, dst, base, offset); } void andq_ir(int imm, RegisterID dst) { - spew("andq $0x%x, %s", imm, nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "andq $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(8,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_AND, dst); m_formatter.immediate8(imm); @@ -642,7 +688,8 @@ public: void negl_r(RegisterID dst) { - spew("negl %s", nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "negl %s\n", MAYBE_PAD, nameIReg(4,dst)); m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NEG, dst); } @@ -654,7 +701,8 @@ public: void notl_r(RegisterID dst) { - spew("notl %s", nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "notl %s\n", MAYBE_PAD, nameIReg(4,dst)); m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NOT, dst); } @@ -666,8 +714,9 @@ public: void orl_rr(RegisterID src, RegisterID dst) { - spew("orl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "orl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_OR_EvGv, src, dst); } @@ -685,7 +734,8 @@ public: void orl_ir(int imm, RegisterID dst) { - spew("orl $0x%x, %s", imm, nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "orl $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(4,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, dst); m_formatter.immediate8(imm); @@ -710,20 +760,23 @@ public: #if WTF_CPU_X86_64 void negq_r(RegisterID dst) { - spew("negq %s", nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "negq %s\n", MAYBE_PAD, nameIReg(8,dst)); m_formatter.oneByteOp64(OP_GROUP3_Ev, GROUP3_OP_NEG, dst); } void orq_rr(RegisterID src, RegisterID dst) { - spew("orq %s, %s", - nameIReg(8,src), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "orq %s, %s\n", MAYBE_PAD, + nameIReg(8,src), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_OR_EvGv, src, dst); } void orq_ir(int imm, RegisterID dst) { - spew("orq $0x%x, %s", imm, nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "orq $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(8,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_OR, dst); m_formatter.immediate8(imm); @@ -735,7 +788,8 @@ public: void notq_r(RegisterID dst) { - spew("notq %s", nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "notq %s\n", MAYBE_PAD, nameIReg(8,dst)); m_formatter.oneByteOp64(OP_GROUP3_Ev, GROUP3_OP_NOT, dst); } #else @@ -754,15 +808,17 @@ public: void subl_rr(RegisterID src, RegisterID dst) { - spew("subl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "subl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_SUB_EvGv, src, dst); } void subl_mr(int offset, RegisterID base, RegisterID dst) { - spew("subl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(4,base), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "subl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(4,base), nameIReg(4,dst)); m_formatter.oneByteOp(OP_SUB_GvEv, dst, base, offset); } @@ -774,7 +830,8 @@ public: void subl_ir(int imm, RegisterID dst) { - spew("subl $0x%x, %s", imm, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "subl $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(4, dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst); m_formatter.immediate8(imm); @@ -786,8 +843,9 @@ public: void subl_im(int imm, int offset, RegisterID base) { - spew("subl $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(4, base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "subl $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(4, base)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, base, offset); m_formatter.immediate8(imm); @@ -806,7 +864,8 @@ public: void subq_ir(int imm, RegisterID dst) { - spew("subq $0x%x, %s", imm, nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "subq $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(8,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst); m_formatter.immediate8(imm); @@ -831,8 +890,9 @@ public: void xorl_rr(RegisterID src, RegisterID dst) { - spew("xorl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "xorl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_XOR_EvGv, src, dst); } @@ -862,8 +922,9 @@ public: void xorl_ir(int imm, RegisterID dst) { - spew("xorl %d, %s", - imm, nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "xorl %d, %s\n", MAYBE_PAD, + imm, nameIReg(4,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst); m_formatter.immediate8(imm); @@ -876,15 +937,17 @@ public: #if WTF_CPU_X86_64 void xorq_rr(RegisterID src, RegisterID dst) { - spew("xorq %s, %s", - nameIReg(8,src), nameIReg(8, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "xorq %s, %s\n", MAYBE_PAD, + nameIReg(8,src), nameIReg(8, dst)); m_formatter.oneByteOp64(OP_XOR_EvGv, src, dst); } void xorq_ir(int imm, RegisterID dst) { - spew("xorq %d, %s", - imm, nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "xorq %d, %s\n", MAYBE_PAD, + imm, nameIReg(8,dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst); m_formatter.immediate8(imm); @@ -897,7 +960,8 @@ public: void sarl_i8r(int imm, RegisterID dst) { - spew("sarl $%d, %s", imm, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "sarl $%d, %s\n", MAYBE_PAD, imm, nameIReg(4, dst)); if (imm == 1) m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst); else { @@ -908,13 +972,15 @@ public: void sarl_CLr(RegisterID dst) { - spew("sarl %%cl, %s", nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "sarl %%cl, %s\n", MAYBE_PAD, nameIReg(4, dst)); m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SAR, dst); } void shrl_i8r(int imm, RegisterID dst) { - spew("shrl $%d, %s", imm, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "shrl $%d, %s\n", MAYBE_PAD, imm, nameIReg(4, dst)); if (imm == 1) m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SHR, dst); else { @@ -925,13 +991,15 @@ public: void shrl_CLr(RegisterID dst) { - spew("shrl %%cl, %s", nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "shrl %%cl, %s\n", MAYBE_PAD, nameIReg(4, dst)); m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHR, dst); } void shll_i8r(int imm, RegisterID dst) { - spew("shll $%d, %s", imm, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "shll $%d, %s\n", MAYBE_PAD, imm, nameIReg(4, dst)); if (imm == 1) m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SHL, dst); else { @@ -942,7 +1010,8 @@ public: void shll_CLr(RegisterID dst) { - spew("shll %%cl, %s", nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "shll %%cl, %s\n", MAYBE_PAD, nameIReg(4, dst)); m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHL, dst); } @@ -955,7 +1024,8 @@ public: void sarq_i8r(int imm, RegisterID dst) { - spew("sarq $%d, %s", imm, nameIReg(8, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "sarq $%d, %s\n", MAYBE_PAD, imm, nameIReg(8, dst)); if (imm == 1) m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst); else { @@ -966,7 +1036,8 @@ public: void shlq_i8r(int imm, RegisterID dst) { - spew("shlq $%d, %s", imm, nameIReg(8, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "shlq $%d, %s\n", MAYBE_PAD, imm, nameIReg(8, dst)); if (imm == 1) m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SHL, dst); else { @@ -977,7 +1048,8 @@ public: void shrq_i8r(int imm, RegisterID dst) { - spew("shrq $%d, %s", imm, nameIReg(8, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "shrq $%d, %s\n", MAYBE_PAD, imm, nameIReg(8, dst)); if (imm == 1) m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SHR, dst); else { @@ -989,29 +1061,31 @@ public: void imull_rr(RegisterID src, RegisterID dst) { - spew("imull %s, %s", nameIReg(4,src), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "imull %s, %s\n", MAYBE_PAD, nameIReg(4,src), nameIReg(4, dst)); m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, src); } void imull_mr(int offset, RegisterID base, RegisterID dst) { - spew("imull %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(4,base), nameIReg(4,dst)); + FIXME_INSN_PRINTING; m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, base, offset); } void imull_i32r(RegisterID src, int32_t value, RegisterID dst) { - spew("imull %d, %s, %s", - value, nameIReg(4, src), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "imull %d, %s, %s\n", + MAYBE_PAD, value, nameIReg(4, src), nameIReg(4, dst)); m_formatter.oneByteOp(OP_IMUL_GvEvIz, dst, src); m_formatter.immediate32(value); } void idivl_r(RegisterID dst) { - spew("idivl %s", - nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "idivl %s\n", MAYBE_PAD, + nameIReg(4, dst)); m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_IDIV, dst); } @@ -1019,28 +1093,32 @@ public: void cmpl_rr(RegisterID src, RegisterID dst) { - spew("cmpl %s, %s", - nameIReg(4, src), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl %s, %s\n", MAYBE_PAD, + nameIReg(4, src), nameIReg(4, dst)); m_formatter.oneByteOp(OP_CMP_EvGv, src, dst); } void cmpl_rm(RegisterID src, int offset, RegisterID base) { - spew("cmpl %s, %s0x%x(%s)", - nameIReg(4, src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl %s, %s0x%x(%s)\n", MAYBE_PAD, + nameIReg(4, src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp(OP_CMP_EvGv, src, base, offset); } void cmpl_mr(int offset, RegisterID base, RegisterID src) { - spew("cmpl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(4, base), nameIReg(src)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(4, base), nameIReg(src)); m_formatter.oneByteOp(OP_CMP_GvEv, src, base, offset); } void cmpl_ir(int imm, RegisterID dst) { - spew("cmpl $0x%x, %s", imm, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(4, dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, dst); m_formatter.immediate8(imm); @@ -1052,15 +1130,17 @@ public: void cmpl_ir_force32(int imm, RegisterID dst) { - spew("cmpl $0x%x, %s", imm, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl $0x%x, %s\n", MAYBE_PAD, imm, nameIReg(4, dst)); m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst); m_formatter.immediate32(imm); } void cmpl_im(int imm, int offset, RegisterID base) { - spew("cmpl $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(4,base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(4,base)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, offset); m_formatter.immediate8(imm); @@ -1084,8 +1164,9 @@ public: void cmpl_im(int imm, int offset, RegisterID base, RegisterID index, int scale) { - spew("cmpl %d, %d(%s,%s,%d)", - imm, offset, nameIReg(4,base), nameIReg(4,index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl %d, %d(%s,%s,%d)\n", MAYBE_PAD, + imm, offset, nameIReg(4,base), nameIReg(4,index), scale); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, index, scale, offset); m_formatter.immediate8(imm); @@ -1097,8 +1178,9 @@ public: void cmpl_im_force32(int imm, int offset, RegisterID base) { - spew("cmpl $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(4,base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpl $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(4,base)); m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, offset); m_formatter.immediate32(imm); } @@ -1106,29 +1188,33 @@ public: #if WTF_CPU_X86_64 void cmpq_rr(RegisterID src, RegisterID dst) { - spew("cmpq %s, %s", - nameIReg(8, src), nameIReg(8, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpq %s, %s\n", MAYBE_PAD, + nameIReg(8, src), nameIReg(8, dst)); m_formatter.oneByteOp64(OP_CMP_EvGv, src, dst); } void cmpq_rm(RegisterID src, int offset, RegisterID base) { - spew("cmpq %s, %d(%s)", - nameIReg(8, src), offset, nameIReg(8, base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpq %s, %d(%s)\n", MAYBE_PAD, + nameIReg(8, src), offset, nameIReg(8, base)); m_formatter.oneByteOp64(OP_CMP_EvGv, src, base, offset); } void cmpq_mr(int offset, RegisterID base, RegisterID src) { - spew("cmpq %d(%s), %s", - offset, nameIReg(8, base), nameIReg(8, src)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpq %d(%s), %s\n", MAYBE_PAD, + offset, nameIReg(8, base), nameIReg(8, src)); m_formatter.oneByteOp64(OP_CMP_GvEv, src, base, offset); } void cmpq_ir(int imm, RegisterID dst) { - spew("cmpq %d, %s", - imm, nameIReg(8, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmpq %d, %s\n", MAYBE_PAD, + imm, nameIReg(8, dst)); if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_CMP, dst); m_formatter.immediate8(imm); @@ -1170,7 +1256,7 @@ public: void cmpl_im(int imm, void* addr) { - spew("cmpl $0x%x, 0x%p", imm, addr); + FIXME_INSN_PRINTING; if (CAN_SIGN_EXTEND_8_32(imm)) { m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, addr); m_formatter.immediate8(imm); @@ -1204,30 +1290,34 @@ public: void testl_rr(RegisterID src, RegisterID dst) { - spew("testl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "testl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_TEST_EvGv, src, dst); } void testb_rr(RegisterID src, RegisterID dst) { - spew("testb %s, %s", - nameIReg(1,src), nameIReg(1,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "testb %s, %s\n", MAYBE_PAD, + nameIReg(1,src), nameIReg(1,dst)); m_formatter.oneByteOp(OP_TEST_EbGb, src, dst); } void testl_i32r(int imm, RegisterID dst) { - spew("testl $0x%x, %s", - imm, nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "testl $0x%x, %s\n", MAYBE_PAD, + imm, nameIReg(dst)); m_formatter.oneByteOp(OP_GROUP3_EvIz, GROUP3_OP_TEST, dst); m_formatter.immediate32(imm); } void testl_i32m(int imm, int offset, RegisterID base) { - spew("testl $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "testl $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp(OP_GROUP3_EvIz, GROUP3_OP_TEST, base, offset); m_formatter.immediate32(imm); } @@ -1254,8 +1344,9 @@ public: #if WTF_CPU_X86_64 void testq_rr(RegisterID src, RegisterID dst) { - spew("testq %s, %s", - nameIReg(8,src), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "testq %s, %s\n", MAYBE_PAD, + nameIReg(8,src), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_TEST_EvGv, src, dst); } @@ -1268,8 +1359,9 @@ public: void testq_i32m(int imm, int offset, RegisterID base) { - spew("testq $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "testq $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp64(OP_GROUP3_EvIz, GROUP3_OP_TEST, base, offset); m_formatter.immediate32(imm); } @@ -1291,16 +1383,18 @@ public: void testb_i8r(int imm, RegisterID dst) { - spew("testb $0x%x, %s", - imm, nameIReg(1,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "testb $0x%x, %s\n", MAYBE_PAD, + imm, nameIReg(1,dst)); m_formatter.oneByteOp8(OP_GROUP3_EbIb, GROUP3_OP_TEST, dst); m_formatter.immediate8(imm); } void setCC_r(Condition cond, RegisterID dst) { - spew("set%s %s", - nameCC(cond), nameIReg(1,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "set%s %s\n", MAYBE_PAD, + nameCC(cond), nameIReg(1,dst)); m_formatter.twoByteOp8(setccOpcode(cond), (GroupOpcodeID)0, dst); } @@ -1332,45 +1426,51 @@ public: void cdq() { - spew("cdq "); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cdq \n", MAYBE_PAD); m_formatter.oneByteOp(OP_CDQ); } void xchgl_rr(RegisterID src, RegisterID dst) { - spew("xchgl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "xchgl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_XCHG_EvGv, src, dst); } #if WTF_CPU_X86_64 void xchgq_rr(RegisterID src, RegisterID dst) { - spew("xchgq %s, %s", - nameIReg(8,src), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "xchgq %s, %s\n", MAYBE_PAD, + nameIReg(8,src), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_XCHG_EvGv, src, dst); } #endif void movl_rr(RegisterID src, RegisterID dst) { - spew("movl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.oneByteOp(OP_MOV_EvGv, src, dst); } void movw_rm(RegisterID src, int offset, RegisterID base) { - spew("movw %s, %s0x%x(%s)", - nameIReg(2,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movw %s, %s0x%x(%s)\n", MAYBE_PAD, + nameIReg(2,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.prefix(PRE_OPERAND_SIZE); m_formatter.oneByteOp(OP_MOV_EvGv, src, base, offset); } void movl_rm(RegisterID src, int offset, RegisterID base) { - spew("movl %s, %s0x%x(%s)", - nameIReg(4,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl %s, %s0x%x(%s)\n", MAYBE_PAD, + nameIReg(4,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp(OP_MOV_EvGv, src, base, offset); } @@ -1382,16 +1482,18 @@ public: void movw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale) { - spew("movw %s, %d(%s,%s,%d)", - nameIReg(2, src), offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movw %s, %d(%s,%s,%d)\n", MAYBE_PAD, + nameIReg(2, src), offset, nameIReg(base), nameIReg(index), scale); m_formatter.prefix(PRE_OPERAND_SIZE); m_formatter.oneByteOp(OP_MOV_EvGv, src, base, index, scale, offset); } void movl_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale) { - spew("movl %s, %d(%s,%s,%d)", - nameIReg(4, src), offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl %s, %d(%s,%s,%d)\n", MAYBE_PAD, + nameIReg(4, src), offset, nameIReg(base), nameIReg(index), scale); m_formatter.oneByteOp(OP_MOV_EvGv, src, base, index, scale, offset); } @@ -1408,8 +1510,9 @@ public: void movl_mr(int offset, RegisterID base, RegisterID dst) { - spew("movl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); m_formatter.oneByteOp(OP_MOV_GvEv, dst, base, offset); } @@ -1421,39 +1524,44 @@ public: void movl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("movl %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(4, dst)); m_formatter.oneByteOp(OP_MOV_GvEv, dst, base, index, scale, offset); } void movl_i32r(int imm, RegisterID dst) { - spew("movl $0x%x, %s", - imm, nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl $0x%x, %s\n", MAYBE_PAD, + imm, nameIReg(dst)); m_formatter.oneByteOp(OP_MOV_EAXIv, dst); m_formatter.immediate32(imm); } void movb_i8m(int imm, int offset, RegisterID base) { - spew("movb $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movb $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp(OP_GROUP11_EvIb, GROUP11_MOV, base, offset); m_formatter.immediate8(imm); } void movb_i8m(int imm, int offset, RegisterID base, RegisterID index, int scale) { - spew("movb $0x%x, %d(%s,%s,%d)", - imm, offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movb $0x%x, %d(%s,%s,%d)\n", MAYBE_PAD, + imm, offset, nameIReg(base), nameIReg(index), scale); m_formatter.oneByteOp(OP_GROUP11_EvIb, GROUP11_MOV, base, index, scale, offset); m_formatter.immediate8(imm); } void movw_i16m(int imm, int offset, RegisterID base) { - spew("movw $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movw $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.prefix(PRE_OPERAND_SIZE); m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, base, offset); m_formatter.immediate16(imm); @@ -1461,16 +1569,18 @@ public: void movl_i32m(int imm, int offset, RegisterID base) { - spew("movl $0x%x, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl $0x%x, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, base, offset); m_formatter.immediate32(imm); } void movw_i16m(int imm, int offset, RegisterID base, RegisterID index, int scale) { - spew("movw $0x%x, %d(%s,%s,%d)", - imm, offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movw $0x%x, %d(%s,%s,%d)\n", MAYBE_PAD, + imm, offset, nameIReg(base), nameIReg(index), scale); m_formatter.prefix(PRE_OPERAND_SIZE); m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, base, index, scale, offset); m_formatter.immediate16(imm); @@ -1478,8 +1588,9 @@ public: void movl_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale) { - spew("movl $0x%x, %d(%s,%s,%d)", - imm, offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl $0x%x, %d(%s,%s,%d)\n", MAYBE_PAD, + imm, offset, nameIReg(base), nameIReg(index), scale); m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, base, index, scale, offset); m_formatter.immediate32(imm); } @@ -1498,15 +1609,17 @@ public: #if WTF_CPU_X86_64 void movq_rr(RegisterID src, RegisterID dst) { - spew("movq %s, %s", - nameIReg(8,src), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq %s, %s\n", MAYBE_PAD, + nameIReg(8,src), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_MOV_EvGv, src, dst); } void movq_rm(RegisterID src, int offset, RegisterID base) { - spew("movq %s, %s0x%x(%s)", - nameIReg(8,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq %s, %s0x%x(%s)\n", MAYBE_PAD, + nameIReg(8,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp64(OP_MOV_EvGv, src, base, offset); } @@ -1518,8 +1631,9 @@ public: void movq_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale) { - spew("movq %s, %s0x%x(%s)", - nameIReg(8,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq %s, %s0x%x(%s)\n", MAYBE_PAD, + nameIReg(8,src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp64(OP_MOV_EvGv, src, base, index, scale, offset); } @@ -1539,8 +1653,9 @@ public: void movq_mr(int offset, RegisterID base, RegisterID dst) { - spew("movq %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_MOV_GvEv, dst, base, offset); } @@ -1552,46 +1667,52 @@ public: void movq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("movq %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(8,dst)); m_formatter.oneByteOp64(OP_MOV_GvEv, dst, base, index, scale, offset); } void leaq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("leaq %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(8,dst)), + js::JaegerSpew(js::JSpew_Insns, + IPFX "leaq %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(8,dst)), m_formatter.oneByteOp64(OP_LEA, dst, base, index, scale, offset); } void movq_i32m(int imm, int offset, RegisterID base) { - spew("movq $%d, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq $%d, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, base, offset); m_formatter.immediate32(imm); } void movq_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale) { - spew("movq $%d, %s0x%x(%s)", - imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq $%d, %s0x%x(%s)\n", MAYBE_PAD, + imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, base, index, scale, offset); m_formatter.immediate32(imm); } void movq_i64r(int64_t imm, RegisterID dst) { - spew("movabsq $0x%llx, %s", - (unsigned long long int)imm, nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movabsq $0x%llx, %s\n", MAYBE_PAD, + (unsigned long long int)imm, nameIReg(8,dst)); m_formatter.oneByteOp64(OP_MOV_EAXIv, dst); m_formatter.immediate64(imm); } void movsxd_rr(RegisterID src, RegisterID dst) { - spew("movsxd %s, %s", - nameIReg(4, src), nameIReg(8, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movsxd %s, %s\n", MAYBE_PAD, + nameIReg(4, src), nameIReg(8, dst)); m_formatter.oneByteOp64(OP_MOVSXD_GvEv, dst, src); } @@ -1599,8 +1720,9 @@ public: #else void movl_rm(RegisterID src, void* addr) { - spew("movl %s, 0(%p)", - nameIReg(4, src), addr); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl %s, 0(%p)\n", MAYBE_PAD, + nameIReg(4, src), addr); if (src == X86Registers::eax) movl_EAXm(addr); else @@ -1609,8 +1731,9 @@ public: void movl_mr(void* addr, RegisterID dst) { - spew("movl 0(%p), %s", - addr, nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movl 0(%p), %s\n", MAYBE_PAD, + addr, nameIReg(4, dst)); if (dst == X86Registers::eax) movl_mEAX(addr); else @@ -1627,71 +1750,81 @@ public: void movb_rm(RegisterID src, int offset, RegisterID base) { - spew("movb %s, %s0x%x(%s)", - nameIReg(1, src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movb %s, %s0x%x(%s)\n", MAYBE_PAD, + nameIReg(1, src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp8(OP_MOV_EbGv, src, base, offset); } void movb_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale) { - spew("movb %s, %d(%s,%s,%d)", - nameIReg(1, src), offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movb %s, %d(%s,%s,%d)\n", MAYBE_PAD, + nameIReg(1, src), offset, nameIReg(base), nameIReg(index), scale); m_formatter.oneByteOp8(OP_MOV_EbGv, src, base, index, scale, offset); } void movzbl_mr(int offset, RegisterID base, RegisterID dst) { - spew("movzbl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movzbl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); m_formatter.twoByteOp(OP2_MOVZX_GvEb, dst, base, offset); } void movzbl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("movzbl %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movzbl %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); m_formatter.twoByteOp(OP2_MOVZX_GvEb, dst, base, index, scale, offset); } void movxbl_mr(int offset, RegisterID base, RegisterID dst) { - spew("movxbl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movxbl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); m_formatter.twoByteOp(OP2_MOVSX_GvEb, dst, base, offset); } void movxbl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("movxbl %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movxbl %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); m_formatter.twoByteOp(OP2_MOVSX_GvEb, dst, base, index, scale, offset); } void movzwl_mr(int offset, RegisterID base, RegisterID dst) { - spew("movzwl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movzwl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); m_formatter.twoByteOp(OP2_MOVZX_GvEw, dst, base, offset); } void movzwl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("movzwl %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movzwl %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); m_formatter.twoByteOp(OP2_MOVZX_GvEw, dst, base, index, scale, offset); } void movxwl_mr(int offset, RegisterID base, RegisterID dst) { - spew("movxwl %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movxwl %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, dst)); m_formatter.twoByteOp(OP2_MOVSX_GvEw, dst, base, offset); } void movxwl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("movxwl %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movxwl %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); m_formatter.twoByteOp(OP2_MOVSX_GvEw, dst, base, index, scale, offset); } @@ -1700,29 +1833,33 @@ public: // In 64-bit, this may cause an unnecessary REX to be planted (if the dst register // is in the range ESP-EDI, and the src would not have required a REX). Unneeded // REX prefixes are defined to be silently ignored by the processor. - spew("movzbl %s, %s", - nameIReg(4,src), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movzbl %s, %s\n", MAYBE_PAD, + nameIReg(4,src), nameIReg(4,dst)); m_formatter.twoByteOp8(OP2_MOVZX_GvEb, dst, src); } void leal_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst) { - spew("leal %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "leal %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameIReg(dst)); m_formatter.oneByteOp(OP_LEA, dst, base, index, scale, offset); } void leal_mr(int offset, RegisterID base, RegisterID dst) { - spew("leal %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "leal %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4,dst)); m_formatter.oneByteOp(OP_LEA, dst, base, offset); } #if WTF_CPU_X86_64 void leaq_mr(int offset, RegisterID base, RegisterID dst) { - spew("leaq %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(8,dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "leaq %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(8,dst)); m_formatter.oneByteOp64(OP_LEA, dst, base, offset); } #endif @@ -1733,7 +1870,8 @@ public: { m_formatter.oneByteOp(OP_CALL_rel32); JmpSrc r = m_formatter.immediateRel32(); - spew("call ((%d))", r.m_offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "call ((%d))\n", MAYBE_PAD, r.m_offset); return r; } @@ -1741,14 +1879,16 @@ public: { m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_CALLN, dst); JmpSrc r = JmpSrc(m_formatter.size()); - spew("call *%s", nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "call *%s\n", MAYBE_PAD, nameIReg(dst)); return r; } void call_m(int offset, RegisterID base) { - spew("call %s0x%x(%s)", - PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "call %s0x%x(%s)\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_CALLN, base, offset); } @@ -1759,7 +1899,8 @@ public: { m_formatter.oneByteOp(OP_CMP_EAXIv); JmpSrc r = m_formatter.immediateRel32(); - spew("cmp eax, ((%d))", r.m_offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cmp eax, ((%d))\n", MAYBE_PAD, r.m_offset); return r; } @@ -1767,7 +1908,8 @@ public: { m_formatter.oneByteOp(OP_JMP_rel32); JmpSrc r = m_formatter.immediateRel32(); - spew("jmp ((%d))", r.m_offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "jmp ((%d))\n", MAYBE_PAD, r.m_offset); return r; } @@ -1776,8 +1918,9 @@ public: // really shouldn't wrap this as a Jump, since it can't be linked. :-/ JmpSrc jmp_r(RegisterID dst) { - spew("jmp ((%s))", - nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "jmp ((%s))\n", MAYBE_PAD, + nameIReg(dst)); m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_JMPN, dst); return JmpSrc(m_formatter.size()); } @@ -1789,8 +1932,9 @@ public: } void jmp_m(int offset, RegisterID base, RegisterID index, int scale) { - spew("jmp ((%d(%s,%s,%d)))", - offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "jmp ((%d(%s,%s,%d)))\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale); m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_JMPN, base, index, scale, offset); } @@ -1909,8 +2053,9 @@ public: { m_formatter.twoByteOp(jccRel32(cond)); JmpSrc r = m_formatter.immediateRel32(); - spew("j%s ((%d))", - nameCC(cond), r.m_offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "j%s ((%d))\n", MAYBE_PAD, + nameCC(cond), r.m_offset); return r; } @@ -1918,24 +2063,27 @@ public: void pcmpeqw_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("pcmpeqw %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "pcmpeqw %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_PCMPEQW, (RegisterID)dst, (RegisterID)src); /* right order ? */ } void addsd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("addsd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addsd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)src); } void addsd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("addsd %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addsd %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, base, offset); } @@ -1943,8 +2091,9 @@ public: #if !WTF_CPU_X86_64 void addsd_mr(const void* address, XMMRegisterID dst) { - spew("addsd %p, %s", - address, nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "addsd %p, %s\n", MAYBE_PAD, + address, nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, address); } @@ -1952,24 +2101,27 @@ public: void cvtss2sd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("cvtps2pd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvtps2pd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F3); m_formatter.twoByteOp(OP2_CVTSS2SD_VsdEd, (RegisterID)dst, (RegisterID)src); } void cvtsd2ss_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("cvtps2pd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvtps2pd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_CVTSD2SS_VsdEd, (RegisterID)dst, (RegisterID)src); } void cvtsi2sd_rr(RegisterID src, XMMRegisterID dst) { - spew("cvtsi2sd %s, %s", - nameIReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvtsi2sd %s, %s\n", MAYBE_PAD, + nameIReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, src); } @@ -1977,8 +2129,9 @@ public: #if WTF_CPU_X86_64 void cvtsq2sd_rr(RegisterID src, XMMRegisterID dst) { - spew("cvtsq2sd %s, %s", - nameIReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvtsq2sd %s, %s\n", MAYBE_PAD, + nameIReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp64(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, src); } @@ -1986,16 +2139,18 @@ public: void cvtsi2sd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("cvtsi2sd %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvtsi2sd %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, base, offset); } void cvtsi2sd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - spew("cvtsi2sd %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvtsi2sd %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, base, index, scale, offset); } @@ -2003,8 +2158,9 @@ public: #if !WTF_CPU_X86_64 void cvtsi2sd_mr(void* address, XMMRegisterID dst) { - spew("cvtsi2sd %p, %s", - address, nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvtsi2sd %p, %s\n", MAYBE_PAD, + address, nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, address); } @@ -2012,8 +2168,9 @@ public: void cvttsd2si_rr(XMMRegisterID src, RegisterID dst) { - spew("cvttsd2si %s, %s", - nameFPReg(src), nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvttsd2si %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameIReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_CVTTSD2SI_GdWsd, dst, (RegisterID)src); } @@ -2021,8 +2178,9 @@ public: #if WTF_CPU_X86_64 void cvttsd2sq_rr(XMMRegisterID src, RegisterID dst) { - spew("cvttsd2sq %s, %s", - nameFPReg(src), nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "cvttsd2sq %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameIReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp64(OP2_CVTTSD2SI_GdWsd, dst, (RegisterID)src); } @@ -2030,23 +2188,26 @@ public: void unpcklps_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("unpcklps %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "unpcklps %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.twoByteOp(OP2_UNPCKLPS_VsdWsd, (RegisterID)dst, (RegisterID)src); } void movd_rr(RegisterID src, XMMRegisterID dst) { - spew("movd %s, %s", - nameIReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movd %s, %s\n", MAYBE_PAD, + nameIReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_MOVD_VdEd, (RegisterID)dst, src); } void psrldq_rr(XMMRegisterID dest, int shift) { - spew("psrldq %s, %d", - nameFPReg(dest), shift); + js::JaegerSpew(js::JSpew_Insns, + IPFX "psrldq %s, %d\n", MAYBE_PAD, + nameFPReg(dest), shift); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)3, (RegisterID)dest); m_formatter.immediate8(shift); @@ -2054,8 +2215,9 @@ public: void psllq_rr(XMMRegisterID dest, int shift) { - spew("psllq %s, %d", - nameFPReg(dest), shift); + js::JaegerSpew(js::JSpew_Insns, + IPFX "psllq %s, %d\n", MAYBE_PAD, + nameFPReg(dest), shift); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)6, (RegisterID)dest); m_formatter.immediate8(shift); @@ -2063,8 +2225,9 @@ public: void psrlq_rr(XMMRegisterID dest, int shift) { - spew("psrlq %s, %d", - nameFPReg(dest), shift); + js::JaegerSpew(js::JSpew_Insns, + IPFX "psrlq %s, %d\n", MAYBE_PAD, + nameFPReg(dest), shift); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)2, (RegisterID)dest); m_formatter.immediate8(shift); @@ -2072,23 +2235,26 @@ public: void movmskpd_rr(XMMRegisterID src, RegisterID dst) { - spew("movmskpd %s, %s", - nameFPReg(src), nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movmskpd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameIReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_MOVMSKPD_EdVd, dst, (RegisterID)src); } void ptest_rr(XMMRegisterID lhs, XMMRegisterID rhs) { - spew("ptest %s, %s", - nameFPReg(lhs), nameFPReg(rhs)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "ptest %s, %s\n", MAYBE_PAD, + nameFPReg(lhs), nameFPReg(rhs)); m_formatter.prefix(PRE_SSE_66); m_formatter.threeByteOp(OP3_PTEST_VdVd, ESCAPE_PTEST, (RegisterID)rhs, (RegisterID)lhs); } void movd_rr(XMMRegisterID src, RegisterID dst) { - spew("movd %s, %s", - nameFPReg(src), nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameIReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_MOVD_EdVd, (RegisterID)src, dst); } @@ -2096,16 +2262,18 @@ public: #if WTF_CPU_X86_64 void movq_rr(XMMRegisterID src, RegisterID dst) { - spew("movq %s, %s", - nameFPReg(src), nameIReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameIReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp64(OP2_MOVD_EdVd, (RegisterID)src, dst); } void movq_rr(RegisterID src, XMMRegisterID dst) { - spew("movq %s, %s", - nameIReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movq %s, %s\n", MAYBE_PAD, + nameIReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp64(OP2_MOVD_VdEd, (RegisterID)dst, src); } @@ -2113,72 +2281,81 @@ public: void movsd_rm(XMMRegisterID src, int offset, RegisterID base) { - spew("movsd %s, %s0x%x(%s)", - nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movsd %s, %s0x%x(%s)\n", MAYBE_PAD, + nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, (RegisterID)src, base, offset); } void movss_rm(XMMRegisterID src, int offset, RegisterID base) { - spew("movss %s, %s0x%x(%s)", - nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movss %s, %s0x%x(%s)\n", MAYBE_PAD, + nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.prefix(PRE_SSE_F3); m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, (RegisterID)src, base, offset); } void movss_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("movss %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movss %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F3); m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, base, offset); } void movsd_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale) { - spew("movsd %s, %d(%s,%s,%d)", - nameFPReg(src), offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movsd %s, %d(%s,%s,%d)\n", MAYBE_PAD, + nameFPReg(src), offset, nameIReg(base), nameIReg(index), scale); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, (RegisterID)src, base, index, scale, offset); } void movss_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale) { - spew("movss %s, %d(%s,%s,%d)", - nameFPReg(src), offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movss %s, %d(%s,%s,%d)\n", MAYBE_PAD, + nameFPReg(src), offset, nameIReg(base), nameIReg(index), scale); m_formatter.prefix(PRE_SSE_F3); m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, (RegisterID)src, base, index, scale, offset); } void movss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - spew("movss %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movss %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F3); m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, base, index, scale, offset); } void movsd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("movsd %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movsd %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, base, offset); } void movsd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - spew("movsd %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movsd %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, base, index, scale, offset); } void movsd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("movsd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movsd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, (RegisterID)src); } @@ -2186,8 +2363,9 @@ public: #if !WTF_CPU_X86_64 void movsd_mr(const void* address, XMMRegisterID dst) { - spew("movsd %p, %s", - address, nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movsd %p, %s\n", MAYBE_PAD, + address, nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, address); } @@ -2195,48 +2373,54 @@ public: void movdqa_rm(XMMRegisterID src, int offset, RegisterID base) { - spew("movdqa %s, %s0x%x(%s)", - nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movdqa %s, %s0x%x(%s)\n", MAYBE_PAD, + nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_MOVDQA_WsdVsd, (RegisterID)src, base, offset); } void movdqa_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale) { - spew("movdqa %s, %d(%s,%s,%d)", - nameFPReg(src), offset, nameIReg(base), nameIReg(index), scale); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movdqa %s, %d(%s,%s,%d)\n", MAYBE_PAD, + nameFPReg(src), offset, nameIReg(base), nameIReg(index), scale); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_MOVDQA_WsdVsd, (RegisterID)src, base, index, scale, offset); } void movdqa_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("movdqa %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movdqa %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_MOVDQA_VsdWsd, (RegisterID)dst, base, offset); } void movdqa_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst) { - spew("movdqa %d(%s,%s,%d), %s", - offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "movdqa %d(%s,%s,%d), %s\n", MAYBE_PAD, + offset, nameIReg(base), nameIReg(index), scale, nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_MOVDQA_VsdWsd, (RegisterID)dst, base, index, scale, offset); } void mulsd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("mulsd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "mulsd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, (RegisterID)src); } void mulsd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("mulsd %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "mulsd %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, base, offset); } @@ -2251,88 +2435,99 @@ public: void subsd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("subsd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "subsd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)src); } void subsd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("subsd %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "subsd %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, base, offset); } void ucomisd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("ucomisd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "ucomisd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)dst, (RegisterID)src); } void ucomisd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("ucomisd %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "ucomisd %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)dst, base, offset); } void divsd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("divsd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "divsd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_DIVSD_VsdWsd, (RegisterID)dst, (RegisterID)src); } void divsd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("divsd %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "divsd %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_DIVSD_VsdWsd, (RegisterID)dst, base, offset); } void xorpd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("xorpd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "xorpd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_XORPD_VpdWpd, (RegisterID)dst, (RegisterID)src); } void orpd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("orpd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "orpd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_ORPD_VpdWpd, (RegisterID)dst, (RegisterID)src); } void andpd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("andpd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "andpd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.twoByteOp(OP2_ANDPD_VpdWpd, (RegisterID)dst, (RegisterID)src); } void sqrtsd_rr(XMMRegisterID src, XMMRegisterID dst) { - spew("sqrtsd %s, %s", - nameFPReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "sqrtsd %s, %s\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_F2); m_formatter.twoByteOp(OP2_SQRTSD_VsdWsd, (RegisterID)dst, (RegisterID)src); } void roundsd_rr(XMMRegisterID src, XMMRegisterID dst, RoundingMode mode) { - spew("roundsd %s, %s, %d", - nameFPReg(src), nameFPReg(dst), (int)mode); + js::JaegerSpew(js::JSpew_Insns, + IPFX "roundsd %s, %s, %d\n", MAYBE_PAD, + nameFPReg(src), nameFPReg(dst), (int)mode); m_formatter.prefix(PRE_SSE_66); m_formatter.threeByteOp(OP3_ROUNDSD_VsdWsd, ESCAPE_ROUNDSD, (RegisterID)dst, (RegisterID)src); m_formatter.immediate8(mode); @@ -2340,8 +2535,9 @@ public: void pinsrd_rr(RegisterID src, XMMRegisterID dst) { - spew("pinsrd $1, %s, %s", - nameIReg(src), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "pinsrd $1, %s, %s\n", MAYBE_PAD, + nameIReg(src), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.threeByteOp(OP3_PINSRD_VsdWsd, ESCAPE_PINSRD, (RegisterID)dst, (RegisterID)src); m_formatter.immediate8(0x01); // the $1 @@ -2349,9 +2545,10 @@ public: void pinsrd_mr(int offset, RegisterID base, XMMRegisterID dst) { - spew("pinsrd $1, %s0x%x(%s), %s", - PRETTY_PRINT_OFFSET(offset), - nameIReg(base), nameFPReg(dst)); + js::JaegerSpew(js::JSpew_Insns, + IPFX "pinsrd $1, %s0x%x(%s), %s\n", MAYBE_PAD, + PRETTY_PRINT_OFFSET(offset), + nameIReg(base), nameFPReg(dst)); m_formatter.prefix(PRE_SSE_66); m_formatter.threeByteOp(OP3_PINSRD_VsdWsd, ESCAPE_PINSRD, (RegisterID)dst, base, offset); m_formatter.immediate8(0x01); // the $1 @@ -2361,20 +2558,21 @@ public: void int3() { - spew("int3"); + js::JaegerSpew(js::JSpew_Insns, IPFX "int3\n", MAYBE_PAD); m_formatter.oneByteOp(OP_INT3); } void ret() { - spew("ret"); + js::JaegerSpew(js::JSpew_Insns, IPFX "ret\n", MAYBE_PAD); m_formatter.oneByteOp(OP_RET); } void ret(int imm) { - spew("ret %d", - imm); + js::JaegerSpew(js::JSpew_Insns, + IPFX "ret %d\n", MAYBE_PAD, + imm); m_formatter.oneByteOp(OP_RET_Iz); m_formatter.immediate16(imm); } @@ -2388,13 +2586,13 @@ public: #if WTF_CPU_X86 void pusha() { - spew("pusha"); + js::JaegerSpew(js::JSpew_Insns, IPFX "pusha\n", MAYBE_PAD); m_formatter.oneByteOp(OP_PUSHA); } void popa() { - spew("popa"); + js::JaegerSpew(js::JSpew_Insns, IPFX "popa\n", MAYBE_PAD); m_formatter.oneByteOp(OP_POPA); } #endif @@ -2404,7 +2602,8 @@ public: JmpDst label() { JmpDst r = JmpDst(m_formatter.size()); - spew("#label ((%d))", r.m_offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "#label ((%d))\n", MAYBE_PAD, r.m_offset); return r; } @@ -2414,6 +2613,7 @@ public: static JmpDst labelFor(JmpSrc jump, intptr_t offset = 0) { + FIXME_INSN_PRINTING; return JmpDst(jump.m_offset + offset); } @@ -2467,8 +2667,9 @@ public: if (oom()) return; - spew("##link ((%d)) jumps to ((%d))", - from.m_offset, to.m_offset); + js::JaegerSpew(js::JSpew_Insns, + IPFX "##link ((%d)) jumps to ((%d))\n", MAYBE_PAD, + from.m_offset, to.m_offset); char* code = reinterpret_cast(m_formatter.data()); setRel32(code + from.m_offset, code + to.m_offset); } @@ -2477,8 +2678,9 @@ public: { ASSERT(from.m_offset != -1); - staticSpew("##link ((%d)) jumps to ((%p))", - from.m_offset, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##link ((%d)) jumps to ((%p))\n", + from.m_offset, to); setRel32(reinterpret_cast(code) + from.m_offset, to); } @@ -2486,7 +2688,7 @@ public: { ASSERT(from.m_offset != -1); - staticSpew("##linkCall"); + FIXME_INSN_PRINTING; setRel32(reinterpret_cast(code) + from.m_offset, to); } @@ -2494,14 +2696,15 @@ public: { ASSERT(where.m_offset != -1); - staticSpew("##linkPointer"); + FIXME_INSN_PRINTING; setPointer(reinterpret_cast(code) + where.m_offset, value); } static void relinkJump(void* from, void* to) { - staticSpew("##relinkJump ((from=%p)) ((to=%p))", - from, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##relinkJump ((from=%p)) ((to=%p))\n", + from, to); setRel32(from, to); } @@ -2513,29 +2716,33 @@ public: static void relinkCall(void* from, void* to) { - staticSpew("##relinkCall ((from=%p)) ((to=%p))", - from, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##relinkCall ((from=%p)) ((to=%p))\n", + from, to); setRel32(from, to); } static void repatchInt32(void* where, int32_t value) { - staticSpew("##relinkInt32 ((where=%p)) ((value=%d))", - where, value); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##relinkInt32 ((where=%p)) ((value=%d))\n", + where, value); setInt32(where, value); } static void repatchPointer(void* where, void* value) { - staticSpew("##repatchPtr ((where=%p)) ((value=%p))", - where, value); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##repatchPtr ((where=%p)) ((value=%p))\n", + where, value); setPointer(where, value); } static void repatchLoadPtrToLEA(void* where) { - staticSpew("##repatchLoadPtrToLEA ((where=%p))", - where); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##repatchLoadPtrToLEA ((where=%p))\n", + where); #if WTF_CPU_X86_64 // On x86-64 pointer memory accesses require a 64-bit operand, and as such a REX prefix. @@ -2547,8 +2754,9 @@ public: static void repatchLEAToLoadPtr(void* where) { - staticSpew("##repatchLEAToLoadPtr ((where=%p))", - where); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##repatchLEAToLoadPtr ((where=%p))\n", + where); #if WTF_CPU_X86_64 // On x86-64 pointer memory accesses require a 64-bit operand, and as such a REX prefix. // Skip over the prefix byte. @@ -2611,7 +2819,8 @@ public: JS_CRASH(0xC0DE); #undef JS_CRASH - staticSpew("##setRel32 ((from=%p)) ((to=%p))", from, to); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##setRel32 ((from=%p)) ((to=%p))\n", from, to); setInt32(from, offset); } @@ -2633,7 +2842,8 @@ public: static void setPointer(void* where, const void* value) { - staticSpew("##setPtr ((where=%p)) ((value=%p))", where, value); + js::JaegerSpew(js::JSpew_Insns, + ISPFX "##setPtr ((where=%p)) ((value=%p))\n", where, value); reinterpret_cast(where)[-1] = value; } diff --git a/js/src/ion/C1Spewer.h b/js/src/ion/C1Spewer.h index 992c4fd8b4a..f842562fe73 100644 --- a/js/src/ion/C1Spewer.h +++ b/js/src/ion/C1Spewer.h @@ -10,6 +10,8 @@ #ifndef jsion_c1spewer_h__ #define jsion_c1spewer_h__ +#include "jscntxt.h" + namespace js { namespace ion { diff --git a/js/src/ion/CodeGenerator.cpp b/js/src/ion/CodeGenerator.cpp index 736d67dbd4e..ad886174dc6 100644 --- a/js/src/ion/CodeGenerator.cpp +++ b/js/src/ion/CodeGenerator.cpp @@ -1457,7 +1457,6 @@ CodeGenerator::generateBody() printer.construct(GetIonContext()->cx); if (!printer.ref().init()) return false; - masm.setPrinter(printer.addr()); } for (; iter != current->end(); iter++) { @@ -1476,10 +1475,8 @@ CodeGenerator::generateBody() if (masm.oom()) return false; - if (counts) { + if (counts) counts->block(i).setCode(printer.ref().string()); - masm.setPrinter(NULL); - } } JS_ASSERT(pushedArgumentSlots_.empty()); diff --git a/js/src/ion/arm/Assembler-arm.h b/js/src/ion/arm/Assembler-arm.h index b7545c37f4a..a853ad9feee 100644 --- a/js/src/ion/arm/Assembler-arm.h +++ b/js/src/ion/arm/Assembler-arm.h @@ -1269,10 +1269,6 @@ class Assembler static const uint32 * getPtr32Target(Iter *iter, Register *dest = NULL, RelocStyle *rs = NULL); bool oom() const; - - void setPrinter(Sprinter *sp) { - } - private: bool isFinished; public: diff --git a/js/src/ion/arm/Trampoline-arm.cpp b/js/src/ion/arm/Trampoline-arm.cpp index d7390a0f992..a86104dd646 100644 --- a/js/src/ion/arm/Trampoline-arm.cpp +++ b/js/src/ion/arm/Trampoline-arm.cpp @@ -5,12 +5,12 @@ * License, v. 2.0. If a copy of the MPL was not distributed with this * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ +#include "ion/IonSpewer.h" #include "jscompartment.h" #include "assembler/assembler/MacroAssembler.h" #include "ion/IonCompartment.h" #include "ion/IonLinker.h" #include "ion/IonFrames.h" -#include "ion/IonSpewer.h" #include "ion/Bailouts.h" #include "ion/VMFunctions.h" diff --git a/js/src/ion/shared/Assembler-x86-shared.h b/js/src/ion/shared/Assembler-x86-shared.h index 31f6c313e1a..9aff16b43e3 100644 --- a/js/src/ion/shared/Assembler-x86-shared.h +++ b/js/src/ion/shared/Assembler-x86-shared.h @@ -128,10 +128,6 @@ class AssemblerX86Shared dataRelocations_.oom(); } - void setPrinter(Sprinter *sp) { - masm.setPrinter(sp); - } - void executableCopy(void *buffer); void processDeferredData(IonCode *code, uint8 *data); void processCodeLabels(IonCode *code); diff --git a/js/src/methodjit/Logging.h b/js/src/methodjit/Logging.h index c83797edba5..9db6c0aec03 100644 --- a/js/src/methodjit/Logging.h +++ b/js/src/methodjit/Logging.h @@ -85,11 +85,6 @@ struct Profiler { #else -static inline bool IsJaegerSpewChannelActive(JaegerSpewChannel channel) -{ - return false; -} - static inline void JaegerSpew(JaegerSpewChannel channel, const char *fmt, ...) { }