Commit Graph

915366 Commits

Author SHA1 Message Date
Bjorn Andersson 72f039db49 phy: qcom-qmp: Ensure register indirection arrays initialized
It's possible that struct qmp_phy_cfg->regs references an array that is
smaller than the possible register lookups that is going to be
performed, with the resulting out-of-bounds read resulting in undefined
behavior.

One such example is when during qcom_qmp_phy_com_init() performs a
qphy_setbits() on entry QPHY_PCS_POWER_DOWN_CONTROL (i.e. 17) with
msm8996_ufsphy_regs_layout only being 12 entries long.

Solve this by inflating all "regs_layout" arrays to ensure that any
remaining entries are zero-initialized, as expected by the code.

Fixes: e4d8b05ad5 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200515013643.2081941-1-bjorn.andersson@linaro.org
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18 19:30:56 +05:30
Roger Quadros 81530a38a3 phy: omap-usb2: Clean up exported header
Move private definitions from header to phy-omap-usb2.c file.
Get rid of unused data structures usb_dpll_params and omap_usb_phy_type.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Link: https://lore.kernel.org/r/20200515080518.26870-2-rogerq@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18 19:30:56 +05:30
Rikard Falkeborn 728ac1ba2e phy: phy-bcm-ns2-usbdrd: Constify phy_ops
phy_ops are never modified and can therefore be made const to allow the
compiler to put it in read-only memory.

Before:
   text    data     bss     dec     hex filename
   7831    3144     128   11103    2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o

After:
   text    data     bss     dec     hex filename
   7959    3016     128   11103    2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200516120441.7627-2-rikard.falkeborn@gmail.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18 19:30:56 +05:30
Rikard Falkeborn c79cc3d55c phy: phy-brcm-usb: Constify static structs
A number of structs were not modified and can therefore be made const
to allow the compiler to put them in read-only memory.

In order to do so, update a few functions that don't modify there input
to take pointers to const.

Before:
   text    data     bss     dec     hex filename
  15511    6448      64   22023    5607 drivers/phy/broadcom/phy-brcm-usb.o

After:
   text    data     bss     dec     hex filename
  16058    5936      64   22058    562a drivers/phy/broadcom/phy-brcm-usb.o

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200516120441.7627-4-rikard.falkeborn@gmail.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18 19:30:56 +05:30
Rikard Falkeborn cbe72af1a7 phy: sr-usb: Constify phy_ops
phy_ops are never modified and can therefore be made const to allow the
compiler to put it in read-only memory.

Before:
   text    data     bss     dec     hex filename
   4310    1244       0    5554    15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o

After:
   text    data     bss     dec     hex filename
   4438    1116       0    5554    15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20200516120441.7627-3-rikard.falkeborn@gmail.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18 19:30:55 +05:30
Peter Chen 11c82afac8 phy: phy-cadence-salvo: add phy .init API
The .init is used for one-time PHY's initialization, and .power_on
is called many times during the device lifecycle.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Link: https://lore.kernel.org/r/20200513125605.5545-1-peter.chen@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:20:21 +05:30
Martin Blumenstingl f004be596c phy: amlogic: meson8b-usb2: Add a compatible string for Meson8m2
The 3.10 vendor kernel sets the ACA_ENABLE bit on Meson8b, Meson8m2 and
GXBB, but not on Meson8. Add a compatible string for Meson8m2 which also
sets that bit.
While here, also update the Kconfig text and MODULE_DESCRIPTION.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-7-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl 7cafc01744 phy: amlogic: meson8b-usb2: unset the IDDQ bit during PHY power-on
The vendor driver unsets the set_iddig bit during power-on as well and
sets it when suspending the PHY. I did not notice this in the vendor
driver first, because it's part of the dwc_otg driver there (instead of
their PHY code). While here, also add all other REG_DBG_UART register
bit definitions.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-6-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl 6b99262fd2 phy: amlogic: meson8b-usb2: Don't set REG_ADP_BC_ACA_ENABLE on Meson8
Skip setting REG_ADP_BC_ACA_ENABLE on Meson8 SoCs and polling for the
REG_ADP_BC_ACA_PIN_FLOAT bit. The vendor also skips this part on Meson8
SoCs.
This fixes initialization of the host-only USB PHY on Meson8 which would
otherwise fail with "USB ID detect failed!".

Fixes: 4a3449d1a0 ("phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCs")
Reported-by: Thomas Graichen <thomas.graichen@gmail.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-5-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl de143a40fa phy: amlogic: meson8b-usb2: Use a MMIO regmap
Using a MMIO regmap and switch to regmap_update_bits() to simplify the
code in the driver. Also switch to devm_platform_ioremap_resource()
instead of open-coding it. No functional changes intended.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-4-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl 2c0dd84403 dt-bindings: phy: meson8b-usb2: Add compatible string for Meson8m2
The USB2 PHY on Meson8m2 is identical to the one on Meson8b but
different to the one on Meson8. The only known difference is that Meson8
does not set the ACA_ENABLE bit while Meson8b and Meson8m2 do.
Add an explicit compatible string for Meson8m2 so those differences can
be taken care of.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200512222424.549351-3-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Martin Blumenstingl 41e291904a dt-bindings: phy: meson8b-usb2: Convert to json-schema
Now that we have the DT validation in place, let's convert the device
tree bindings for the Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2
PHY over to a YAML schema.

While here, also add the fallback compatible string
"amlogic,meson-gxbb-usb2-phy" which is already used in
arch/arm/boot/dts/meson{,8,8b}.dtsi.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Thomas Graichen <thomas.graichen@gmail.com>
Link: https://lore.kernel.org/r/20200512222424.549351-2-martin.blumenstingl@googlemail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15 13:16:55 +05:30
Geert Uytterhoeven 4127cbcd98 phy: intel-lgm-emmc: Add architecture dependency
The Intel eMMC PHY is only present on Intel Lightning Mountain SoCs.
Add an architecture dependency to the PHY_INTEL_EMMC config symbol, to
avoid asking the user about it when configuring a kernel for a non-x86
architecture.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200507113626.24026-3-geert+renesas@glider.be
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13 08:27:35 +05:30
Wei Yongjun e2ae8bca49 phy: ti: j721e-wiz: Fix some error return code in wiz_probe()
Fix to return negative error code from some error handling
cases instead of 0, as done elsewhere in this function.

Fixes: 091876cc35 ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Link: https://lore.kernel.org/r/20200507054109.110849-1-weiyongjun1@huawei.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13 08:27:35 +05:30
Christophe JAILLET 6d9c1de864 phy: cpcap-usb: Remove some useless code
Axe a clk that is unused in the driver.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20200507203127.202197-1-christophe.jaillet@wanadoo.fr
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13 08:27:35 +05:30
Jonathan Bakker 05942b8c36 phy: samsung: s5pv210-usb2: Add delay after reset
The USB phy takes some time to reset, so make sure we give it to it. The
delay length was taken from the 4x12 phy driver.

This manifested in issues with the DWC2 driver since commit fe369e1826
("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.")
where the endianness check would read the DWC ID as 0 due to the phy still
resetting, resulting in the wrong endian mode being chosen.

Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13 08:27:35 +05:30
Peter Chen 50d35aa8c1 phy: cadence: salvo: add salvo phy driver
Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2.
According to the Cadence, this PHY is a legacy Module, and Sierra and
Torrent are later evolutions from it, and their sequence overlap is
minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY
drivers.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-07 09:46:36 +05:30
Peter Chen 6bbee9da90 doc: dt-binding: cdns-salvo-phy: add binding doc
Add Cadence SALVO PHY binding doc, this PHY is a legacy module,
and is only used for USB3 and USB2.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-07 09:46:36 +05:30
Wesley Cheng b9d3e8a380 dt-bindings: phy: usb-snps-femto-v2: Add regulator entries to example
Fix errors reported by dt_binding_check, due to missing required
regulators in the example node.

Fixes: f06b9fc9a8 ("dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2")
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588753589-22673-1-git-send-email-wcheng@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-06 14:32:40 +05:30
Wesley Cheng 78c2aac2a0 phy: qcom-qmp: Rename UFS PCS QMP v4 registers
The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe.  Rename the register offsets to denote that the value is specific for
the UFS PCS register.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 10:44:04 +05:30
Wesley Cheng e4d8b05ad5 phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROL to a different offset.  Allow for
an offset in the register table to override default value
if it is a DP capable PHY.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Manu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 10:44:04 +05:30
Jack Pham 9a24b929d3 phy: qcom-qmp: Add SM8150 QMP USB3 PHY support
Add support for SM8150 QMP USB3 PHY with the necessary
initialization sequences as well as additional QMP V4
register definitions.

Signed-off-by: Jack Pham <jackp@codeaurora.org>
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Manu Gautam <mgautam@codeaurora.org>
Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 10:44:04 +05:30
Wesley Cheng 51e8114f80 phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs
This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs.  There
are potentially multiple instances of this UTMI PHY on the
SOC, all which can utilize this driver.  The V2 driver will
have a different register map compared to V1.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Philipp Zabel <pza@pengutronix.de>
Reviewed-by: Manu Gautam <mgautam@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 10:44:04 +05:30
Wesley Cheng f06b9fc9a8 dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2
This binding shows the descriptions and properties for the
Synopsis Femto USB PHY V2 used on QCOM platforms.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/1588636467-23409-2-git-send-email-wcheng@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05 10:44:04 +05:30
Robert Marko 4f8dad0aac dt-bindings: phy-qcom-ipq4019-usb: add binding document
This patch adds the binding documentation for the HS/SS USB PHY found
inside Qualcom Dakota SoCs.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200503201823.531757-2-robert.marko@sartura.hr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-04 13:07:29 +05:30