05a58345db
drm/amdgpu: add ras error count after each query (v2)
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v1: increase ras ce/ue error count
v2: log the number of correctable and uncorrectable errors
Signed-off-by: Tao Zhou <tao.zhou1@amd.com >
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:49:33 -05:00
939e2258ce
drm/amdgpu: querry umc error count
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check umc error count in both ras querry function and
ras interrupt handler
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:49:28 -05:00
5b6b35aaac
drm/amdgpu: init umc v6_1 functions for vega20
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init umc callback function for vega20 in sw early init phase
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:49:22 -05:00
9884c2b1c3
drm/amdgpu: add umc v6_1 query error count support
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Implement umc query_ras_error_count function to support querry
both correctable and uncorrectable error
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Signed-off-by: Tao Zhou <tao.zhou1@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:49:16 -05:00
03c9963f47
drm/amdgpu: add umc v6_1_1 IP headers
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the change introduces IP headers for unified memory controller (umc)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:49:10 -05:00
245219a660
drm/amdgpu: add rsmu v_0_0_2 ip headers
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remote smu (rsmu) is a sub-block used as ip register interface,
error handling, reset generation.etc
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:49:03 -05:00
9e585a523b
drm/amdgpu: add amdgpu_umc_functions structure
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This is common structure as UMC callback function
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:48:57 -05:00
6501a77170
drm/amdgpu: init RSMU and UMC ip base address for vega20
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the driver needs to program RSMU and UMC registers to
support vega20 RAS feature
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:48:51 -05:00
7af25d5b7e
drm/amdgpu: move some ras data structure to amdgpu_ras.h
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These are common structures that can be included by IP specific
source files
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Dennis Li <dennis.li@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:48:32 -05:00
fa1884f9d8
drm/amdgpu: drop drmP.h from vcn_v2_5.c
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Unused.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:33:41 -05:00
9a2ffeb525
drm/amdgpu: drop drmP.h from vcn_v2_0.c
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And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:33:36 -05:00
75589f496d
drm/amdgpu: drop drmP.h from sdma_v5_0.c
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And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:33:31 -05:00
e9eea90247
drm/amdgpu: drop drmP.h from nv.c
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And fix up the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:33:26 -05:00
b23b2e9e49
drm/amdgpu: drop drmP.h from navi10_ih.c
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And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:33:21 -05:00
0a069bbe13
drm/amdgpu: drop drmP.h in gfx_v10_0.c
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And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:33:16 -05:00
3b90f6ecdf
drm/amdgpu: drop drmP.h from amdgpu_amdkfd_gfx_v10.c
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Unused.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:33:10 -05:00
32978d8cfd
drm/amdgpu: drop drmP.h in amdgpu_amdkfd_arcturus.c
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Unused.
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-31 14:32:56 -05:00
59de58f84f
drm/amd/powerplay: determine the features to enable by pptable only
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Per current logics, the features to enable are determined together
by driver and pptable. This is not efficient in co-debug with
firmware team.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:35 -05:00
861324983d
drm/amdgpu: correct irq type used for sdma ecc
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we should pass irq type, instead of irq client id,
to irq_get/put interface
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:35 -05:00
b4af964e75
drm/amd/powerplay: make power limit retrieval as asic specific
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The power limit retrieval should be done per asic. Since we may
need to lookup in the pptable and that's really asic specific.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:35 -05:00
1f23cadbe0
drm/amd/powerplay: correct arcturus current clock level calculation
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There may be 1Mhz delta between target and actual frequency. That
should be taken into consideration for current level check.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:35 -05:00
60d435b73d
drm/amd/powerplay: support UMD PSTATE settings on arcturus
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Enable arcturus UMD PSTATE support.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:35 -05:00
4bf76e60b9
drm/amd/powerplay: fix arcturus real-time clock frequency retrieval
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Make sure we can still get the accurate gfxclk/uclk/socclk frequency
even on dpm disabled.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:34 -05:00
790ef68afc
drm/amd/powerplay: remove redundancy debug log in smu
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remove redundacy debug log in smu.
eg:
[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
Signed-off-by: Kevin Wang <kevin1.wang@amd.com >
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:34 -05:00
8a856ced35
drm/amd/powerplay: correct the bitmask used in arcturus
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Those bitmask prefixed by "SMU_" should be used.
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Kevin Wang <kevin1.wang@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2019-07-30 23:48:34 -05:00
Tao Zhou
Hawking Zhang
Alex Deucher
Evan Quan
Kevin Wang