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Merge tag 'wireless-drivers-next-2021-12-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next
Kalle Valo says: ==================== wireless-drivers-next patches for v5.17 Second set of patches for v5.17, planning to do at least one more. Smaller new features, nothing special this time. Major changes: rtw88 * debugfs file to fix tx rate iwlwifi * support SAR GEO Offset Mapping (SGOM) via BIOS * support firmware API version 68 * add some new device IDs ath11k * support PCI devices with 1 MSI vector * WCN6855 hw2.1 support * 11d scan offload support * full monitor mode, only supported on QCN9074 * scan MAC address randomization support * reserved host DDR addresses from DT for PCI devices support ath9k * switch to rate table based lookup ath * extend South Korea regulatory domain support wcn36xx * beacon filter support * tag 'wireless-drivers-next-2021-12-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next: (129 commits) wcn36xx: Implement beacon filtering wcn36xx: Fix physical location of beacon filter comment wcn36xx: Fix beacon filter structure definitions ath11k: Use reserved host DDR addresses from DT for PCI devices dt: bindings: add new DT entry for ath11k PCI device support wilc1000: Improve WILC TX performance when power_save is off wl1251: specify max. IE length rsi: fix array out of bound wilc1000: Rename workqueue from "WILC_wq" to "NETDEV-wq" wilc1000: Rename tx task from "K_TXQ_TASK" to NETDEV-tx wilc1000: Rename irq handler from "WILC_IRQ" to netdev name wilc1000: Rename SPI driver from "WILC_SPI" to "wilc1000_spi" wilc1000: Fix spurious "FW not responding" error wilc1000: Remove misleading USE_SPI_DMA macro wilc1000: Fix missing newline in error message wilc1000: Fix copy-and-paste typo in wilc_set_mac_address rtw89: coex: Update COEX to 5.5.8 rtw89: coex: Cancel PS leaving while C2H comes rtw89: coex: Update BT counters while receiving report rtw89: coex: Define LPS state for BTC using ... ==================== Link: https://lore.kernel.org/r/20211217130952.34887C36AE9@smtp.kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
@@ -150,6 +150,12 @@ properties:
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string to uniquely identify variant of the calibration data in the
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board-2.bin for designs with colliding bus and device specific ids
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memory-region:
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maxItems: 1
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description:
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phandle to a node describing reserved memory (System RAM memory)
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used by ath11k firmware (see bindings/reserved-memory/reserved-memory.txt)
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required:
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- compatible
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- reg
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@@ -279,3 +285,27 @@ examples:
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"tcl2host-status-ring";
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qcom,rproc = <&q6v5_wcss>;
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};
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- |
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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qcn9074_0: qcn9074_0@51100000 {
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no-map;
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reg = <0x0 0x51100000 0x0 0x03500000>;
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};
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};
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pci {
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pcie0 {
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#size-cells = <2>;
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#address-cells = <3>;
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wifi_0: wifi@0 {
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reg = <0 0 0 0 0>;
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memory-region = <&qcn9074_0>;
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};
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};
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};
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@@ -90,6 +90,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = true,
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.dynamic_sar_support = false,
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},
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@@ -125,6 +126,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = true,
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.dynamic_sar_support = false,
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},
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@@ -161,6 +163,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -191,6 +194,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.uart_pin_workaround = true,
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.tx_stats_over_pktlog = false,
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.credit_size_workaround = false,
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.bmi_large_size_download = true,
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.supports_peer_stats_info = true,
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.dynamic_sar_support = true,
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@@ -227,6 +231,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -262,6 +267,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -297,6 +303,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -335,6 +342,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = true,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.supports_peer_stats_info = true,
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.dynamic_sar_support = true,
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@@ -377,6 +385,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -425,6 +434,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -470,6 +480,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -505,6 +516,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -542,6 +554,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = true,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -571,6 +584,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.uart_pin_workaround = true,
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.credit_size_workaround = true,
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.dynamic_sar_support = false,
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},
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{
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@@ -612,6 +626,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = false,
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},
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@@ -640,6 +655,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.rri_on_ddr = true,
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.hw_filter_reset_required = false,
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.fw_diag_ce_download = false,
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.credit_size_workaround = false,
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.tx_stats_over_pktlog = false,
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.dynamic_sar_support = true,
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},
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@@ -715,6 +731,7 @@ static void ath10k_send_suspend_complete(struct ath10k *ar)
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static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
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{
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bool mtu_workaround = ar->hw_params.credit_size_workaround;
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int ret;
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u32 param = 0;
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@@ -732,7 +749,7 @@ static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
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param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
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if (mode == ATH10K_FIRMWARE_MODE_NORMAL)
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if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
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param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
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else
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param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
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@@ -1400,115 +1400,6 @@ enum htt_dbg_stats_status {
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HTT_DBG_STATS_STATUS_SERIES_DONE = 7
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};
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/*
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* target -> host statistics upload
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*
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* The following field definitions describe the format of the HTT target
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* to host stats upload confirmation message.
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* The message contains a cookie echoed from the HTT host->target stats
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* upload request, which identifies which request the confirmation is
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* for, and a series of tag-length-value stats information elements.
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* The tag-length header for each stats info element also includes a
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* status field, to indicate whether the request for the stat type in
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* question was fully met, partially met, unable to be met, or invalid
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* (if the stat type in question is disabled in the target).
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* A special value of all 1's in this status field is used to indicate
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* the end of the series of stats info elements.
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*
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*
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* |31 16|15 8|7 5|4 0|
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* |------------------------------------------------------------|
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* | reserved | msg type |
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* |------------------------------------------------------------|
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* | cookie LSBs |
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* |------------------------------------------------------------|
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* | cookie MSBs |
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* |------------------------------------------------------------|
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* | stats entry length | reserved | S |stat type|
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* |------------------------------------------------------------|
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* | |
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* | type-specific stats info |
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* | |
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* |------------------------------------------------------------|
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* | stats entry length | reserved | S |stat type|
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* |------------------------------------------------------------|
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* | |
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* | type-specific stats info |
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* | |
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* |------------------------------------------------------------|
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* | n/a | reserved | 111 | n/a |
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* |------------------------------------------------------------|
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* Header fields:
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* - MSG_TYPE
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* Bits 7:0
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* Purpose: identifies this is a statistics upload confirmation message
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* Value: 0x9
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* - COOKIE_LSBS
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* Bits 31:0
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* Purpose: Provide a mechanism to match a target->host stats confirmation
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* message with its preceding host->target stats request message.
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* Value: LSBs of the opaque cookie specified by the host-side requestor
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* - COOKIE_MSBS
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* Bits 31:0
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* Purpose: Provide a mechanism to match a target->host stats confirmation
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* message with its preceding host->target stats request message.
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* Value: MSBs of the opaque cookie specified by the host-side requestor
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*
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* Stats Information Element tag-length header fields:
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* - STAT_TYPE
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* Bits 4:0
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* Purpose: identifies the type of statistics info held in the
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* following information element
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* Value: htt_dbg_stats_type
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* - STATUS
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* Bits 7:5
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* Purpose: indicate whether the requested stats are present
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* Value: htt_dbg_stats_status, including a special value (0x7) to mark
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* the completion of the stats entry series
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* - LENGTH
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* Bits 31:16
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* Purpose: indicate the stats information size
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* Value: This field specifies the number of bytes of stats information
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* that follows the element tag-length header.
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* It is expected but not required that this length is a multiple of
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* 4 bytes. Even if the length is not an integer multiple of 4, the
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* subsequent stats entry header will begin on a 4-byte aligned
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* boundary.
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*/
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#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
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#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
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#define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
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#define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
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||||
|
||||
struct htt_stats_conf_item {
|
||||
union {
|
||||
u8 info;
|
||||
struct {
|
||||
u8 stat_type:5; /* %HTT_DBG_STATS_ */
|
||||
u8 status:3; /* %HTT_DBG_STATS_STATUS_ */
|
||||
} __packed;
|
||||
} __packed;
|
||||
u8 pad;
|
||||
__le16 length;
|
||||
u8 payload[]; /* roundup(length, 4) long */
|
||||
} __packed;
|
||||
|
||||
struct htt_stats_conf {
|
||||
u8 pad[3];
|
||||
__le32 cookie_lsb;
|
||||
__le32 cookie_msb;
|
||||
|
||||
/* each item has variable length! */
|
||||
struct htt_stats_conf_item items[];
|
||||
} __packed;
|
||||
|
||||
static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
|
||||
const struct htt_stats_conf_item *item)
|
||||
{
|
||||
return (void *)item + sizeof(*item) + roundup(item->length, 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
|
||||
*
|
||||
@@ -1828,7 +1719,6 @@ struct htt_resp {
|
||||
struct htt_rc_update rc_update;
|
||||
struct htt_rx_test rx_test;
|
||||
struct htt_pktlog_msg pktlog_msg;
|
||||
struct htt_stats_conf stats_conf;
|
||||
struct htt_rx_pn_ind rx_pn_ind;
|
||||
struct htt_rx_offload_ind rx_offload_ind;
|
||||
struct htt_rx_in_ord_ind rx_in_ord_ind;
|
||||
|
||||
@@ -147,6 +147,9 @@ void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
|
||||
htt->num_pending_tx--;
|
||||
if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
|
||||
ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
|
||||
|
||||
if (htt->num_pending_tx == 0)
|
||||
wake_up(&htt->empty_tx_wq);
|
||||
}
|
||||
|
||||
int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
|
||||
|
||||
@@ -618,6 +618,9 @@ struct ath10k_hw_params {
|
||||
*/
|
||||
bool uart_pin_workaround;
|
||||
|
||||
/* Workaround for the credit size calculation */
|
||||
bool credit_size_workaround;
|
||||
|
||||
/* tx stats support over pktlog */
|
||||
bool tx_stats_over_pktlog;
|
||||
|
||||
|
||||
@@ -6380,13 +6380,14 @@ static int ath10k_hw_scan(struct ieee80211_hw *hw,
|
||||
scan_timeout = min_t(u32, arg.max_rest_time *
|
||||
(arg.n_channels - 1) + (req->duration +
|
||||
ATH10K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD) *
|
||||
arg.n_channels, arg.max_scan_time + 200);
|
||||
|
||||
arg.n_channels, arg.max_scan_time);
|
||||
} else {
|
||||
/* Add a 200ms margin to account for event/command processing */
|
||||
scan_timeout = arg.max_scan_time + 200;
|
||||
scan_timeout = arg.max_scan_time;
|
||||
}
|
||||
|
||||
/* Add a 200ms margin to account for event/command processing */
|
||||
scan_timeout += 200;
|
||||
|
||||
ret = ath10k_start_scan(ar, &arg);
|
||||
if (ret) {
|
||||
ath10k_warn(ar, "failed to start hw scan: %d\n", ret);
|
||||
|
||||
@@ -82,8 +82,6 @@ int ath10k_txrx_tx_unref(struct ath10k_htt *htt,
|
||||
flags = skb_cb->flags;
|
||||
ath10k_htt_tx_free_msdu_id(htt, tx_done->msdu_id);
|
||||
ath10k_htt_tx_dec_pending(htt);
|
||||
if (htt->num_pending_tx == 0)
|
||||
wake_up(&htt->empty_tx_wq);
|
||||
spin_unlock_bh(&htt->tx_lock);
|
||||
|
||||
rcu_read_lock();
|
||||
|
||||
@@ -2611,9 +2611,30 @@ int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb)
|
||||
ath10k_mac_handle_beacon(ar, skb);
|
||||
|
||||
if (ieee80211_is_beacon(hdr->frame_control) ||
|
||||
ieee80211_is_probe_resp(hdr->frame_control))
|
||||
ieee80211_is_probe_resp(hdr->frame_control)) {
|
||||
struct ieee80211_mgmt *mgmt = (void *)skb->data;
|
||||
u8 *ies;
|
||||
int ies_ch;
|
||||
|
||||
status->boottime_ns = ktime_get_boottime_ns();
|
||||
|
||||
if (!ar->scan_channel)
|
||||
goto drop;
|
||||
|
||||
ies = mgmt->u.beacon.variable;
|
||||
|
||||
ies_ch = cfg80211_get_ies_channel_number(mgmt->u.beacon.variable,
|
||||
skb_tail_pointer(skb) - ies,
|
||||
sband->band);
|
||||
|
||||
if (ies_ch > 0 && ies_ch != channel) {
|
||||
ath10k_dbg(ar, ATH10K_DBG_MGMT,
|
||||
"channel mismatched ds channel %d scan channel %d\n",
|
||||
ies_ch, channel);
|
||||
goto drop;
|
||||
}
|
||||
}
|
||||
|
||||
ath10k_dbg(ar, ATH10K_DBG_MGMT,
|
||||
"event mgmt rx skb %pK len %d ftype %02x stype %02x\n",
|
||||
skb, skb->len,
|
||||
@@ -2627,6 +2648,10 @@ int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb)
|
||||
ieee80211_rx_ni(ar->hw, skb);
|
||||
|
||||
return 0;
|
||||
|
||||
drop:
|
||||
dev_kfree_skb(skb);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int freq_to_idx(struct ath10k *ar, int freq)
|
||||
|
||||
@@ -3478,7 +3478,9 @@ struct wmi_phyerr_event {
|
||||
__le32 num_phyerrs;
|
||||
__le32 tsf_l32;
|
||||
__le32 tsf_u32;
|
||||
struct wmi_phyerr phyerrs[];
|
||||
|
||||
/* array of struct wmi_phyerr */
|
||||
u8 phyerrs[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_10_4_phyerr_event {
|
||||
|
||||
@@ -206,13 +206,13 @@ static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset)
|
||||
|
||||
static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
|
||||
{
|
||||
const struct ce_pipe_config *ce_config;
|
||||
const struct ce_attr *ce_attr;
|
||||
|
||||
ce_config = &ab->hw_params.target_ce_config[ce_id];
|
||||
if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT)
|
||||
ce_attr = &ab->hw_params.host_ce_config[ce_id];
|
||||
if (ce_attr->src_nentries)
|
||||
ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_ADDRESS);
|
||||
|
||||
if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) {
|
||||
if (ce_attr->dest_nentries) {
|
||||
ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS);
|
||||
ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
|
||||
CE_HOST_IE_3_ADDRESS);
|
||||
@@ -221,13 +221,13 @@ static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
|
||||
|
||||
static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
|
||||
{
|
||||
const struct ce_pipe_config *ce_config;
|
||||
const struct ce_attr *ce_attr;
|
||||
|
||||
ce_config = &ab->hw_params.target_ce_config[ce_id];
|
||||
if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT)
|
||||
ce_attr = &ab->hw_params.host_ce_config[ce_id];
|
||||
if (ce_attr->src_nentries)
|
||||
ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_ADDRESS);
|
||||
|
||||
if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) {
|
||||
if (ce_attr->dest_nentries) {
|
||||
ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS);
|
||||
ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
|
||||
CE_HOST_IE_3_ADDRESS);
|
||||
|
||||
@@ -74,10 +74,14 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
|
||||
BIT(NL80211_IFTYPE_AP) |
|
||||
BIT(NL80211_IFTYPE_MESH_POINT),
|
||||
.supports_monitor = true,
|
||||
.full_monitor_mode = false,
|
||||
.supports_shadow_regs = false,
|
||||
.idle_ps = false,
|
||||
.supports_sta_ps = false,
|
||||
.cold_boot_calib = true,
|
||||
.fw_mem_mode = 0,
|
||||
.num_vdevs = 16 + 1,
|
||||
.num_peers = 512,
|
||||
.supports_suspend = false,
|
||||
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
|
||||
.fix_l1ss = true,
|
||||
@@ -128,10 +132,14 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
|
||||
BIT(NL80211_IFTYPE_AP) |
|
||||
BIT(NL80211_IFTYPE_MESH_POINT),
|
||||
.supports_monitor = true,
|
||||
.full_monitor_mode = false,
|
||||
.supports_shadow_regs = false,
|
||||
.idle_ps = false,
|
||||
.supports_sta_ps = false,
|
||||
.cold_boot_calib = true,
|
||||
.fw_mem_mode = 0,
|
||||
.num_vdevs = 16 + 1,
|
||||
.num_peers = 512,
|
||||
.supports_suspend = false,
|
||||
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
|
||||
.fix_l1ss = true,
|
||||
@@ -181,10 +189,14 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
|
||||
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
|
||||
BIT(NL80211_IFTYPE_AP),
|
||||
.supports_monitor = false,
|
||||
.full_monitor_mode = false,
|
||||
.supports_shadow_regs = true,
|
||||
.idle_ps = true,
|
||||
.supports_sta_ps = true,
|
||||
.cold_boot_calib = false,
|
||||
.fw_mem_mode = 0,
|
||||
.num_vdevs = 16 + 1,
|
||||
.num_peers = 512,
|
||||
.supports_suspend = true,
|
||||
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
|
||||
.fix_l1ss = true,
|
||||
@@ -234,10 +246,14 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
|
||||
BIT(NL80211_IFTYPE_AP) |
|
||||
BIT(NL80211_IFTYPE_MESH_POINT),
|
||||
.supports_monitor = true,
|
||||
.full_monitor_mode = true,
|
||||
.supports_shadow_regs = false,
|
||||
.idle_ps = false,
|
||||
.supports_sta_ps = false,
|
||||
.cold_boot_calib = false,
|
||||
.fw_mem_mode = 2,
|
||||
.num_vdevs = 8,
|
||||
.num_peers = 128,
|
||||
.supports_suspend = false,
|
||||
.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
|
||||
.fix_l1ss = true,
|
||||
@@ -287,10 +303,70 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
|
||||
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
|
||||
BIT(NL80211_IFTYPE_AP),
|
||||
.supports_monitor = false,
|
||||
.full_monitor_mode = false,
|
||||
.supports_shadow_regs = true,
|
||||
.idle_ps = true,
|
||||
.supports_sta_ps = true,
|
||||
.cold_boot_calib = false,
|
||||
.fw_mem_mode = 0,
|
||||
.num_vdevs = 16 + 1,
|
||||
.num_peers = 512,
|
||||
.supports_suspend = true,
|
||||
.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
|
||||
.fix_l1ss = false,
|
||||
.credit_flow = true,
|
||||
.max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
|
||||
.hal_params = &ath11k_hw_hal_params_qca6390,
|
||||
.supports_dynamic_smps_6ghz = false,
|
||||
.alloc_cacheable_memory = false,
|
||||
.wakeup_mhi = true,
|
||||
},
|
||||
{
|
||||
.name = "wcn6855 hw2.1",
|
||||
.hw_rev = ATH11K_HW_WCN6855_HW21,
|
||||
.fw = {
|
||||
.dir = "WCN6855/hw2.1",
|
||||
.board_size = 256 * 1024,
|
||||
.cal_offset = 128 * 1024,
|
||||
},
|
||||
.max_radios = 3,
|
||||
.bdf_addr = 0x4B0C0000,
|
||||
.hw_ops = &wcn6855_ops,
|
||||
.ring_mask = &ath11k_hw_ring_mask_qca6390,
|
||||
.internal_sleep_clock = true,
|
||||
.regs = &wcn6855_regs,
|
||||
.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
|
||||
.host_ce_config = ath11k_host_ce_config_qca6390,
|
||||
.ce_count = 9,
|
||||
.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
|
||||
.target_ce_count = 9,
|
||||
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
|
||||
.svc_to_ce_map_len = 14,
|
||||
.single_pdev_only = true,
|
||||
.rxdma1_enable = false,
|
||||
.num_rxmda_per_pdev = 2,
|
||||
.rx_mac_buf_ring = true,
|
||||
.vdev_start_delay = true,
|
||||
.htt_peer_map_v2 = false,
|
||||
|
||||
.spectral = {
|
||||
.fft_sz = 0,
|
||||
.fft_pad_sz = 0,
|
||||
.summary_pad_sz = 0,
|
||||
.fft_hdr_len = 0,
|
||||
.max_fft_bins = 0,
|
||||
},
|
||||
|
||||
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
|
||||
BIT(NL80211_IFTYPE_AP),
|
||||
.supports_monitor = false,
|
||||
.supports_shadow_regs = true,
|
||||
.idle_ps = true,
|
||||
.supports_sta_ps = true,
|
||||
.cold_boot_calib = false,
|
||||
.fw_mem_mode = 0,
|
||||
.num_vdevs = 16 + 1,
|
||||
.num_peers = 512,
|
||||
.supports_suspend = true,
|
||||
.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
|
||||
.fix_l1ss = false,
|
||||
@@ -1009,7 +1085,7 @@ static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
|
||||
ath11k_dp_free(ab);
|
||||
ath11k_hal_srng_deinit(ab);
|
||||
|
||||
ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS)) - 1;
|
||||
ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
|
||||
|
||||
ret = ath11k_hal_srng_init(ab);
|
||||
if (ret)
|
||||
@@ -1043,6 +1119,7 @@ void ath11k_core_halt(struct ath11k *ar)
|
||||
ath11k_mac_peer_cleanup_all(ar);
|
||||
cancel_delayed_work_sync(&ar->scan.timeout);
|
||||
cancel_work_sync(&ar->regd_update_work);
|
||||
cancel_work_sync(&ab->update_11d_work);
|
||||
|
||||
rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
|
||||
synchronize_rcu();
|
||||
@@ -1050,6 +1127,34 @@ void ath11k_core_halt(struct ath11k *ar)
|
||||
idr_init(&ar->txmgmt_idr);
|
||||
}
|
||||
|
||||
static void ath11k_update_11d(struct work_struct *work)
|
||||
{
|
||||
struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
|
||||
struct ath11k *ar;
|
||||
struct ath11k_pdev *pdev;
|
||||
struct wmi_set_current_country_params set_current_param = {};
|
||||
int ret, i;
|
||||
|
||||
spin_lock_bh(&ab->base_lock);
|
||||
memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2);
|
||||
spin_unlock_bh(&ab->base_lock);
|
||||
|
||||
ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n",
|
||||
set_current_param.alpha2[0],
|
||||
set_current_param.alpha2[1]);
|
||||
|
||||
for (i = 0; i < ab->num_radios; i++) {
|
||||
pdev = &ab->pdevs[i];
|
||||
ar = pdev->ar;
|
||||
|
||||
ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param);
|
||||
if (ret)
|
||||
ath11k_warn(ar->ab,
|
||||
"pdev id %d failed set current country code: %d\n",
|
||||
i, ret);
|
||||
}
|
||||
}
|
||||
|
||||
static void ath11k_core_restart(struct work_struct *work)
|
||||
{
|
||||
struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
|
||||
@@ -1083,6 +1188,7 @@ static void ath11k_core_restart(struct work_struct *work)
|
||||
idr_for_each(&ar->txmgmt_idr,
|
||||
ath11k_mac_tx_mgmt_pending_free, ar);
|
||||
idr_destroy(&ar->txmgmt_idr);
|
||||
wake_up(&ar->txmgmt_empty_waitq);
|
||||
}
|
||||
|
||||
wake_up(&ab->wmi_ab.tx_credits_wq);
|
||||
@@ -1219,12 +1325,14 @@ struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
|
||||
|
||||
mutex_init(&ab->core_lock);
|
||||
spin_lock_init(&ab->base_lock);
|
||||
mutex_init(&ab->vdev_id_11d_lock);
|
||||
|
||||
INIT_LIST_HEAD(&ab->peers);
|
||||
init_waitqueue_head(&ab->peer_mapping_wq);
|
||||
init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
|
||||
init_waitqueue_head(&ab->qmi.cold_boot_waitq);
|
||||
INIT_WORK(&ab->restart_work, ath11k_core_restart);
|
||||
INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
|
||||
timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
|
||||
init_completion(&ab->htc_suspend);
|
||||
init_completion(&ab->wow.wakeup_completed);
|
||||
|
||||
@@ -117,6 +117,7 @@ enum ath11k_hw_rev {
|
||||
ATH11K_HW_IPQ6018_HW10,
|
||||
ATH11K_HW_QCN9074_HW10,
|
||||
ATH11K_HW_WCN6855_HW20,
|
||||
ATH11K_HW_WCN6855_HW21,
|
||||
};
|
||||
|
||||
enum ath11k_firmware_mode {
|
||||
@@ -199,6 +200,9 @@ enum ath11k_dev_flags {
|
||||
ATH11K_FLAG_REGISTERED,
|
||||
ATH11K_FLAG_QMI_FAIL,
|
||||
ATH11K_FLAG_HTC_SUSPEND_COMPLETE,
|
||||
ATH11K_FLAG_CE_IRQ_ENABLED,
|
||||
ATH11K_FLAG_EXT_IRQ_ENABLED,
|
||||
ATH11K_FLAG_FIXED_MEM_RGN,
|
||||
};
|
||||
|
||||
enum ath11k_monitor_flags {
|
||||
@@ -547,6 +551,7 @@ struct ath11k {
|
||||
/* protects txmgmt_idr data */
|
||||
spinlock_t txmgmt_idr_lock;
|
||||
atomic_t num_pending_mgmt_tx;
|
||||
wait_queue_head_t txmgmt_empty_waitq;
|
||||
|
||||
/* cycle count is reported twice for each visited channel during scan.
|
||||
* access protected by data_lock
|
||||
@@ -585,6 +590,11 @@ struct ath11k {
|
||||
#endif
|
||||
bool dfs_block_radar_events;
|
||||
struct ath11k_thermal thermal;
|
||||
u32 vdev_id_11d_scan;
|
||||
struct completion finish_11d_scan;
|
||||
struct completion finish_11d_ch_list;
|
||||
bool pending_11d;
|
||||
bool regdom_set_by_user;
|
||||
};
|
||||
|
||||
struct ath11k_band_cap {
|
||||
@@ -711,6 +721,11 @@ struct ath11k_base {
|
||||
/* Protects data like peers */
|
||||
spinlock_t base_lock;
|
||||
struct ath11k_pdev pdevs[MAX_RADIOS];
|
||||
struct {
|
||||
enum WMI_HOST_WLAN_BAND supported_bands;
|
||||
u32 pdev_id;
|
||||
} target_pdev_ids[MAX_RADIOS];
|
||||
u8 target_pdev_count;
|
||||
struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
|
||||
struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
|
||||
unsigned long long free_vdev_map;
|
||||
@@ -754,6 +769,8 @@ struct ath11k_base {
|
||||
struct completion driver_recovery;
|
||||
struct workqueue_struct *workqueue;
|
||||
struct work_struct restart_work;
|
||||
struct work_struct update_11d_work;
|
||||
u8 new_alpha2[3];
|
||||
struct {
|
||||
/* protected by data_lock */
|
||||
u32 fw_crash_counter;
|
||||
@@ -763,6 +780,8 @@ struct ath11k_base {
|
||||
struct ath11k_dbring_cap *db_caps;
|
||||
u32 num_db_cap;
|
||||
|
||||
/* To synchronize 11d scan vdev id */
|
||||
struct mutex vdev_id_11d_lock;
|
||||
struct timer_list mon_reap_timer;
|
||||
|
||||
struct completion htc_suspend;
|
||||
|
||||
@@ -6,6 +6,35 @@
|
||||
#include "core.h"
|
||||
#include "debug.h"
|
||||
|
||||
#define ATH11K_DB_MAGIC_VALUE 0xdeadbeaf
|
||||
|
||||
int ath11k_dbring_validate_buffer(struct ath11k *ar, void *buffer, u32 size)
|
||||
{
|
||||
u32 *temp;
|
||||
int idx;
|
||||
|
||||
size = size >> 2;
|
||||
|
||||
for (idx = 0, temp = buffer; idx < size; idx++, temp++) {
|
||||
if (*temp == ATH11K_DB_MAGIC_VALUE)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath11k_dbring_fill_magic_value(struct ath11k *ar,
|
||||
void *buffer, u32 size)
|
||||
{
|
||||
u32 *temp;
|
||||
int idx;
|
||||
|
||||
size = size >> 2;
|
||||
|
||||
for (idx = 0, temp = buffer; idx < size; idx++, temp++)
|
||||
*temp++ = ATH11K_DB_MAGIC_VALUE;
|
||||
}
|
||||
|
||||
static int ath11k_dbring_bufs_replenish(struct ath11k *ar,
|
||||
struct ath11k_dbring *ring,
|
||||
struct ath11k_dbring_element *buff)
|
||||
@@ -26,6 +55,7 @@ static int ath11k_dbring_bufs_replenish(struct ath11k *ar,
|
||||
|
||||
ptr_unaligned = buff->payload;
|
||||
ptr_aligned = PTR_ALIGN(ptr_unaligned, ring->buf_align);
|
||||
ath11k_dbring_fill_magic_value(ar, ptr_aligned, ring->buf_sz);
|
||||
paddr = dma_map_single(ab->dev, ptr_aligned, ring->buf_sz,
|
||||
DMA_FROM_DEVICE);
|
||||
|
||||
|
||||
@@ -76,4 +76,6 @@ int ath11k_dbring_get_cap(struct ath11k_base *ab,
|
||||
struct ath11k_dbring_cap *db_cap);
|
||||
void ath11k_dbring_srng_cleanup(struct ath11k *ar, struct ath11k_dbring *ring);
|
||||
void ath11k_dbring_buf_cleanup(struct ath11k *ar, struct ath11k_dbring *ring);
|
||||
int ath11k_dbring_validate_buffer(struct ath11k *ar, void *data, u32 size);
|
||||
|
||||
#endif /* ATH11K_DBRING_H */
|
||||
|
||||
@@ -1051,6 +1051,7 @@ int ath11k_dp_alloc(struct ath11k_base *ab)
|
||||
|
||||
INIT_LIST_HEAD(&dp->reo_cmd_list);
|
||||
INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list);
|
||||
INIT_LIST_HEAD(&dp->dp_full_mon_mpdu_list);
|
||||
spin_lock_init(&dp->reo_cmd_lock);
|
||||
|
||||
dp->reo_cmd_cache_flush_count = 0;
|
||||
|
||||
@@ -89,6 +89,19 @@ struct dp_tx_ring {
|
||||
int tx_status_tail;
|
||||
};
|
||||
|
||||
enum dp_mon_status_buf_state {
|
||||
/* PPDU id matches in dst ring and status ring */
|
||||
DP_MON_STATUS_MATCH,
|
||||
/* status ring dma is not done */
|
||||
DP_MON_STATUS_NO_DMA,
|
||||
/* status ring is lagging, reap status ring */
|
||||
DP_MON_STATUS_LAG,
|
||||
/* status ring is leading, reap dst ring and drop */
|
||||
DP_MON_STATUS_LEAD,
|
||||
/* replinish monitor status ring */
|
||||
DP_MON_STATUS_REPLINISH,
|
||||
};
|
||||
|
||||
struct ath11k_pdev_mon_stats {
|
||||
u32 status_ppdu_state;
|
||||
u32 status_ppdu_start;
|
||||
@@ -104,6 +117,12 @@ struct ath11k_pdev_mon_stats {
|
||||
u32 dup_mon_buf_cnt;
|
||||
};
|
||||
|
||||
struct dp_full_mon_mpdu {
|
||||
struct list_head list;
|
||||
struct sk_buff *head;
|
||||
struct sk_buff *tail;
|
||||
};
|
||||
|
||||
struct dp_link_desc_bank {
|
||||
void *vaddr_unaligned;
|
||||
void *vaddr;
|
||||
@@ -135,7 +154,11 @@ struct ath11k_mon_data {
|
||||
u32 mon_last_buf_cookie;
|
||||
u64 mon_last_linkdesc_paddr;
|
||||
u16 chan_noise_floor;
|
||||
|
||||
bool hold_mon_dst_ring;
|
||||
enum dp_mon_status_buf_state buf_state;
|
||||
dma_addr_t mon_status_paddr;
|
||||
struct dp_full_mon_mpdu *mon_mpdu;
|
||||
struct hal_sw_mon_ring_entries sw_mon_entries;
|
||||
struct ath11k_pdev_mon_stats rx_mon_stats;
|
||||
/* lock for monitor data */
|
||||
spinlock_t mon_lock;
|
||||
@@ -245,6 +268,7 @@ struct ath11k_dp {
|
||||
struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
|
||||
struct list_head reo_cmd_list;
|
||||
struct list_head reo_cmd_cache_flush_list;
|
||||
struct list_head dp_full_mon_mpdu_list;
|
||||
u32 reo_cmd_cache_flush_count;
|
||||
/**
|
||||
* protects access to below fields,
|
||||
@@ -292,6 +316,7 @@ enum htt_h2t_msg_type {
|
||||
HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc,
|
||||
HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10,
|
||||
HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
|
||||
HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17,
|
||||
};
|
||||
|
||||
#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
|
||||
@@ -957,6 +982,33 @@ struct htt_rx_ring_tlv_filter {
|
||||
u32 pkt_filter_flags3; /* DATA */
|
||||
};
|
||||
|
||||
#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0)
|
||||
#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8)
|
||||
|
||||
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0)
|
||||
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1)
|
||||
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2)
|
||||
#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3)
|
||||
|
||||
/**
|
||||
* Enumeration for full monitor mode destination ring select
|
||||
* 0 - REO destination ring select
|
||||
* 1 - FW destination ring select
|
||||
* 2 - SW destination ring select
|
||||
* 3 - Release destination ring select
|
||||
*/
|
||||
enum htt_rx_full_mon_release_ring {
|
||||
HTT_RX_MON_RING_REO,
|
||||
HTT_RX_MON_RING_FW,
|
||||
HTT_RX_MON_RING_SW,
|
||||
HTT_RX_MON_RING_RELEASE,
|
||||
};
|
||||
|
||||
struct htt_rx_full_monitor_mode_cfg_cmd {
|
||||
u32 info0;
|
||||
u32 cfg;
|
||||
} __packed;
|
||||
|
||||
/* HTT message target->host */
|
||||
|
||||
enum htt_t2h_msg_type {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -9,6 +9,7 @@
|
||||
#include "debugfs_sta.h"
|
||||
#include "hw.h"
|
||||
#include "peer.h"
|
||||
#include "mac.h"
|
||||
|
||||
static enum hal_tcl_encap_type
|
||||
ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
|
||||
@@ -985,6 +986,7 @@ ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
|
||||
struct ath11k_dp *dp = &ab->dp;
|
||||
struct sk_buff *skb;
|
||||
struct htt_ext_stats_cfg_cmd *cmd;
|
||||
u32 pdev_id;
|
||||
int len = sizeof(*cmd);
|
||||
int ret;
|
||||
|
||||
@@ -998,7 +1000,12 @@ ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
|
||||
memset(cmd, 0, sizeof(*cmd));
|
||||
cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
|
||||
|
||||
cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id;
|
||||
if (ab->hw_params.single_pdev_only)
|
||||
pdev_id = ath11k_mac_get_target_pdev_id(ar);
|
||||
else
|
||||
pdev_id = ar->pdev->pdev_id;
|
||||
|
||||
cmd->hdr.pdev_mask = 1 << pdev_id;
|
||||
|
||||
cmd->hdr.stats_type = type;
|
||||
cmd->cfg_param0 = cfg_params->cfg0;
|
||||
@@ -1026,6 +1033,15 @@ int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
|
||||
struct htt_rx_ring_tlv_filter tlv_filter = {0};
|
||||
int ret = 0, ring_id = 0, i;
|
||||
|
||||
if (ab->hw_params.full_monitor_mode) {
|
||||
ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab,
|
||||
dp->mac_id, !reset);
|
||||
if (ret < 0) {
|
||||
ath11k_err(ab, "failed to setup full monitor %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
|
||||
|
||||
if (!reset) {
|
||||
@@ -1091,3 +1107,42 @@ int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id,
|
||||
bool config)
|
||||
{
|
||||
struct htt_rx_full_monitor_mode_cfg_cmd *cmd;
|
||||
struct sk_buff *skb;
|
||||
int ret, len = sizeof(*cmd);
|
||||
|
||||
skb = ath11k_htc_alloc_skb(ab, len);
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
skb_put(skb, len);
|
||||
cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data;
|
||||
memset(cmd, 0, sizeof(*cmd));
|
||||
cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE,
|
||||
HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE);
|
||||
|
||||
cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id);
|
||||
|
||||
cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE |
|
||||
FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING,
|
||||
HTT_RX_MON_RING_SW);
|
||||
if (config) {
|
||||
cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END |
|
||||
HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END;
|
||||
}
|
||||
|
||||
ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free:
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -37,4 +37,6 @@ int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
|
||||
int rx_buf_size,
|
||||
struct htt_rx_ring_tlv_filter *tlv_filter);
|
||||
|
||||
int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id,
|
||||
bool config);
|
||||
#endif
|
||||
|
||||
@@ -974,6 +974,7 @@ int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
|
||||
srng->msi_data = params->msi_data;
|
||||
srng->initialized = 1;
|
||||
spin_lock_init(&srng->lock);
|
||||
lockdep_set_class(&srng->lock, hal->srng_key + ring_id);
|
||||
|
||||
for (i = 0; i < HAL_SRNG_NUM_REG_GRP; i++) {
|
||||
srng->hwreg_base[i] = srng_config->reg_start[i] +
|
||||
@@ -1260,6 +1261,24 @@ static int ath11k_hal_srng_create_config(struct ath11k_base *ab)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath11k_hal_register_srng_key(struct ath11k_base *ab)
|
||||
{
|
||||
struct ath11k_hal *hal = &ab->hal;
|
||||
u32 ring_id;
|
||||
|
||||
for (ring_id = 0; ring_id < HAL_SRNG_RING_ID_MAX; ring_id++)
|
||||
lockdep_register_key(hal->srng_key + ring_id);
|
||||
}
|
||||
|
||||
static void ath11k_hal_unregister_srng_key(struct ath11k_base *ab)
|
||||
{
|
||||
struct ath11k_hal *hal = &ab->hal;
|
||||
u32 ring_id;
|
||||
|
||||
for (ring_id = 0; ring_id < HAL_SRNG_RING_ID_MAX; ring_id++)
|
||||
lockdep_unregister_key(hal->srng_key + ring_id);
|
||||
}
|
||||
|
||||
int ath11k_hal_srng_init(struct ath11k_base *ab)
|
||||
{
|
||||
struct ath11k_hal *hal = &ab->hal;
|
||||
@@ -1279,6 +1298,8 @@ int ath11k_hal_srng_init(struct ath11k_base *ab)
|
||||
if (ret)
|
||||
goto err_free_cont_rdp;
|
||||
|
||||
ath11k_hal_register_srng_key(ab);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_cont_rdp:
|
||||
@@ -1293,6 +1314,7 @@ void ath11k_hal_srng_deinit(struct ath11k_base *ab)
|
||||
{
|
||||
struct ath11k_hal *hal = &ab->hal;
|
||||
|
||||
ath11k_hal_unregister_srng_key(ab);
|
||||
ath11k_hal_free_cont_rdp(ab);
|
||||
ath11k_hal_free_cont_wrp(ab);
|
||||
kfree(hal->srng_config);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user