mirror of
https://github.com/ukui/kernel.git
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Merge tag 'deps-irqchip-gic-3.17' of git://git.infradead.org/users/jcooper/linux
* tag 'deps-irqchip-gic-3.17' of git://git.infradead.org/users/jcooper/linux: irqchip: gic-v3: Initial support for GICv3 irqchip: gic: Move some bits of GICv2 to a library-type file Conflicts: arch/arm64/Kconfig
This commit is contained in:
Catalin Marinas
@@ -10,6 +10,7 @@ config ARM64
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select ARM_ARCH_TIMER
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select ARM_GIC
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select AUDIT_ARCH_COMPAT_GENERIC
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select ARM_GIC_V3
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select BUILDTIME_EXTABLE_SORT
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select CLONE_BACKWARDS
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select COMMON_CLK
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@@ -22,6 +22,7 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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@@ -289,6 +290,23 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr // Clear virtual offset
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#ifdef CONFIG_ARM_GIC_V3
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/* GICv3 system register access */
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #24, #4
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cmp x0, #1
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b.ne 3f
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mrs x0, ICC_SRE_EL2
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orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
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orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
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msr ICC_SRE_EL2, x0
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isb // Make sure SRE is now set
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msr ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
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3:
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#endif
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/* Populate ID registers. */
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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@@ -19,6 +19,7 @@
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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@@ -10,6 +10,11 @@ config ARM_GIC
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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@@ -15,7 +15,8 @@ obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
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obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
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obj-$(CONFIG_ARM_VIC) += irq-vic.o
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obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
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@@ -0,0 +1,115 @@
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/*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include "irq-gic-common.h"
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void gic_configure_irq(unsigned int irq, unsigned int type,
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void __iomem *base, void (*sync_access)(void))
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{
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u32 enablemask = 1 << (irq % 32);
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u32 enableoff = (irq / 32) * 4;
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u32 confmask = 0x2 << ((irq % 16) * 2);
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u32 confoff = (irq / 16) * 4;
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bool enabled = false;
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u32 val;
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/*
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* Read current configuration register, and insert the config
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* for "irq", depending on "type".
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*/
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val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val &= ~confmask;
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else if (type == IRQ_TYPE_EDGE_RISING)
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val |= confmask;
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/*
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* As recommended by the spec, disable the interrupt before changing
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* the configuration
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*/
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if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
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if (sync_access)
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sync_access();
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enabled = true;
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}
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/*
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* Write back the new configuration, and possibly re-enable
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* the interrupt.
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*/
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writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
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if (enabled)
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
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if (sync_access)
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sync_access();
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}
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void __init gic_dist_config(void __iomem *base, int gic_irqs,
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void (*sync_access)(void))
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{
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unsigned int i;
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < gic_irqs; i += 16)
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writel_relaxed(0, base + GIC_DIST_CONFIG + i / 4);
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/*
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i);
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as they are enabled by redistributor registers.
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*/
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for (i = 32; i < gic_irqs; i += 32)
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writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i / 8);
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if (sync_access)
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sync_access();
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}
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void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
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{
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int i;
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/*
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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writel_relaxed(0xffff0000, base + GIC_DIST_ENABLE_CLEAR);
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writel_relaxed(0x0000ffff, base + GIC_DIST_ENABLE_SET);
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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if (sync_access)
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sync_access();
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}
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@@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _IRQ_GIC_COMMON_H
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#define _IRQ_GIC_COMMON_H
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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void gic_configure_irq(unsigned int irq, unsigned int type,
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void __iomem *base, void (*sync_access)(void));
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void gic_dist_config(void __iomem *base, int gic_irqs,
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void (*sync_access)(void));
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void gic_cpu_config(void __iomem *base, void (*sync_access)(void));
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#endif /* _IRQ_GIC_COMMON_H */
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File diff suppressed because it is too large
Load Diff
@@ -46,6 +46,7 @@
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include "irq-gic-common.h"
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#include "irqchip.h"
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union gic_base {
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@@ -188,12 +189,6 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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void __iomem *base = gic_dist_base(d);
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unsigned int gicirq = gic_irq(d);
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u32 enablemask = 1 << (gicirq % 32);
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u32 enableoff = (gicirq / 32) * 4;
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u32 confmask = 0x2 << ((gicirq % 16) * 2);
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u32 confoff = (gicirq / 16) * 4;
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bool enabled = false;
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u32 val;
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/* Interrupt configuration for SGIs can't be changed */
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if (gicirq < 16)
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@@ -207,25 +202,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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if (gic_arch_extn.irq_set_type)
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gic_arch_extn.irq_set_type(d, type);
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val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val &= ~confmask;
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else if (type == IRQ_TYPE_EDGE_RISING)
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val |= confmask;
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/*
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* As recommended by the spec, disable the interrupt before changing
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* the configuration
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*/
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if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
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enabled = true;
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}
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writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
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if (enabled)
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
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gic_configure_irq(gicirq, type, base, NULL);
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raw_spin_unlock(&irq_controller_lock);
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@@ -386,12 +363,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
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writel_relaxed(0, base + GIC_DIST_CTRL);
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < gic_irqs; i += 16)
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writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
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/*
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* Set all global interrupts to this CPU only.
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*/
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@@ -401,18 +372,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
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/*
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as these enables are banked registers.
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*/
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for (i = 32; i < gic_irqs; i += 32)
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writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
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gic_dist_config(base, gic_irqs, NULL);
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writel_relaxed(1, base + GIC_DIST_CTRL);
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}
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@@ -439,18 +399,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
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if (i != cpu)
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gic_cpu_map[i] &= ~cpu_mask;
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/*
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||||
* Deal with the banked PPI and SGI interrupts - disable all
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||||
* PPI interrupts, ensure all SGI interrupts are enabled.
|
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*/
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writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
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writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
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||||
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/*
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* Set priority on PPI and SGI interrupts
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*/
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||||
for (i = 0; i < 32; i += 4)
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writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
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gic_cpu_config(dist_base, NULL);
|
||||
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||||
writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
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||||
writel_relaxed(1, base + GIC_CPU_CTRL);
|
||||
|
||||
@@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
|
||||
#define __LINUX_IRQCHIP_ARM_GIC_V3_H
|
||||
|
||||
/*
|
||||
* Distributor registers. We assume we're running non-secure, with ARE
|
||||
* being set. Secure-only and non-ARE registers are not described.
|
||||
*/
|
||||
#define GICD_CTLR 0x0000
|
||||
#define GICD_TYPER 0x0004
|
||||
#define GICD_IIDR 0x0008
|
||||
#define GICD_STATUSR 0x0010
|
||||
#define GICD_SETSPI_NSR 0x0040
|
||||
#define GICD_CLRSPI_NSR 0x0048
|
||||
#define GICD_SETSPI_SR 0x0050
|
||||
#define GICD_CLRSPI_SR 0x0058
|
||||
#define GICD_SEIR 0x0068
|
||||
#define GICD_ISENABLER 0x0100
|
||||
#define GICD_ICENABLER 0x0180
|
||||
#define GICD_ISPENDR 0x0200
|
||||
#define GICD_ICPENDR 0x0280
|
||||
#define GICD_ISACTIVER 0x0300
|
||||
#define GICD_ICACTIVER 0x0380
|
||||
#define GICD_IPRIORITYR 0x0400
|
||||
#define GICD_ICFGR 0x0C00
|
||||
#define GICD_IROUTER 0x6000
|
||||
#define GICD_PIDR2 0xFFE8
|
||||
|
||||
#define GICD_CTLR_RWP (1U << 31)
|
||||
#define GICD_CTLR_ARE_NS (1U << 4)
|
||||
#define GICD_CTLR_ENABLE_G1A (1U << 1)
|
||||
#define GICD_CTLR_ENABLE_G1 (1U << 0)
|
||||
|
||||
#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
|
||||
#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
|
||||
|
||||
#define GIC_PIDR2_ARCH_MASK 0xf0
|
||||
#define GIC_PIDR2_ARCH_GICv3 0x30
|
||||
#define GIC_PIDR2_ARCH_GICv4 0x40
|
||||
|
||||
/*
|
||||
* Re-Distributor registers, offsets from RD_base
|
||||
*/
|
||||
#define GICR_CTLR GICD_CTLR
|
||||
#define GICR_IIDR 0x0004
|
||||
#define GICR_TYPER 0x0008
|
||||
#define GICR_STATUSR GICD_STATUSR
|
||||
#define GICR_WAKER 0x0014
|
||||
#define GICR_SETLPIR 0x0040
|
||||
#define GICR_CLRLPIR 0x0048
|
||||
#define GICR_SEIR GICD_SEIR
|
||||
#define GICR_PROPBASER 0x0070
|
||||
#define GICR_PENDBASER 0x0078
|
||||
#define GICR_INVLPIR 0x00A0
|
||||
#define GICR_INVALLR 0x00B0
|
||||
#define GICR_SYNCR 0x00C0
|
||||
#define GICR_MOVLPIR 0x0100
|
||||
#define GICR_MOVALLR 0x0110
|
||||
#define GICR_PIDR2 GICD_PIDR2
|
||||
|
||||
#define GICR_WAKER_ProcessorSleep (1U << 1)
|
||||
#define GICR_WAKER_ChildrenAsleep (1U << 2)
|
||||
|
||||
/*
|
||||
* Re-Distributor registers, offsets from SGI_base
|
||||
*/
|
||||
#define GICR_ISENABLER0 GICD_ISENABLER
|
||||
#define GICR_ICENABLER0 GICD_ICENABLER
|
||||
#define GICR_ISPENDR0 GICD_ISPENDR
|
||||
#define GICR_ICPENDR0 GICD_ICPENDR
|
||||
#define GICR_ISACTIVER0 GICD_ISACTIVER
|
||||
#define GICR_ICACTIVER0 GICD_ICACTIVER
|
||||
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
|
||||
#define GICR_ICFGR0 GICD_ICFGR
|
||||
|
||||
#define GICR_TYPER_VLPIS (1U << 1)
|
||||
#define GICR_TYPER_LAST (1U << 4)
|
||||
|
||||
/*
|
||||
* CPU interface registers
|
||||
*/
|
||||
#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
|
||||
#define ICC_CTLR_EL1_EOImode_drop (1U << 1)
|
||||
#define ICC_SRE_EL1_SRE (1U << 0)
|
||||
|
||||
/*
|
||||
* Hypervisor interface registers (SRE only)
|
||||
*/
|
||||
#define ICH_LR_VIRTUAL_ID_MASK ((1UL << 32) - 1)
|
||||
|
||||
#define ICH_LR_EOI (1UL << 41)
|
||||
#define ICH_LR_GROUP (1UL << 60)
|
||||
#define ICH_LR_STATE (3UL << 62)
|
||||
#define ICH_LR_PENDING_BIT (1UL << 62)
|
||||
#define ICH_LR_ACTIVE_BIT (1UL << 63)
|
||||
|
||||
#define ICH_MISR_EOI (1 << 0)
|
||||
#define ICH_MISR_U (1 << 1)
|
||||
|
||||
#define ICH_HCR_EN (1 << 0)
|
||||
#define ICH_HCR_UIE (1 << 1)
|
||||
|
||||
#define ICH_VMCR_CTLR_SHIFT 0
|
||||
#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
|
||||
#define ICH_VMCR_BPR1_SHIFT 18
|
||||
#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
|
||||
#define ICH_VMCR_BPR0_SHIFT 21
|
||||
#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
|
||||
#define ICH_VMCR_PMR_SHIFT 24
|
||||
#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
|
||||
|
||||
#define ICC_EOIR1_EL1 S3_0_C12_C12_1
|
||||
#define ICC_IAR1_EL1 S3_0_C12_C12_0
|
||||
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
|
||||
#define ICC_PMR_EL1 S3_0_C4_C6_0
|
||||
#define ICC_CTLR_EL1 S3_0_C12_C12_4
|
||||
#define ICC_SRE_EL1 S3_0_C12_C12_5
|
||||
#define ICC_GRPEN1_EL1 S3_0_C12_C12_7
|
||||
|
||||
#define ICC_IAR1_EL1_SPURIOUS 0x3ff
|
||||
|
||||
#define ICC_SRE_EL2 S3_4_C12_C9_5
|
||||
|
||||
#define ICC_SRE_EL2_SRE (1 << 0)
|
||||
#define ICC_SRE_EL2_ENABLE (1 << 3)
|
||||
|
||||
/*
|
||||
* System register definitions
|
||||
*/
|
||||
#define ICH_VSEIR_EL2 S3_4_C12_C9_4
|
||||
#define ICH_HCR_EL2 S3_4_C12_C11_0
|
||||
#define ICH_VTR_EL2 S3_4_C12_C11_1
|
||||
#define ICH_MISR_EL2 S3_4_C12_C11_2
|
||||
#define ICH_EISR_EL2 S3_4_C12_C11_3
|
||||
#define ICH_ELSR_EL2 S3_4_C12_C11_5
|
||||
#define ICH_VMCR_EL2 S3_4_C12_C11_7
|
||||
|
||||
#define __LR0_EL2(x) S3_4_C12_C12_ ## x
|
||||
#define __LR8_EL2(x) S3_4_C12_C13_ ## x
|
||||
|
||||
#define ICH_LR0_EL2 __LR0_EL2(0)
|
||||
#define ICH_LR1_EL2 __LR0_EL2(1)
|
||||
#define ICH_LR2_EL2 __LR0_EL2(2)
|
||||
#define ICH_LR3_EL2 __LR0_EL2(3)
|
||||
#define ICH_LR4_EL2 __LR0_EL2(4)
|
||||
#define ICH_LR5_EL2 __LR0_EL2(5)
|
||||
#define ICH_LR6_EL2 __LR0_EL2(6)
|
||||
#define ICH_LR7_EL2 __LR0_EL2(7)
|
||||
#define ICH_LR8_EL2 __LR8_EL2(0)
|
||||
#define ICH_LR9_EL2 __LR8_EL2(1)
|
||||
#define ICH_LR10_EL2 __LR8_EL2(2)
|
||||
#define ICH_LR11_EL2 __LR8_EL2(3)
|
||||
#define ICH_LR12_EL2 __LR8_EL2(4)
|
||||
#define ICH_LR13_EL2 __LR8_EL2(5)
|
||||
#define ICH_LR14_EL2 __LR8_EL2(6)
|
||||
#define ICH_LR15_EL2 __LR8_EL2(7)
|
||||
|
||||
#define __AP0Rx_EL2(x) S3_4_C12_C8_ ## x
|
||||
#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
|
||||
#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
|
||||
#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
|
||||
#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
|
||||
|
||||
#define __AP1Rx_EL2(x) S3_4_C12_C9_ ## x
|
||||
#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
|
||||
#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
|
||||
#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
|
||||
#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
static inline void gic_write_eoir(u64 irq)
|
||||
{
|
||||
asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
|
||||
isb();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user