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dt-bindings: opp: Convert qcom-nvmem-cpufreq to DT schema
Convert qcom-nvmem-cpufreq to DT schema format, splitting it into an OPP schema and a CPUFreq schema in the process. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Yassine Oudjana
committed by
Viresh Kumar
Viresh Kumar
parent
784adeb3a3
commit
ec24d1d554
@@ -0,0 +1,166 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
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maintainers:
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- Ilia Lin <ilia.lin@kernel.org>
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description: |
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In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
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voltage is dynamically configured by Core Power Reduction (CPR) depending on
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current CPU frequency and efuse values.
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CPR provides a power domain with multiple levels that are selected depending
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on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
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according to the required OPPs defined in the CPU OPP tables.
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select:
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properties:
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compatible:
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contains:
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enum:
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- qcom,qcs404
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required:
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- compatible
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properties:
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cpus:
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type: object
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patternProperties:
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'cpu@[0-9a-f]+':
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type: object
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properties:
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power-domains:
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maxItems: 1
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power-domain-names:
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items:
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- const: cpr
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required:
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- power-domains
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- power-domain-names
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patternProperties:
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'^opp-table(-[a-z0-9]+)?$':
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if:
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properties:
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compatible:
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const: operating-points-v2-kryo-cpu
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then:
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patternProperties:
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'^opp-?[0-9]+$':
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required:
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- required-opps
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additionalProperties: true
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examples:
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- |
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/ {
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model = "Qualcomm Technologies, Inc. QCS404";
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compatible = "qcom,qcs404";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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};
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2-kryo-cpu";
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opp-shared;
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opp-1094400000 {
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opp-hz = /bits/ 64 <1094400000>;
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required-opps = <&cpr_opp1>;
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};
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opp-1248000000 {
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opp-hz = /bits/ 64 <1248000000>;
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required-opps = <&cpr_opp2>;
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};
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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required-opps = <&cpr_opp3>;
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};
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};
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cpr_opp_table: opp-table-cpr {
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compatible = "operating-points-v2-qcom-level";
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cpr_opp1: opp1 {
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opp-level = <1>;
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qcom,opp-fuse-level = <1>;
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};
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cpr_opp2: opp2 {
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opp-level = <2>;
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qcom,opp-fuse-level = <2>;
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};
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cpr_opp3: opp3 {
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opp-level = <3>;
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qcom,opp-fuse-level = <3>;
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};
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};
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};
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@@ -0,0 +1,257 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. NVMEM OPP bindings
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maintainers:
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- Ilia Lin <ilia.lin@kernel.org>
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allOf:
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- $ref: opp-v2-base.yaml#
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description: |
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In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
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the CPU frequencies subset and voltage value of each OPP varies based on
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the silicon variant in use.
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Qualcomm Technologies, Inc. Process Voltage Scaling Tables
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defines the voltage and frequency value based on the msm-id in SMEM
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and speedbin blown in the efuse combination.
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The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
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to provide the OPP framework with required information (existing HW bitmap).
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This is used to determine the voltage and frequency value for each OPP of
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operating-points-v2 table when it is parsed by the OPP framework.
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properties:
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compatible:
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const: operating-points-v2-kryo-cpu
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nvmem-cells:
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description: |
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A phandle pointing to a nvmem-cells node representing the
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efuse registers that has information about the
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speedbin that is used to select the right frequency/voltage
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value pair.
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opp-shared: true
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patternProperties:
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'^opp-?[0-9]+$':
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type: object
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properties:
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opp-hz: true
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opp-microvolt: true
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opp-supported-hw:
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description: |
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A single 32 bit bitmap value, representing compatible HW.
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Bitmap:
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0: MSM8996 V3, speedbin 0
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1: MSM8996 V3, speedbin 1
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2: MSM8996 V3, speedbin 2
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3: unused
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4: MSM8996 SG, speedbin 0
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5: MSM8996 SG, speedbin 1
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6: MSM8996 SG, speedbin 2
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7-31: unused
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maximum: 0x77
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clock-latency-ns: true
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required-opps: true
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required:
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- opp-hz
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required:
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- compatible
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if:
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required:
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- nvmem-cells
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then:
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patternProperties:
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'^opp-?[0-9]+$':
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required:
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- opp-supported-hw
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additionalProperties: false
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examples:
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- |
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/ {
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model = "Qualcomm Technologies, Inc. DB820c";
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compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 0>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 0>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 1>;
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operating-points-v2 = <&cluster1_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 1>;
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operating-points-v2 = <&cluster1_opp>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2-kryo-cpu";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x77>;
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clock-latency-ns = <200000>;
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};
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opp-1593600000 {
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opp-hz = /bits/ 64 <1593600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x71>;
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clock-latency-ns = <200000>;
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};
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opp-2188800000 {
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opp-hz = /bits/ 64 <2188800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x10>;
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clock-latency-ns = <200000>;
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};
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};
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cluster1_opp: opp-table-1 {
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compatible = "operating-points-v2-kryo-cpu";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x77>;
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clock-latency-ns = <200000>;
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};
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opp-1593600000 {
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opp-hz = /bits/ 64 <1593600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x70>;
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clock-latency-ns = <200000>;
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};
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opp-2150400000 {
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opp-hz = /bits/ 64 <2150400000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x31>;
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clock-latency-ns = <200000>;
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};
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opp-2342400000 {
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opp-hz = /bits/ 64 <2342400000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x10>;
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clock-latency-ns = <200000>;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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qfprom: qfprom@74000 {
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compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
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reg = <0x00074000 0x8ff>;
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#address-cells = <1>;
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#size-cells = <1>;
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speedbin_efuse: speedbin@133 {
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reg = <0x133 0x1>;
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bits = <5 3>;
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};
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};
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};
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};
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File diff suppressed because it is too large
Load Diff
+2
-1
@@ -15940,7 +15940,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
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M: Ilia Lin <ilia.lin@kernel.org>
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L: linux-pm@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
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F: Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
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F: Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
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F: drivers/cpufreq/qcom-cpufreq-nvmem.c
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QUALCOMM CRYPTO DRIVERS
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Reference in New Issue
Block a user