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staging: ccree: fix missing or redundant spaces
Add and/or remove redundant and/or missing spaces in ccree source Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
97af1ce278
commit
e7258b6a22
@@ -18,7 +18,7 @@ config CRYPTO_DEV_CCREE
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select CRYPTO_CTR
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select CRYPTO_XTS
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help
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Say 'Y' to enable a driver for the Arm TrustZone CryptoCell
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Say 'Y' to enable a driver for the Arm TrustZone CryptoCell
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C7xx. Currently only the CryptoCell 712 REE is supported.
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Choose this if you wish to use hardware acceleration of
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cryptographic operations on the system REE.
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@@ -238,8 +238,8 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c
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} else { /*ENCRYPT*/
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if (unlikely(areq_ctx->is_icv_fragmented == true))
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ssi_buffer_mgr_copy_scatterlist_portion(
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areq_ctx->mac_buf, areq_ctx->dstSgl, areq->cryptlen+areq_ctx->dstOffset,
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areq->cryptlen+areq_ctx->dstOffset + ctx->authsize, SSI_SG_FROM_BUF);
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areq_ctx->mac_buf, areq_ctx->dstSgl, areq->cryptlen + areq_ctx->dstOffset,
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areq->cryptlen + areq_ctx->dstOffset + ctx->authsize, SSI_SG_FROM_BUF);
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/* If an IV was generated, copy it back to the user provided buffer. */
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if (areq_ctx->backup_giv != NULL) {
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@@ -1561,7 +1561,7 @@ static int config_ccm_adata(struct aead_request *req)
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(req->cryptlen - ctx->authsize);
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int rc;
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memset(req_ctx->mac_buf, 0, AES_BLOCK_SIZE);
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memset(req_ctx->ccm_config, 0, AES_BLOCK_SIZE*3);
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memset(req_ctx->ccm_config, 0, AES_BLOCK_SIZE * 3);
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/* taken from crypto/ccm.c */
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/* 2 <= L <= 8, so 1 <= L' <= 7. */
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@@ -1585,12 +1585,12 @@ static int config_ccm_adata(struct aead_request *req)
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/* END of "taken from crypto/ccm.c" */
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/* l(a) - size of associated data. */
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req_ctx->ccm_hdr_size = format_ccm_a0 (a0, req->assoclen);
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req_ctx->ccm_hdr_size = format_ccm_a0(a0, req->assoclen);
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memset(req->iv + 15 - req->iv[0], 0, req->iv[0] + 1);
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req->iv[15] = 1;
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memcpy(ctr_count_0, req->iv, AES_BLOCK_SIZE) ;
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memcpy(ctr_count_0, req->iv, AES_BLOCK_SIZE);
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ctr_count_0[15] = 0;
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return 0;
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@@ -1858,7 +1858,7 @@ static inline void ssi_aead_dump_gcm(
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SSI_LOG_DEBUG("%s\n", title);
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}
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SSI_LOG_DEBUG("cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d \n", \
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SSI_LOG_DEBUG("cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d\n", \
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ctx->cipher_mode, ctx->authsize, ctx->enc_keylen, req->assoclen, req_ctx->cryptlen);
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if (ctx->enckey != NULL) {
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@@ -1878,12 +1878,12 @@ static inline void ssi_aead_dump_gcm(
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dump_byte_array("gcm_len_block", req_ctx->gcm_len_block.lenA, AES_BLOCK_SIZE);
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if (req->src != NULL && req->cryptlen) {
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dump_byte_array("req->src", sg_virt(req->src), req->cryptlen+req->assoclen);
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dump_byte_array("req->src", sg_virt(req->src), req->cryptlen + req->assoclen);
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}
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if (req->dst != NULL) {
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dump_byte_array("req->dst", sg_virt(req->dst), req->cryptlen+ctx->authsize+req->assoclen);
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}
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dump_byte_array("req->dst", sg_virt(req->dst), req->cryptlen + ctx->authsize + req->assoclen);
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}
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}
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#endif
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@@ -1899,7 +1899,7 @@ static int config_gcm_context(struct aead_request *req)
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(req->cryptlen - ctx->authsize);
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__be32 counter = cpu_to_be32(2);
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SSI_LOG_DEBUG("config_gcm_context() cryptlen = %d, req->assoclen = %d ctx->authsize = %d \n", cryptlen, req->assoclen, ctx->authsize);
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SSI_LOG_DEBUG("config_gcm_context() cryptlen = %d, req->assoclen = %d ctx->authsize = %d\n", cryptlen, req->assoclen, ctx->authsize);
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memset(req_ctx->hkey, 0, AES_BLOCK_SIZE);
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@@ -1916,15 +1916,15 @@ static int config_gcm_context(struct aead_request *req)
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if (req_ctx->plaintext_authenticate_only == false) {
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__be64 temp64;
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temp64 = cpu_to_be64(req->assoclen * 8);
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memcpy (&req_ctx->gcm_len_block.lenA, &temp64, sizeof(temp64));
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memcpy(&req_ctx->gcm_len_block.lenA, &temp64, sizeof(temp64));
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temp64 = cpu_to_be64(cryptlen * 8);
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memcpy (&req_ctx->gcm_len_block.lenC, &temp64, 8);
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memcpy(&req_ctx->gcm_len_block.lenC, &temp64, 8);
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} else { //rfc4543=> all data(AAD,IV,Plain) are considered additional data that is nothing is encrypted.
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__be64 temp64;
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temp64 = cpu_to_be64((req->assoclen+GCM_BLOCK_RFC4_IV_SIZE+cryptlen) * 8);
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memcpy (&req_ctx->gcm_len_block.lenA, &temp64, sizeof(temp64));
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temp64 = cpu_to_be64((req->assoclen + GCM_BLOCK_RFC4_IV_SIZE + cryptlen) * 8);
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memcpy(&req_ctx->gcm_len_block.lenA, &temp64, sizeof(temp64));
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temp64 = 0;
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memcpy (&req_ctx->gcm_len_block.lenC, &temp64, 8);
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memcpy(&req_ctx->gcm_len_block.lenC, &temp64, 8);
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}
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return 0;
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@@ -2220,7 +2220,7 @@ static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsign
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struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
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int rc = 0;
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SSI_LOG_DEBUG("ssi_rfc4106_gcm_setkey() keylen %d, key %p \n", keylen, key);
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SSI_LOG_DEBUG("ssi_rfc4106_gcm_setkey() keylen %d, key %p\n", keylen, key);
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if (keylen < 4)
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return -EINVAL;
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@@ -2238,7 +2238,7 @@ static int ssi_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsign
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struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
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int rc = 0;
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SSI_LOG_DEBUG("ssi_rfc4543_gcm_setkey() keylen %d, key %p \n", keylen, key);
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SSI_LOG_DEBUG("ssi_rfc4543_gcm_setkey() keylen %d, key %p\n", keylen, key);
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if (keylen < 4)
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return -EINVAL;
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@@ -2273,7 +2273,7 @@ static int ssi_gcm_setauthsize(struct crypto_aead *authenc,
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static int ssi_rfc4106_gcm_setauthsize(struct crypto_aead *authenc,
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unsigned int authsize)
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{
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SSI_LOG_DEBUG("ssi_rfc4106_gcm_setauthsize() authsize %d \n", authsize);
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SSI_LOG_DEBUG("ssi_rfc4106_gcm_setauthsize() authsize %d\n", authsize);
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switch (authsize) {
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case 8:
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@@ -2290,7 +2290,7 @@ static int ssi_rfc4106_gcm_setauthsize(struct crypto_aead *authenc,
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static int ssi_rfc4543_gcm_setauthsize(struct crypto_aead *authenc,
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unsigned int authsize)
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{
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SSI_LOG_DEBUG("ssi_rfc4543_gcm_setauthsize() authsize %d \n", authsize);
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SSI_LOG_DEBUG("ssi_rfc4543_gcm_setauthsize() authsize %d\n", authsize);
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if (authsize != 16)
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return -EINVAL;
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@@ -28,17 +28,17 @@
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/* mac_cmp - HW writes 8 B but all bytes hold the same value */
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#define ICV_CMP_SIZE 8
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#define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE*3)
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#define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3)
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#define MAX_MAC_SIZE MAX(SHA256_DIGEST_SIZE, AES_BLOCK_SIZE)
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/* defines for AES GCM configuration buffer */
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#define GCM_BLOCK_LEN_SIZE 8
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#define GCM_BLOCK_RFC4_IV_OFFSET 4
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#define GCM_BLOCK_RFC4_IV_SIZE 8 /* IV size for rfc's */
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#define GCM_BLOCK_RFC4_NONCE_OFFSET 0
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#define GCM_BLOCK_RFC4_NONCE_SIZE 4
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#define GCM_BLOCK_RFC4_IV_OFFSET 4
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#define GCM_BLOCK_RFC4_IV_SIZE 8 /* IV size for rfc's */
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#define GCM_BLOCK_RFC4_NONCE_OFFSET 0
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#define GCM_BLOCK_RFC4_NONCE_SIZE 4
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@@ -74,7 +74,7 @@ struct aead_req_ctx {
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u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
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struct {
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u8 lenA[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
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u8 lenC[GCM_BLOCK_LEN_SIZE] ;
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u8 lenC[GCM_BLOCK_LEN_SIZE];
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} gcm_len_block;
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u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
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File diff suppressed because it is too large
Load Diff
@@ -69,9 +69,9 @@ static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void __io
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static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size) {
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switch (ctx_p->flow_mode){
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switch (ctx_p->flow_mode) {
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case S_DIN_to_AES:
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switch (size){
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switch (size) {
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case CC_AES_128_BIT_KEY_SIZE:
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case CC_AES_192_BIT_KEY_SIZE:
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if (likely((ctx_p->cipher_mode != DRV_CIPHER_XTS) &&
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@@ -81,8 +81,8 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size) {
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break;
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case CC_AES_256_BIT_KEY_SIZE:
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return 0;
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case (CC_AES_192_BIT_KEY_SIZE*2):
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case (CC_AES_256_BIT_KEY_SIZE*2):
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case (CC_AES_192_BIT_KEY_SIZE * 2):
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case (CC_AES_256_BIT_KEY_SIZE * 2):
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if (likely((ctx_p->cipher_mode == DRV_CIPHER_XTS) ||
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(ctx_p->cipher_mode == DRV_CIPHER_ESSIV) ||
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(ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)))
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@@ -111,9 +111,9 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size) {
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static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int size) {
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switch (ctx_p->flow_mode){
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switch (ctx_p->flow_mode) {
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case S_DIN_to_AES:
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switch (ctx_p->cipher_mode){
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switch (ctx_p->cipher_mode) {
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case DRV_CIPHER_XTS:
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if ((size >= SSI_MIN_AES_XTS_SIZE) &&
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(size <= SSI_MAX_AES_XTS_SIZE) &&
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@@ -198,7 +198,7 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm)
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dev = &ctx_p->drvdata->plat_dev->dev;
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/* Allocate key buffer, cache line aligned */
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ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL|GFP_DMA);
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ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL | GFP_DMA);
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if (!ctx_p->user.key) {
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SSI_LOG_ERR("Allocating key buffer in context failed\n");
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rc = -ENOMEM;
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@@ -257,11 +257,11 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
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}
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typedef struct tdes_keys{
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typedef struct tdes_keys {
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u8 key1[DES_KEY_SIZE];
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u8 key2[DES_KEY_SIZE];
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u8 key3[DES_KEY_SIZE];
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}tdes_keys_t;
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} tdes_keys_t;
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static const u8 zero_buff[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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@@ -275,8 +275,8 @@ static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
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tdes_keys_t *tdes_key = (tdes_keys_t*)key;
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/* verify key1 != key2 and key3 != key2*/
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if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, sizeof(tdes_key->key1)) == 0) ||
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(memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2, sizeof(tdes_key->key3)) == 0) )) {
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if (unlikely((memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, sizeof(tdes_key->key1)) == 0) ||
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(memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2, sizeof(tdes_key->key3)) == 0))) {
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return -ENOEXEC;
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}
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#endif /* CCREE_FIPS_SUPPORT */
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@@ -336,11 +336,11 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
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#if SSI_CC_HAS_MULTI2
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/*last byte of key buffer is round number and should not be a part of key size*/
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if (ctx_p->flow_mode == S_DIN_to_MULTI2) {
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keylen -=1;
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keylen -= 1;
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}
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#endif /*SSI_CC_HAS_MULTI2*/
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if (unlikely(validate_keys_sizes(ctx_p,keylen) != 0)) {
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if (unlikely(validate_keys_sizes(ctx_p, keylen) != 0)) {
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SSI_LOG_ERR("Unsupported key size %d.\n", keylen);
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crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
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return -EINVAL;
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@@ -485,7 +485,7 @@ ssi_blkcipher_create_setup_desc(
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set_flow_mode(&desc[*seq_size], flow_mode);
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set_cipher_mode(&desc[*seq_size], cipher_mode);
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if ((cipher_mode == DRV_CIPHER_CTR) ||
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(cipher_mode == DRV_CIPHER_OFB) ) {
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(cipher_mode == DRV_CIPHER_OFB)) {
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set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
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} else {
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set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);
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@@ -650,7 +650,7 @@ ssi_blkcipher_create_data_desc(
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return;
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}
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/* Process */
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if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)){
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if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)) {
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SSI_LOG_DEBUG(" data params addr 0x%llX length 0x%X \n",
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(unsigned long long)sg_dma_address(src),
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nbytes);
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@@ -737,10 +737,10 @@ static int ssi_blkcipher_complete(struct device *dev,
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/*Set the inflight couter value to local variable*/
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inflight_counter = ctx_p->drvdata->inflight_counter;
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/*Decrease the inflight counter*/
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if(ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0)
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if (ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0)
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ctx_p->drvdata->inflight_counter--;
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if(areq){
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if (areq) {
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ablkcipher_request_complete(areq, completion_error);
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return 0;
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}
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@@ -761,10 +761,10 @@ static int ssi_blkcipher_process(
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struct device *dev = &ctx_p->drvdata->plat_dev->dev;
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struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN];
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struct ssi_crypto_req ssi_req = {};
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int rc, seq_len = 0,cts_restore_flag = 0;
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int rc, seq_len = 0, cts_restore_flag = 0;
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SSI_LOG_DEBUG("%s areq=%p info=%p nbytes=%d\n",
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((direction==DRV_CRYPTO_DIRECTION_ENCRYPT)?"Encrypt":"Decrypt"),
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((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"),
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areq, info, nbytes);
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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@@ -781,7 +781,7 @@ static int ssi_blkcipher_process(
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return 0;
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}
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/*For CTS in case of data size aligned to 16 use CBC mode*/
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if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)){
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if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)) {
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ctx_p->cipher_mode = DRV_CIPHER_CBC;
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cts_restore_flag = 1;
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@@ -848,8 +848,8 @@ static int ssi_blkcipher_process(
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/* STAT_PHASE_3: Lock HW and push sequence */
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rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, (areq == NULL)? 0:1);
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if(areq != NULL) {
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rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, (areq == NULL) ? 0 : 1);
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if (areq != NULL) {
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if (unlikely(rc != -EINPROGRESS)) {
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/* Failed to send the request or request completed synchronously */
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ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
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@@ -77,7 +77,7 @@
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#ifdef DX_DUMP_BYTES
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void dump_byte_array(const char *name, const u8 *the_array, unsigned long size)
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{
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int i , line_offset = 0, ret = 0;
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int i, line_offset = 0, ret = 0;
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const u8 *cur_byte;
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char line_buf[80];
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@@ -89,17 +89,17 @@ void dump_byte_array(const char *name, const u8 *the_array, unsigned long size)
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ret = snprintf(line_buf, sizeof(line_buf), "%s[%lu]: ",
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name, size);
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if (ret < 0) {
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SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n",ret);
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SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret);
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return;
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}
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line_offset = ret;
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for (i = 0 , cur_byte = the_array;
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for (i = 0, cur_byte = the_array;
|
||||
(i < size) && (line_offset < sizeof(line_buf)); i++, cur_byte++) {
|
||||
ret = snprintf(line_buf + line_offset,
|
||||
sizeof(line_buf) - line_offset,
|
||||
"0x%02X ", *cur_byte);
|
||||
if (ret < 0) {
|
||||
SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n",ret);
|
||||
SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret);
|
||||
return;
|
||||
}
|
||||
line_offset += ret;
|
||||
@@ -301,9 +301,9 @@ static int init_cc_resources(struct platform_device *plat_dev)
|
||||
if (rc)
|
||||
goto init_cc_res_err;
|
||||
|
||||
if(new_drvdata->plat_dev->dev.dma_mask == NULL)
|
||||
if (new_drvdata->plat_dev->dev.dma_mask == NULL)
|
||||
{
|
||||
new_drvdata->plat_dev->dev.dma_mask = & new_drvdata->plat_dev->dev.coherent_dma_mask;
|
||||
new_drvdata->plat_dev->dev.dma_mask = &new_drvdata->plat_dev->dev.coherent_dma_mask;
|
||||
}
|
||||
if (!new_drvdata->plat_dev->dev.coherent_dma_mask)
|
||||
{
|
||||
@@ -523,7 +523,7 @@ static int cc7x_probe(struct platform_device *plat_dev)
|
||||
asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (ctr));
|
||||
SSI_LOG_DEBUG("Main ID register (MIDR): Implementer 0x%02X, Arch 0x%01X,"
|
||||
" Part 0x%03X, Rev r%dp%d\n",
|
||||
(ctr>>24), (ctr>>16)&0xF, (ctr>>4)&0xFFF, (ctr>>20)&0xF, ctr&0xF);
|
||||
(ctr >> 24), (ctr >> 16) & 0xF, (ctr >> 4) & 0xFFF, (ctr >> 20) & 0xF, ctr & 0xF);
|
||||
#endif
|
||||
|
||||
/* Map registers space */
|
||||
@@ -546,13 +546,13 @@ static int cc7x_remove(struct platform_device *plat_dev)
|
||||
|
||||
return 0;
|
||||
}
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
static struct dev_pm_ops arm_cc7x_driver_pm = {
|
||||
SET_RUNTIME_PM_OPS(ssi_power_mgr_runtime_suspend, ssi_power_mgr_runtime_resume, NULL)
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
#define DX_DRIVER_RUNTIME_PM (&arm_cc7x_driver_pm)
|
||||
#else
|
||||
#define DX_DRIVER_RUNTIME_PM NULL
|
||||
|
||||
@@ -93,7 +93,7 @@
|
||||
|
||||
/* Logging macros */
|
||||
#define SSI_LOG(level, format, ...) \
|
||||
printk(level "cc715ree::%s: " format , __func__, ##__VA_ARGS__)
|
||||
printk(level "cc715ree::%s: " format, __func__, ##__VA_ARGS__)
|
||||
#define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__)
|
||||
#define SSI_LOG_WARNING(format, ...) SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__)
|
||||
#define SSI_LOG_NOTICE(format, ...) SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__)
|
||||
@@ -107,7 +107,7 @@
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
|
||||
#define SSI_MAX_IVGEN_DMA_ADDRESSES 3
|
||||
#define SSI_MAX_IVGEN_DMA_ADDRESSES 3
|
||||
struct ssi_crypto_req {
|
||||
void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base);
|
||||
void *user_arg;
|
||||
|
||||
@@ -153,20 +153,20 @@
|
||||
#define NIST_TDES_VECTOR_SIZE 8
|
||||
#define NIST_TDES_IV_SIZE 8
|
||||
|
||||
#define NIST_TDES_ECB_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
#define NIST_TDES_ECB_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
|
||||
#define NIST_TDES_ECB3_KEY { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, \
|
||||
0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0x01, \
|
||||
0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0x01, 0x23 }
|
||||
#define NIST_TDES_ECB3_PLAIN_DATA { 0x54, 0x68, 0x65, 0x20, 0x71, 0x75, 0x66, 0x63 }
|
||||
#define NIST_TDES_ECB3_CIPHER { 0xa8, 0x26, 0xfd, 0x8c, 0xe5, 0x3b, 0x85, 0x5f }
|
||||
#define NIST_TDES_ECB3_PLAIN_DATA { 0x54, 0x68, 0x65, 0x20, 0x71, 0x75, 0x66, 0x63 }
|
||||
#define NIST_TDES_ECB3_CIPHER { 0xa8, 0x26, 0xfd, 0x8c, 0xe5, 0x3b, 0x85, 0x5f }
|
||||
|
||||
#define NIST_TDES_CBC3_IV { 0xf8, 0xee, 0xe1, 0x35, 0x9c, 0x6e, 0x54, 0x40 }
|
||||
#define NIST_TDES_CBC3_IV { 0xf8, 0xee, 0xe1, 0x35, 0x9c, 0x6e, 0x54, 0x40 }
|
||||
#define NIST_TDES_CBC3_KEY { 0xe9, 0xda, 0x37, 0xf8, 0xdc, 0x97, 0x6d, 0x5b, \
|
||||
0xb6, 0x8c, 0x04, 0xe3, 0xec, 0x98, 0x20, 0x15, \
|
||||
0xf4, 0x0e, 0x08, 0xb5, 0x97, 0x29, 0xf2, 0x8f }
|
||||
#define NIST_TDES_CBC3_PLAIN_DATA { 0x3b, 0xb7, 0xa7, 0xdb, 0xa3, 0xd5, 0x92, 0x91 }
|
||||
#define NIST_TDES_CBC3_CIPHER { 0x5b, 0x84, 0x24, 0xd2, 0x39, 0x3e, 0x55, 0xa2 }
|
||||
#define NIST_TDES_CBC3_PLAIN_DATA { 0x3b, 0xb7, 0xa7, 0xdb, 0xa3, 0xd5, 0x92, 0x91 }
|
||||
#define NIST_TDES_CBC3_CIPHER { 0x5b, 0x84, 0x24, 0xd2, 0x39, 0x3e, 0x55, 0xa2 }
|
||||
|
||||
|
||||
/* NIST AES-CCM */
|
||||
|
||||
@@ -214,8 +214,8 @@ static const FipsCipherData FipsCipherDataTable[] = {
|
||||
{ 1, NIST_AES_256_XTS_KEY, CC_AES_256_BIT_KEY_SIZE, NIST_AES_256_XTS_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_XTS, NIST_AES_256_XTS_PLAIN, NIST_AES_256_XTS_CIPHER, NIST_AES_256_XTS_VECTOR_SIZE },
|
||||
{ 1, NIST_AES_256_XTS_KEY, CC_AES_256_BIT_KEY_SIZE, NIST_AES_256_XTS_IV, DRV_CRYPTO_DIRECTION_DECRYPT, DRV_CIPHER_XTS, NIST_AES_256_XTS_CIPHER, NIST_AES_256_XTS_PLAIN, NIST_AES_256_XTS_VECTOR_SIZE },
|
||||
#if (CC_SUPPORT_SHA > 256)
|
||||
{ 1, NIST_AES_512_XTS_KEY, 2*CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_VECTOR_SIZE },
|
||||
{ 1, NIST_AES_512_XTS_KEY, 2*CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_DECRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_VECTOR_SIZE },
|
||||
{ 1, NIST_AES_512_XTS_KEY, 2 * CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_VECTOR_SIZE },
|
||||
{ 1, NIST_AES_512_XTS_KEY, 2 * CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_DECRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_VECTOR_SIZE },
|
||||
#endif
|
||||
/* DES */
|
||||
{ 0, NIST_TDES_ECB3_KEY, CC_DRV_DES_TRIPLE_KEY_SIZE, NIST_TDES_ECB_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_ECB, NIST_TDES_ECB3_PLAIN_DATA, NIST_TDES_ECB3_CIPHER, NIST_TDES_VECTOR_SIZE },
|
||||
@@ -277,9 +277,9 @@ FIPS_CipherToFipsError(enum drv_cipher_mode mode, bool is_aes)
|
||||
switch (mode)
|
||||
{
|
||||
case DRV_CIPHER_ECB:
|
||||
return is_aes ? CC_REE_FIPS_ERROR_AES_ECB_PUT : CC_REE_FIPS_ERROR_DES_ECB_PUT ;
|
||||
return is_aes ? CC_REE_FIPS_ERROR_AES_ECB_PUT : CC_REE_FIPS_ERROR_DES_ECB_PUT;
|
||||
case DRV_CIPHER_CBC:
|
||||
return is_aes ? CC_REE_FIPS_ERROR_AES_CBC_PUT : CC_REE_FIPS_ERROR_DES_CBC_PUT ;
|
||||
return is_aes ? CC_REE_FIPS_ERROR_AES_CBC_PUT : CC_REE_FIPS_ERROR_DES_CBC_PUT;
|
||||
case DRV_CIPHER_OFB:
|
||||
return CC_REE_FIPS_ERROR_AES_OFB_PUT;
|
||||
case DRV_CIPHER_CTR:
|
||||
@@ -332,7 +332,7 @@ ssi_cipher_fips_run_test(struct ssi_drvdata *drvdata,
|
||||
set_flow_mode(&desc[idx], s_flow_mode);
|
||||
set_cipher_mode(&desc[idx], cipher_mode);
|
||||
if ((cipher_mode == DRV_CIPHER_CTR) ||
|
||||
(cipher_mode == DRV_CIPHER_OFB) ) {
|
||||
(cipher_mode == DRV_CIPHER_OFB)) {
|
||||
set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
|
||||
} else {
|
||||
set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
|
||||
@@ -432,7 +432,7 @@ ssi_cipher_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffe
|
||||
{
|
||||
FipsCipherData *cipherData = (FipsCipherData*)&FipsCipherDataTable[i];
|
||||
int rc = 0;
|
||||
size_t iv_size = cipherData->isAes ? NIST_AES_IV_SIZE : NIST_TDES_IV_SIZE ;
|
||||
size_t iv_size = cipherData->isAes ? NIST_AES_IV_SIZE : NIST_TDES_IV_SIZE;
|
||||
|
||||
memset(cpu_addr_buffer, 0, sizeof(struct fips_cipher_ctx));
|
||||
|
||||
|
||||
@@ -88,9 +88,9 @@ static void ssi_fips_update_tee_upon_ree_status(struct ssi_drvdata *drvdata, ssi
|
||||
{
|
||||
void __iomem *cc_base = drvdata->cc_base;
|
||||
if (err == CC_REE_FIPS_ERROR_OK) {
|
||||
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS|CC_FIPS_SYNC_MODULE_OK));
|
||||
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS | CC_FIPS_SYNC_MODULE_OK));
|
||||
} else {
|
||||
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS|CC_FIPS_SYNC_MODULE_ERROR));
|
||||
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS | CC_FIPS_SYNC_MODULE_ERROR));
|
||||
}
|
||||
}
|
||||
|
||||
@@ -305,7 +305,7 @@ int ssi_fips_init(struct ssi_drvdata *p_drvdata)
|
||||
|
||||
FIPS_DBG("CC FIPS code .. (fips=%d) \n", ssi_fips_support);
|
||||
|
||||
fips_h = kzalloc(sizeof(struct ssi_fips_handle),GFP_KERNEL);
|
||||
fips_h = kzalloc(sizeof(struct ssi_fips_handle), GFP_KERNEL);
|
||||
if (fips_h == NULL) {
|
||||
ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL);
|
||||
return -ENOMEM;
|
||||
@@ -329,7 +329,7 @@ int ssi_fips_init(struct ssi_drvdata *p_drvdata)
|
||||
#endif
|
||||
|
||||
/* init fips driver data */
|
||||
rc = ssi_fips_set_state((ssi_fips_support == 0)? CC_FIPS_STATE_NOT_SUPPORTED : CC_FIPS_STATE_SUPPORTED);
|
||||
rc = ssi_fips_set_state((ssi_fips_support == 0) ? CC_FIPS_STATE_NOT_SUPPORTED : CC_FIPS_STATE_SUPPORTED);
|
||||
if (unlikely(rc != 0)) {
|
||||
ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL);
|
||||
rc = -EAGAIN;
|
||||
|
||||
@@ -24,24 +24,24 @@
|
||||
struct ssi_drvdata;
|
||||
|
||||
// IG - how to make 1 file for TEE and REE
|
||||
typedef enum CC_FipsSyncStatus{
|
||||
CC_FIPS_SYNC_MODULE_OK = 0x0,
|
||||
CC_FIPS_SYNC_MODULE_ERROR = 0x1,
|
||||
CC_FIPS_SYNC_REE_STATUS = 0x4,
|
||||
CC_FIPS_SYNC_TEE_STATUS = 0x8,
|
||||
CC_FIPS_SYNC_STATUS_RESERVE32B = S32_MAX
|
||||
}CCFipsSyncStatus_t;
|
||||
typedef enum CC_FipsSyncStatus {
|
||||
CC_FIPS_SYNC_MODULE_OK = 0x0,
|
||||
CC_FIPS_SYNC_MODULE_ERROR = 0x1,
|
||||
CC_FIPS_SYNC_REE_STATUS = 0x4,
|
||||
CC_FIPS_SYNC_TEE_STATUS = 0x8,
|
||||
CC_FIPS_SYNC_STATUS_RESERVE32B = S32_MAX
|
||||
} CCFipsSyncStatus_t;
|
||||
|
||||
|
||||
#define CHECK_AND_RETURN_UPON_FIPS_ERROR() {\
|
||||
if (ssi_fips_check_fips_error() != 0) {\
|
||||
return -ENOEXEC;\
|
||||
}\
|
||||
} \
|
||||
}
|
||||
#define CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR() {\
|
||||
if (ssi_fips_check_fips_error() != 0) {\
|
||||
return;\
|
||||
}\
|
||||
} \
|
||||
}
|
||||
#define SSI_FIPS_INIT(p_drvData) (ssi_fips_init(p_drvData))
|
||||
#define SSI_FIPS_FINI(p_drvData) (ssi_fips_fini(p_drvData))
|
||||
|
||||
@@ -111,7 +111,7 @@ struct ssi_hash_ctx {
|
||||
static void ssi_hash_create_data_desc(
|
||||
struct ahash_req_ctx *areq_ctx,
|
||||
struct ssi_hash_ctx *ctx,
|
||||
unsigned int flow_mode,struct cc_hw_desc desc[],
|
||||
unsigned int flow_mode, struct cc_hw_desc desc[],
|
||||
bool is_not_last_data,
|
||||
unsigned int *seq_size);
|
||||
|
||||
@@ -158,22 +158,22 @@ static int ssi_hash_map_request(struct device *dev,
|
||||
struct cc_hw_desc desc;
|
||||
int rc = -ENOMEM;
|
||||
|
||||
state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE ,GFP_KERNEL|GFP_DMA);
|
||||
state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA);
|
||||
if (!state->buff0) {
|
||||
SSI_LOG_ERR("Allocating buff0 in context failed\n");
|
||||
goto fail0;
|
||||
}
|
||||
state->buff1 = kzalloc(SSI_MAX_HASH_BLCK_SIZE ,GFP_KERNEL|GFP_DMA);
|
||||
state->buff1 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA);
|
||||
if (!state->buff1) {
|
||||
SSI_LOG_ERR("Allocating buff1 in context failed\n");
|
||||
goto fail_buff0;
|
||||
}
|
||||
state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE ,GFP_KERNEL|GFP_DMA);
|
||||
state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE, GFP_KERNEL | GFP_DMA);
|
||||
if (!state->digest_result_buff) {
|
||||
SSI_LOG_ERR("Allocating digest_result_buff in context failed\n");
|
||||
goto fail_buff1;
|
||||
}
|
||||
state->digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL|GFP_DMA);
|
||||
state->digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA);
|
||||
if (!state->digest_buff) {
|
||||
SSI_LOG_ERR("Allocating digest-buffer in context failed\n");
|
||||
goto fail_digest_result_buff;
|
||||
@@ -181,7 +181,7 @@ static int ssi_hash_map_request(struct device *dev,
|
||||
|
||||
SSI_LOG_DEBUG("Allocated digest-buffer in context ctx->digest_buff=@%p\n", state->digest_buff);
|
||||
if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) {
|
||||
state->digest_bytes_len = kzalloc(HASH_LEN_SIZE, GFP_KERNEL|GFP_DMA);
|
||||
state->digest_bytes_len = kzalloc(HASH_LEN_SIZE, GFP_KERNEL | GFP_DMA);
|
||||
if (!state->digest_bytes_len) {
|
||||
SSI_LOG_ERR("Allocating digest-bytes-len in context failed\n");
|
||||
goto fail1;
|
||||
@@ -191,7 +191,7 @@ static int ssi_hash_map_request(struct device *dev,
|
||||
state->digest_bytes_len = NULL;
|
||||
}
|
||||
|
||||
state->opad_digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL|GFP_DMA);
|
||||
state->opad_digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA);
|
||||
if (!state->opad_digest_buff) {
|
||||
SSI_LOG_ERR("Allocating opad-digest-buffer in context failed\n");
|
||||
goto fail2;
|
||||
@@ -431,7 +431,7 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
|
||||
int rc = 0;
|
||||
|
||||
|
||||
SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac?"hmac":"hash", nbytes);
|
||||
SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
@@ -598,7 +598,7 @@ static int ssi_hash_update(struct ahash_req_ctx *state,
|
||||
int rc;
|
||||
|
||||
SSI_LOG_DEBUG("===== %s-update (%d) ====\n", ctx->is_hmac ?
|
||||
"hmac":"hash", nbytes);
|
||||
"hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
if (nbytes == 0) {
|
||||
@@ -696,11 +696,11 @@ static int ssi_hash_finup(struct ahash_req_ctx *state,
|
||||
int idx = 0;
|
||||
int rc;
|
||||
|
||||
SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac?"hmac":"hash", nbytes);
|
||||
SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src , nbytes, 1) != 0)) {
|
||||
if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) {
|
||||
SSI_LOG_ERR("map_ahash_request_final() failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
@@ -742,7 +742,7 @@ static int ssi_hash_finup(struct ahash_req_ctx *state,
|
||||
set_cipher_mode(&desc[idx], ctx->hw_mode);
|
||||
set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
|
||||
digestsize, NS_BIT, 0);
|
||||
ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]);
|
||||
ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]);
|
||||
set_flow_mode(&desc[idx], S_HASH_to_DOUT);
|
||||
set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
|
||||
idx++;
|
||||
@@ -792,7 +792,7 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
|
||||
set_flow_mode(&desc[idx], S_HASH_to_DOUT);
|
||||
set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
|
||||
set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
|
||||
ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]);
|
||||
ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]);
|
||||
set_cipher_mode(&desc[idx], ctx->hw_mode);
|
||||
idx++;
|
||||
|
||||
@@ -833,7 +833,7 @@ static int ssi_hash_final(struct ahash_req_ctx *state,
|
||||
int idx = 0;
|
||||
int rc;
|
||||
|
||||
SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac?"hmac":"hash", nbytes);
|
||||
SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
@@ -890,7 +890,7 @@ static int ssi_hash_final(struct ahash_req_ctx *state,
|
||||
set_cipher_mode(&desc[idx], ctx->hw_mode);
|
||||
set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
|
||||
digestsize, NS_BIT, 0);
|
||||
ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]);
|
||||
ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]);
|
||||
set_flow_mode(&desc[idx], S_HASH_to_DOUT);
|
||||
set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
|
||||
idx++;
|
||||
@@ -939,7 +939,7 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE);
|
||||
set_flow_mode(&desc[idx], S_HASH_to_DOUT);
|
||||
set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
|
||||
set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
|
||||
ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]);
|
||||
ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]);
|
||||
set_cipher_mode(&desc[idx], ctx->hw_mode);
|
||||
idx++;
|
||||
|
||||
@@ -1057,7 +1057,7 @@ static int ssi_hash_setkey(void *hash,
|
||||
set_flow_mode(&desc[idx], S_HASH_to_DOUT);
|
||||
set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
|
||||
set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
|
||||
ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]);
|
||||
ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]);
|
||||
idx++;
|
||||
|
||||
hw_desc_init(&desc[idx]);
|
||||
@@ -1871,7 +1871,7 @@ out:
|
||||
static int ssi_ahash_setkey(struct crypto_ahash *ahash,
|
||||
const u8 *key, unsigned int keylen)
|
||||
{
|
||||
return ssi_hash_setkey((void *) ahash, key, keylen, false);
|
||||
return ssi_hash_setkey((void *)ahash, key, keylen, false);
|
||||
}
|
||||
|
||||
struct ssi_hash_template {
|
||||
@@ -2143,7 +2143,7 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata)
|
||||
struct ssi_hash_handle *hash_handle = drvdata->hash_handle;
|
||||
ssi_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr;
|
||||
unsigned int larval_seq_len = 0;
|
||||
struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX/sizeof(u32)];
|
||||
struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)];
|
||||
int rc = 0;
|
||||
#if (DX_DEV_SHA_MAX > 256)
|
||||
int i;
|
||||
|
||||
@@ -31,7 +31,7 @@
|
||||
#include "ssi_pm.h"
|
||||
|
||||
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
|
||||
#define POWER_DOWN_ENABLE 0x01
|
||||
#define POWER_DOWN_DISABLE 0x00
|
||||
@@ -71,14 +71,14 @@ int ssi_power_mgr_runtime_resume(struct device *dev)
|
||||
}
|
||||
|
||||
rc = init_cc_regs(drvdata, false);
|
||||
if (rc !=0) {
|
||||
SSI_LOG_ERR("init_cc_regs (%x)\n",rc);
|
||||
if (rc != 0) {
|
||||
SSI_LOG_ERR("init_cc_regs (%x)\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = ssi_request_mgr_runtime_resume_queue(drvdata);
|
||||
if (rc !=0) {
|
||||
SSI_LOG_ERR("ssi_request_mgr_runtime_resume_queue (%x)\n",rc);
|
||||
if (rc != 0) {
|
||||
SSI_LOG_ERR("ssi_request_mgr_runtime_resume_queue (%x)\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
@@ -126,10 +126,10 @@ int ssi_power_mgr_runtime_put_suspend(struct device *dev)
|
||||
int ssi_power_mgr_init(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
int rc = 0;
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
struct platform_device *plat_dev = drvdata->plat_dev;
|
||||
/* must be before the enabling to avoid resdundent suspending */
|
||||
pm_runtime_set_autosuspend_delay(&plat_dev->dev,SSI_SUSPEND_TIMEOUT);
|
||||
pm_runtime_set_autosuspend_delay(&plat_dev->dev, SSI_SUSPEND_TIMEOUT);
|
||||
pm_runtime_use_autosuspend(&plat_dev->dev);
|
||||
/* activate the PM module */
|
||||
rc = pm_runtime_set_active(&plat_dev->dev);
|
||||
@@ -143,7 +143,7 @@ int ssi_power_mgr_init(struct ssi_drvdata *drvdata)
|
||||
|
||||
void ssi_power_mgr_fini(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
struct platform_device *plat_dev = drvdata->plat_dev;
|
||||
|
||||
pm_runtime_disable(&plat_dev->dev);
|
||||
|
||||
@@ -32,7 +32,7 @@ int ssi_power_mgr_init(struct ssi_drvdata *drvdata);
|
||||
|
||||
void ssi_power_mgr_fini(struct ssi_drvdata *drvdata);
|
||||
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
int ssi_power_mgr_runtime_suspend(struct device *dev);
|
||||
|
||||
int ssi_power_mgr_runtime_resume(struct device *dev);
|
||||
|
||||
@@ -57,7 +57,7 @@ struct ssi_request_mgr_handle {
|
||||
#else
|
||||
struct tasklet_struct comptask;
|
||||
#endif
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
bool is_runtime_suspended;
|
||||
#endif
|
||||
};
|
||||
@@ -81,7 +81,7 @@ void request_mgr_fini(struct ssi_drvdata *drvdata)
|
||||
}
|
||||
|
||||
SSI_LOG_DEBUG("max_used_hw_slots=%d\n", (req_mgr_h->hw_queue_size -
|
||||
req_mgr_h->min_free_hw_slots) );
|
||||
req_mgr_h->min_free_hw_slots));
|
||||
SSI_LOG_DEBUG("max_used_sw_slots=%d\n", req_mgr_h->max_used_sw_slots);
|
||||
|
||||
#ifdef COMP_IN_WQ
|
||||
@@ -101,7 +101,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata)
|
||||
struct ssi_request_mgr_handle *req_mgr_h;
|
||||
int rc = 0;
|
||||
|
||||
req_mgr_h = kzalloc(sizeof(struct ssi_request_mgr_handle),GFP_KERNEL);
|
||||
req_mgr_h = kzalloc(sizeof(struct ssi_request_mgr_handle), GFP_KERNEL);
|
||||
if (req_mgr_h == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto req_mgr_init_err;
|
||||
@@ -168,13 +168,13 @@ static inline void enqueue_seq(
|
||||
int i;
|
||||
|
||||
for (i = 0; i < seq_len; i++) {
|
||||
writel_relaxed(seq[i].word[0], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[1], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[2], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[3], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[4], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[0], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[1], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[2], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[3], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[4], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
wmb();
|
||||
writel_relaxed(seq[i].word[5], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
writel_relaxed(seq[i].word[5], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0)));
|
||||
#ifdef DX_DUMP_DESCS
|
||||
SSI_LOG_DEBUG("desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
|
||||
seq[i].word[0], seq[i].word[1], seq[i].word[2], seq[i].word[3], seq[i].word[4], seq[i].word[5]);
|
||||
@@ -215,11 +215,11 @@ static inline int request_mgr_queues_status_check(
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if ((likely(req_mgr_h->q_free_slots >= total_seq_len)) ) {
|
||||
if ((likely(req_mgr_h->q_free_slots >= total_seq_len))) {
|
||||
return 0;
|
||||
}
|
||||
/* Wait for space in HW queue. Poll constant num of iterations. */
|
||||
for (poll_queue =0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue ++) {
|
||||
for (poll_queue = 0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue++) {
|
||||
req_mgr_h->q_free_slots =
|
||||
CC_HAL_READ_REGISTER(
|
||||
CC_REG_OFFSET(CRY_KERNEL,
|
||||
@@ -229,7 +229,7 @@ static inline int request_mgr_queues_status_check(
|
||||
req_mgr_h->min_free_hw_slots = req_mgr_h->q_free_slots;
|
||||
}
|
||||
|
||||
if (likely (req_mgr_h->q_free_slots >= total_seq_len)) {
|
||||
if (likely(req_mgr_h->q_free_slots >= total_seq_len)) {
|
||||
/* If there is enough place return */
|
||||
return 0;
|
||||
}
|
||||
@@ -255,8 +255,8 @@ static inline int request_mgr_queues_status_check(
|
||||
* \param desc The crypto sequence
|
||||
* \param len The crypto sequence length
|
||||
* \param is_dout If "true": completion is handled by the caller
|
||||
* If "false": this function adds a dummy descriptor completion
|
||||
* and waits upon completion signal.
|
||||
* If "false": this function adds a dummy descriptor completion
|
||||
* and waits upon completion signal.
|
||||
*
|
||||
* \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false"
|
||||
*/
|
||||
@@ -273,13 +273,13 @@ int send_request(
|
||||
int rc;
|
||||
unsigned int max_required_seq_len = (total_seq_len +
|
||||
((ssi_req->ivgen_dma_addr_len == 0) ? 0 :
|
||||
SSI_IVPOOL_SEQ_LEN ) +
|
||||
((is_dout == 0 )? 1 : 0));
|
||||
SSI_IVPOOL_SEQ_LEN) +
|
||||
((is_dout == 0) ? 1 : 0));
|
||||
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
rc = ssi_power_mgr_runtime_get(&drvdata->plat_dev->dev);
|
||||
if (rc != 0) {
|
||||
SSI_LOG_ERR("ssi_power_mgr_runtime_get returned %x\n",rc);
|
||||
SSI_LOG_ERR("ssi_power_mgr_runtime_get returned %x\n", rc);
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
@@ -294,7 +294,7 @@ int send_request(
|
||||
rc = request_mgr_queues_status_check(req_mgr_h,
|
||||
cc_base,
|
||||
max_required_seq_len);
|
||||
if (likely(rc == 0 ))
|
||||
if (likely(rc == 0))
|
||||
/* There is enough place in the queue */
|
||||
break;
|
||||
/* something wrong release the spinlock*/
|
||||
@@ -304,7 +304,7 @@ int send_request(
|
||||
/* Any error other than HW queue full
|
||||
* (SW queue is full)
|
||||
*/
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev);
|
||||
#endif
|
||||
return rc;
|
||||
@@ -339,7 +339,7 @@ int send_request(
|
||||
if (unlikely(rc != 0)) {
|
||||
SSI_LOG_ERR("Failed to generate IV (rc=%d)\n", rc);
|
||||
spin_unlock_bh(&req_mgr_h->hw_lock);
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev);
|
||||
#endif
|
||||
return rc;
|
||||
@@ -348,7 +348,7 @@ int send_request(
|
||||
total_seq_len += iv_seq_len;
|
||||
}
|
||||
|
||||
used_sw_slots = ((req_mgr_h->req_queue_head - req_mgr_h->req_queue_tail) & (MAX_REQUEST_QUEUE_SIZE-1));
|
||||
used_sw_slots = ((req_mgr_h->req_queue_head - req_mgr_h->req_queue_tail) & (MAX_REQUEST_QUEUE_SIZE - 1));
|
||||
if (unlikely(used_sw_slots > req_mgr_h->max_used_sw_slots)) {
|
||||
req_mgr_h->max_used_sw_slots = used_sw_slots;
|
||||
}
|
||||
@@ -412,7 +412,7 @@ int send_request_init(
|
||||
|
||||
/* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */
|
||||
rc = request_mgr_queues_status_check(req_mgr_h, cc_base, total_seq_len);
|
||||
if (unlikely(rc != 0 )) {
|
||||
if (unlikely(rc != 0)) {
|
||||
return rc;
|
||||
}
|
||||
set_queue_last_ind(&desc[(len - 1)]);
|
||||
@@ -455,11 +455,11 @@ static void proc_completions(struct ssi_drvdata *drvdata)
|
||||
struct platform_device *plat_dev = drvdata->plat_dev;
|
||||
struct ssi_request_mgr_handle * request_mgr_handle =
|
||||
drvdata->request_mgr_handle;
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
int rc = 0;
|
||||
#endif
|
||||
|
||||
while(request_mgr_handle->axi_completed) {
|
||||
while (request_mgr_handle->axi_completed) {
|
||||
request_mgr_handle->axi_completed--;
|
||||
|
||||
/* Dequeue request */
|
||||
@@ -480,7 +480,7 @@ static void proc_completions(struct ssi_drvdata *drvdata)
|
||||
u32 axi_err;
|
||||
int i;
|
||||
SSI_LOG_INFO("Delay\n");
|
||||
for (i=0;i<1000000;i++) {
|
||||
for (i = 0; i < 1000000; i++) {
|
||||
axi_err = READ_REGISTER(drvdata->cc_base + CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR));
|
||||
}
|
||||
}
|
||||
@@ -492,10 +492,10 @@ static void proc_completions(struct ssi_drvdata *drvdata)
|
||||
request_mgr_handle->req_queue_tail = (request_mgr_handle->req_queue_tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1);
|
||||
SSI_LOG_DEBUG("Dequeue request tail=%u\n", request_mgr_handle->req_queue_tail);
|
||||
SSI_LOG_DEBUG("Request completed. axi_completed=%d\n", request_mgr_handle->axi_completed);
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
rc = ssi_power_mgr_runtime_put_suspend(&plat_dev->dev);
|
||||
if (rc != 0) {
|
||||
SSI_LOG_ERR("Failed to set runtime suspension %d\n",rc);
|
||||
SSI_LOG_ERR("Failed to set runtime suspension %d\n", rc);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@@ -561,7 +561,7 @@ static void comp_handler(unsigned long devarg)
|
||||
* resume the queue configuration - no need to take the lock as this happens inside
|
||||
* the spin lock protection
|
||||
*/
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
struct ssi_request_mgr_handle * request_mgr_handle = drvdata->request_mgr_handle;
|
||||
@@ -570,7 +570,7 @@ int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata)
|
||||
request_mgr_handle->is_runtime_suspended = false;
|
||||
spin_unlock_bh(&request_mgr_handle->hw_lock);
|
||||
|
||||
return 0 ;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -600,7 +600,7 @@ bool ssi_request_mgr_is_queue_runtime_suspend(struct ssi_drvdata *drvdata)
|
||||
struct ssi_request_mgr_handle * request_mgr_handle =
|
||||
drvdata->request_mgr_handle;
|
||||
|
||||
return request_mgr_handle->is_runtime_suspended;
|
||||
return request_mgr_handle->is_runtime_suspended;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -33,8 +33,8 @@ int request_mgr_init(struct ssi_drvdata *drvdata);
|
||||
* \param desc The crypto sequence
|
||||
* \param len The crypto sequence length
|
||||
* \param is_dout If "true": completion is handled by the caller
|
||||
* If "false": this function adds a dummy descriptor completion
|
||||
* and waits upon completion signal.
|
||||
* If "false": this function adds a dummy descriptor completion
|
||||
* and waits upon completion signal.
|
||||
*
|
||||
* \return int Returns -EINPROGRESS if "is_dout=ture"; "0" if "is_dout=false"
|
||||
*/
|
||||
@@ -49,7 +49,7 @@ void complete_request(struct ssi_drvdata *drvdata);
|
||||
|
||||
void request_mgr_fini(struct ssi_drvdata *drvdata);
|
||||
|
||||
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
|
||||
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
|
||||
int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata);
|
||||
|
||||
int ssi_request_mgr_runtime_suspend_queue(struct ssi_drvdata *drvdata);
|
||||
|
||||
@@ -66,7 +66,7 @@ static struct stat_name stat_name_db[MAX_STAT_OP_TYPES] =
|
||||
.stat_phase_name[STAT_PHASE_5] = "Sequence completion",
|
||||
.stat_phase_name[STAT_PHASE_6] = "HW cycles",
|
||||
},
|
||||
{ .op_type_name = "Setkey",
|
||||
{ .op_type_name = "Setkey",
|
||||
.stat_phase_name[STAT_PHASE_0] = "Init and sanity checks",
|
||||
.stat_phase_name[STAT_PHASE_1] = "Copy key to ctx",
|
||||
.stat_phase_name[STAT_PHASE_2] = "Create sequence",
|
||||
@@ -114,8 +114,8 @@ static void init_db(struct stat_item item[MAX_STAT_OP_TYPES][MAX_STAT_PHASES])
|
||||
unsigned int i, j;
|
||||
|
||||
/* Clear db */
|
||||
for (i=0; i<MAX_STAT_OP_TYPES; i++) {
|
||||
for (j=0; j<MAX_STAT_PHASES; j++) {
|
||||
for (i = 0; i < MAX_STAT_OP_TYPES; i++) {
|
||||
for (j = 0; j < MAX_STAT_PHASES; j++) {
|
||||
item[i][j].min = 0xFFFFFFFF;
|
||||
item[i][j].max = 0;
|
||||
item[i][j].sum = 0;
|
||||
@@ -130,7 +130,7 @@ static void update_db(struct stat_item *item, unsigned int result)
|
||||
item->sum += result;
|
||||
if (result < item->min)
|
||||
item->min = result;
|
||||
if (result > item->max )
|
||||
if (result > item->max)
|
||||
item->max = result;
|
||||
}
|
||||
|
||||
@@ -139,8 +139,8 @@ static void display_db(struct stat_item item[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]
|
||||
unsigned int i, j;
|
||||
u64 avg;
|
||||
|
||||
for (i=STAT_OP_TYPE_ENCODE; i<MAX_STAT_OP_TYPES; i++) {
|
||||
for (j=0; j<MAX_STAT_PHASES; j++) {
|
||||
for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) {
|
||||
for (j = 0; j < MAX_STAT_PHASES; j++) {
|
||||
if (item[i][j].count > 0) {
|
||||
avg = (u64)item[i][j].sum;
|
||||
do_div(avg, item[i][j].count);
|
||||
@@ -174,18 +174,18 @@ static ssize_t ssi_sys_stats_cc_db_clear(struct kobject *kobj,
|
||||
static ssize_t ssi_sys_stat_host_db_show(struct kobject *kobj,
|
||||
struct kobj_attribute *attr, char *buf)
|
||||
{
|
||||
int i, j ;
|
||||
int i, j;
|
||||
char line[512];
|
||||
u32 min_cyc, max_cyc;
|
||||
u64 avg;
|
||||
ssize_t buf_len, tmp_len=0;
|
||||
ssize_t buf_len, tmp_len = 0;
|
||||
|
||||
buf_len = scnprintf(buf,PAGE_SIZE,
|
||||
buf_len = scnprintf(buf, PAGE_SIZE,
|
||||
"phase\t\t\t\t\t\t\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n");
|
||||
if ( buf_len <0 )/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
return buf_len;
|
||||
for (i=STAT_OP_TYPE_ENCODE; i<MAX_STAT_OP_TYPES; i++) {
|
||||
for (j=0; j<MAX_STAT_PHASES-1; j++) {
|
||||
for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) {
|
||||
for (j = 0; j < MAX_STAT_PHASES - 1; j++) {
|
||||
if (stat_host_db[i][j].count > 0) {
|
||||
avg = (u64)stat_host_db[i][j].sum;
|
||||
do_div(avg, stat_host_db[i][j].count);
|
||||
@@ -194,18 +194,18 @@ static ssize_t ssi_sys_stat_host_db_show(struct kobject *kobj,
|
||||
} else {
|
||||
avg = min_cyc = max_cyc = 0;
|
||||
}
|
||||
tmp_len = scnprintf(line,512,
|
||||
tmp_len = scnprintf(line, 512,
|
||||
"%s::%s\t\t\t\t\t%6u\t%6u\t%6u\t%7u\n",
|
||||
stat_name_db[i].op_type_name,
|
||||
stat_name_db[i].stat_phase_name[j],
|
||||
min_cyc, (unsigned int)avg, max_cyc,
|
||||
stat_host_db[i][j].count);
|
||||
if ( tmp_len <0 )/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
return buf_len;
|
||||
if ( buf_len + tmp_len >= PAGE_SIZE)
|
||||
if (buf_len + tmp_len >= PAGE_SIZE)
|
||||
return buf_len;
|
||||
buf_len += tmp_len;
|
||||
strncat(buf, line,512);
|
||||
strncat(buf, line, 512);
|
||||
}
|
||||
}
|
||||
return buf_len;
|
||||
@@ -218,13 +218,13 @@ static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj,
|
||||
char line[256];
|
||||
u32 min_cyc, max_cyc;
|
||||
u64 avg;
|
||||
ssize_t buf_len,tmp_len=0;
|
||||
ssize_t buf_len, tmp_len = 0;
|
||||
|
||||
buf_len = scnprintf(buf,PAGE_SIZE,
|
||||
buf_len = scnprintf(buf, PAGE_SIZE,
|
||||
"phase\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n");
|
||||
if ( buf_len <0 )/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
return buf_len;
|
||||
for (i=STAT_OP_TYPE_ENCODE; i<MAX_STAT_OP_TYPES; i++) {
|
||||
for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) {
|
||||
if (stat_cc_db[i][STAT_PHASE_6].count > 0) {
|
||||
avg = (u64)stat_cc_db[i][STAT_PHASE_6].sum;
|
||||
do_div(avg, stat_cc_db[i][STAT_PHASE_6].count);
|
||||
@@ -233,7 +233,7 @@ static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj,
|
||||
} else {
|
||||
avg = min_cyc = max_cyc = 0;
|
||||
}
|
||||
tmp_len = scnprintf(line,256,
|
||||
tmp_len = scnprintf(line, 256,
|
||||
"%s\t%6u\t%6u\t%6u\t%7u\n",
|
||||
stat_name_db[i].op_type_name,
|
||||
min_cyc,
|
||||
@@ -241,13 +241,13 @@ static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj,
|
||||
max_cyc,
|
||||
stat_cc_db[i][STAT_PHASE_6].count);
|
||||
|
||||
if ( tmp_len < 0 )/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/
|
||||
return buf_len;
|
||||
|
||||
if ( buf_len + tmp_len >= PAGE_SIZE)
|
||||
if (buf_len + tmp_len >= PAGE_SIZE)
|
||||
return buf_len;
|
||||
buf_len += tmp_len;
|
||||
strncat(buf, line,256);
|
||||
strncat(buf, line, 256);
|
||||
}
|
||||
return buf_len;
|
||||
}
|
||||
@@ -304,7 +304,7 @@ static ssize_t ssi_sys_regdump_show(struct kobject *kobj,
|
||||
static ssize_t ssi_sys_help_show(struct kobject *kobj,
|
||||
struct kobj_attribute *attr, char *buf)
|
||||
{
|
||||
char* help_str[]={
|
||||
char* help_str[] = {
|
||||
"cat reg_dump ", "Print several of CC register values",
|
||||
#if defined CC_CYCLE_COUNT
|
||||
"cat stats_host ", "Print host statistics",
|
||||
@@ -313,11 +313,11 @@ static ssize_t ssi_sys_help_show(struct kobject *kobj,
|
||||
"echo <number> > stats_cc ", "Clear CC statistics database",
|
||||
#endif
|
||||
};
|
||||
int i=0, offset = 0;
|
||||
int i = 0, offset = 0;
|
||||
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "Usage:\n");
|
||||
for ( i = 0; i < ARRAY_SIZE(help_str); i+=2) {
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s\t\t%s\n", help_str[i], help_str[i+1]);
|
||||
for (i = 0; i < ARRAY_SIZE(help_str); i += 2) {
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s\t\t%s\n", help_str[i], help_str[i + 1]);
|
||||
}
|
||||
return offset;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user