Merge tag 'wireless-drivers-next-2021-04-23' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next

Kalle Valo says:

====================
wireless-drivers-next patches for v5.13

Third, and final, set of patches for v5.13. We got one more week
before the merge window and this includes from that extra week.
Smaller features to rtw88 and mt76, but mostly this contains fixes.

rtw88

* 8822c: Add gap-k calibration to improve long range performance

mt76

* parse rate power limits from DT

* debugfs file to test firmware crash

* debugfs to disable NAPI threaded mode
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2021-04-23 13:58:25 -07:00
81 changed files with 3433 additions and 1162 deletions
@@ -72,6 +72,90 @@ properties:
led-sources:
maxItems: 1
power-limits:
type: object
additionalProperties: false
patternProperties:
"^r[0-9]+":
type: object
additionalProperties: false
properties:
regdomain:
$ref: /schemas/types.yaml#/definitions/string
description:
Regdomain refers to a legal regulatory region. Different
countries define different levels of allowable transmitter
power, time that a channel can be occupied, and different
available channels
enum:
- FCC
- ETSI
- JP
patternProperties:
"^txpower-[256]g$":
type: object
additionalProperties: false
patternProperties:
"^b[0-9]+$":
type: object
additionalProperties: false
properties:
channels:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
description:
Pairs of first and last channel number of the selected
band
rates-cck:
$ref: /schemas/types.yaml#/definitions/uint8-array
minItems: 4
maxItems: 4
description:
4 half-dBm per-rate power limit values
rates-ofdm:
$ref: /schemas/types.yaml#/definitions/uint8-array
minItems: 8
maxItems: 8
description:
8 half-dBm per-rate power limit values
rates-mcs:
$ref: /schemas/types.yaml#/definitions/uint8-matrix
description:
Sets of per-rate power limit values for 802.11n/802.11ac
rates for multiple channel bandwidth settings.
Each set starts with the number of channel bandwidth
settings for which the rate set applies, followed by
either 8 or 10 power limit values. The order of the
channel bandwidth settings is 20, 40, 80 and 160 MHz.
maxItems: 4
items:
minItems: 9
maxItems: 11
rates-ru:
$ref: /schemas/types.yaml#/definitions/uint8-matrix
description:
Sets of per-rate power limit values for 802.11ax rates
for multiple channel bandwidth or resource unit settings.
Each set starts with the number of channel bandwidth or
resource unit settings for which the rate set applies,
followed by 12 power limit values. The order of the
channel resource unit settings is RU26, RU52, RU106,
RU242/SU20, RU484/SU40, RU996/SU80 and RU2x996/SU160.
items:
minItems: 13
maxItems: 13
txs-delta:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Half-dBm power delta for different numbers of antennas
required:
- compatible
- reg
@@ -93,6 +177,29 @@ examples:
led {
led-sources = <2>;
};
power-limits {
r0 {
regdomain = "FCC";
txpower-5g {
b0 {
channels = <36 48>;
rates-ofdm = /bits/ 8 <23 23 23 23 23 23 23 23>;
rates-mcs = /bits/ 8 <1 23 23 23 23 23 23 23 23 23 23>,
<3 22 22 22 22 22 22 22 22 22 22>;
rates-ru = /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22 22 22>,
<4 20 20 20 20 20 20 20 20 20 20 20 20>;
};
b1 {
channels = <100 181>;
rates-ofdm = /bits/ 8 <14 14 14 14 14 14 14 14>;
rates-mcs = /bits/ 8 <4 14 14 14 14 14 14 14 14 14 14>;
txs-delta = <12 9 6>;
rates-ru = /bits/ 8 <7 14 14 14 14 14 14 14 14 14 14 14 14>;
};
};
};
};
};
};
+1 -1
View File
@@ -669,7 +669,7 @@ static int ath10k_htc_send_bundle(struct ath10k_htc_ep *ep,
ath10k_dbg(ar, ATH10K_DBG_HTC,
"bundle tx status %d eid %d req count %d count %d len %d\n",
ret, ep->eid, skb_queue_len(&ep->tx_req_head), cn, bundle_skb->len);
ret, ep->eid, skb_queue_len(&ep->tx_req_head), cn, skb_len);
return ret;
}
@@ -592,6 +592,9 @@ static void ath10k_wmi_event_tdls_peer(struct ath10k *ar, struct sk_buff *skb)
GFP_ATOMIC
);
break;
default:
kfree(tb);
return;
}
exit:
+12 -3
View File
@@ -349,10 +349,19 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
if (ab->hw_rev == ATH11K_HW_QCA6390_HW20)
ath11k_mhi_config = &ath11k_mhi_config_qca6390;
else if (ab->hw_rev == ATH11K_HW_QCN9074_HW10)
switch (ab->hw_rev) {
case ATH11K_HW_QCN9074_HW10:
ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
break;
case ATH11K_HW_QCA6390_HW20:
ath11k_mhi_config = &ath11k_mhi_config_qca6390;
break;
default:
ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n",
ab->hw_rev);
mhi_free_controller(mhi_ctrl);
return -EINVAL;
}
ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
if (ret) {
+1 -1
View File
@@ -2514,7 +2514,7 @@ static int ath11k_qmi_event_load_bdf(struct ath11k_qmi *qmi)
ret = ath11k_qmi_request_target_cap(ab);
if (ret < 0) {
ath11k_warn(ab, "failed to requeqst qmi target capabilities: %d\n",
ath11k_warn(ab, "failed to request qmi target capabilities: %d\n",
ret);
return ret;
}
@@ -246,7 +246,7 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
if (unlikely(r)) {
ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
reg_offset, r);
return -EIO;
return -1;
}
return be32_to_cpu(val);
+1 -1
View File
@@ -286,7 +286,7 @@ static bool ath9k_hw_read_revisions(struct ath_hw *ah)
srev = REG_READ(ah, AR_SREV);
if (srev == -EIO) {
if (srev == -1) {
ath_err(ath9k_hw_common(ah),
"Failed to read SREV register");
return false;
@@ -151,7 +151,7 @@ static void _brcmf_set_multicast_list(struct work_struct *work)
/* Send down the multicast list first. */
cnt = netdev_mc_count(ndev);
buflen = sizeof(cnt) + (cnt * ETH_ALEN);
buf = kmalloc(buflen, GFP_ATOMIC);
buf = kmalloc(buflen, GFP_KERNEL);
if (!buf)
return;
bufp = buf;
@@ -453,7 +453,6 @@ struct cmd_ds_802_11_beacon_set {
u8 beacon[MRVL_MAX_BCN_SIZE];
};
struct lbtf_private;
struct cmd_ctrl_node;
/** Function Prototype Declaration */
@@ -25,6 +25,32 @@ mt76_reg_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mt76_reg_get, mt76_reg_set,
"0x%08llx\n");
static int
mt76_napi_threaded_set(void *data, u64 val)
{
struct mt76_dev *dev = data;
if (!mt76_is_mmio(dev))
return -EOPNOTSUPP;
if (dev->napi_dev.threaded != val)
return dev_set_threaded(&dev->napi_dev, val);
return 0;
}
static int
mt76_napi_threaded_get(void *data, u64 *val)
{
struct mt76_dev *dev = data;
*val = dev->napi_dev.threaded;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_napi_threaded, mt76_napi_threaded_get,
mt76_napi_threaded_set, "%llu\n");
int mt76_queues_read(struct seq_file *s, void *data)
{
struct mt76_dev *dev = dev_get_drvdata(s->private);
@@ -102,6 +128,8 @@ struct dentry *mt76_register_debugfs(struct mt76_dev *dev)
debugfs_create_u32("regidx", 0600, dir, &dev->debugfs_reg);
debugfs_create_file_unsafe("regval", 0600, dir, dev,
&fops_regval);
debugfs_create_file_unsafe("napi_threaded", 0600, dir, dev,
&fops_napi_threaded);
debugfs_create_blob("eeprom", 0400, dir, &dev->eeprom);
if (dev->otp.data)
debugfs_create_blob("otp", 0400, dir, &dev->otp);
+5 -5
View File
@@ -602,8 +602,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
return done;
}
static int
mt76_dma_rx_poll(struct napi_struct *napi, int budget)
int mt76_dma_rx_poll(struct napi_struct *napi, int budget)
{
struct mt76_dev *dev;
int qid, done = 0, cur;
@@ -626,9 +625,11 @@ mt76_dma_rx_poll(struct napi_struct *napi, int budget)
return done;
}
EXPORT_SYMBOL_GPL(mt76_dma_rx_poll);
static int
mt76_dma_init(struct mt76_dev *dev)
mt76_dma_init(struct mt76_dev *dev,
int (*poll)(struct napi_struct *napi, int budget))
{
int i;
@@ -639,8 +640,7 @@ mt76_dma_init(struct mt76_dev *dev)
dev->napi_dev.threaded = 1;
mt76_for_each_q_rx(dev, i) {
netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll,
64);
netif_napi_add(&dev->napi_dev, &dev->napi[i], poll, 64);
mt76_dma_rx_fill(dev, &dev->q_rx[i]);
napi_enable(&dev->napi[i]);
}
+1
View File
@@ -45,6 +45,7 @@ enum mt76_mcu_evt_type {
EVT_EVENT_DFS_DETECT_RSP,
};
int mt76_dma_rx_poll(struct napi_struct *napi, int budget);
void mt76_dma_attach(struct mt76_dev *dev);
void mt76_dma_cleanup(struct mt76_dev *dev);
+225 -6
View File
@@ -9,8 +9,7 @@
#include <linux/etherdevice.h>
#include "mt76.h"
static int
mt76_get_of_eeprom(struct mt76_dev *dev, int len)
int mt76_get_of_eeprom(struct mt76_dev *dev, void *eep, int offset, int len)
{
#if defined(CONFIG_OF) && defined(CONFIG_MTD)
struct device_node *np = dev->dev->of_node;
@@ -18,7 +17,6 @@ mt76_get_of_eeprom(struct mt76_dev *dev, int len)
const __be32 *list;
const char *part;
phandle phandle;
int offset = 0;
int size;
size_t retlen;
int ret;
@@ -54,7 +52,7 @@ mt76_get_of_eeprom(struct mt76_dev *dev, int len)
}
offset = be32_to_cpup(list);
ret = mtd_read(mtd, offset, len, &retlen, dev->eeprom.data);
ret = mtd_read(mtd, offset, len, &retlen, eep);
put_mtd_device(mtd);
if (ret)
goto out_put_node;
@@ -65,7 +63,7 @@ mt76_get_of_eeprom(struct mt76_dev *dev, int len)
}
if (of_property_read_bool(dev->dev->of_node, "big-endian")) {
u8 *data = (u8 *)dev->eeprom.data;
u8 *data = (u8 *)eep;
int i;
/* convert eeprom data in Little Endian */
@@ -86,6 +84,7 @@ out_put_node:
return -ENOENT;
#endif
}
EXPORT_SYMBOL_GPL(mt76_get_of_eeprom);
void
mt76_eeprom_override(struct mt76_phy *phy)
@@ -104,6 +103,226 @@ mt76_eeprom_override(struct mt76_phy *phy)
}
EXPORT_SYMBOL_GPL(mt76_eeprom_override);
static bool mt76_string_prop_find(struct property *prop, const char *str)
{
const char *cp = NULL;
if (!prop || !str || !str[0])
return false;
while ((cp = of_prop_next_string(prop, cp)) != NULL)
if (!strcasecmp(cp, str))
return true;
return false;
}
static struct device_node *
mt76_find_power_limits_node(struct mt76_dev *dev)
{
struct device_node *np = dev->dev->of_node;
const char *const region_names[] = {
[NL80211_DFS_ETSI] = "etsi",
[NL80211_DFS_FCC] = "fcc",
[NL80211_DFS_JP] = "jp",
};
struct device_node *cur, *fallback = NULL;
const char *region_name = NULL;
if (dev->region < ARRAY_SIZE(region_names))
region_name = region_names[dev->region];
np = of_get_child_by_name(np, "power-limits");
if (!np)
return NULL;
for_each_child_of_node(np, cur) {
struct property *country = of_find_property(cur, "country", NULL);
struct property *regd = of_find_property(cur, "regdomain", NULL);
if (!country && !regd) {
fallback = cur;
continue;
}
if (mt76_string_prop_find(country, dev->alpha2) ||
mt76_string_prop_find(regd, region_name))
return cur;
}
return fallback;
}
static const __be32 *
mt76_get_of_array(struct device_node *np, char *name, size_t *len, int min)
{
struct property *prop = of_find_property(np, name, NULL);
if (!prop || !prop->value || prop->length < min * 4)
return NULL;
*len = prop->length;
return prop->value;
}
static struct device_node *
mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan)
{
struct device_node *cur;
const __be32 *val;
size_t len;
for_each_child_of_node(np, cur) {
val = mt76_get_of_array(cur, "channels", &len, 2);
if (!val)
continue;
while (len >= 2 * sizeof(*val)) {
if (chan->hw_value >= be32_to_cpu(val[0]) &&
chan->hw_value <= be32_to_cpu(val[1]))
return cur;
val += 2;
len -= 2 * sizeof(*val);
}
}
return NULL;
}
static s8
mt76_get_txs_delta(struct device_node *np, u8 nss)
{
const __be32 *val;
size_t len;
val = mt76_get_of_array(np, "txs-delta", &len, nss);
if (!val)
return 0;
return be32_to_cpu(val[nss - 1]);
}
static void
mt76_apply_array_limit(s8 *pwr, size_t pwr_len, const __be32 *data,
s8 target_power, s8 nss_delta, s8 *max_power)
{
int i;
if (!data)
return;
for (i = 0; i < pwr_len; i++) {
pwr[i] = min_t(s8, target_power,
be32_to_cpu(data[i]) + nss_delta);
*max_power = max(*max_power, pwr[i]);
}
}
static void
mt76_apply_multi_array_limit(s8 *pwr, size_t pwr_len, s8 pwr_num,
const __be32 *data, size_t len, s8 target_power,
s8 nss_delta, s8 *max_power)
{
int i, cur;
if (!data)
return;
len /= 4;
cur = be32_to_cpu(data[0]);
for (i = 0; i < pwr_num; i++) {
if (len < pwr_len + 1)
break;
mt76_apply_array_limit(pwr + pwr_len * i, pwr_len, data + 1,
target_power, nss_delta, max_power);
if (--cur > 0)
continue;
data += pwr_len + 1;
len -= pwr_len + 1;
if (!len)
break;
cur = be32_to_cpu(data[0]);
}
}
s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
struct ieee80211_channel *chan,
struct mt76_power_limits *dest,
s8 target_power)
{
struct mt76_dev *dev = phy->dev;
struct device_node *np;
const __be32 *val;
char name[16];
u32 mcs_rates = dev->drv->mcs_rates;
u32 ru_rates = ARRAY_SIZE(dest->ru[0]);
char band;
size_t len;
s8 max_power = 0;
s8 txs_delta;
if (!mcs_rates)
mcs_rates = 10;
memset(dest, target_power, sizeof(*dest));
if (!IS_ENABLED(CONFIG_OF))
return target_power;
np = mt76_find_power_limits_node(dev);
if (!np)
return target_power;
switch (chan->band) {
case NL80211_BAND_2GHZ:
band = '2';
break;
case NL80211_BAND_5GHZ:
band = '5';
break;
default:
return target_power;
}
snprintf(name, sizeof(name), "txpower-%cg", band);
np = of_get_child_by_name(np, name);
if (!np)
return target_power;
np = mt76_find_channel_node(np, chan);
if (!np)
return target_power;
txs_delta = mt76_get_txs_delta(np, hweight8(phy->antenna_mask));
val = mt76_get_of_array(np, "rates-cck", &len, ARRAY_SIZE(dest->cck));
mt76_apply_array_limit(dest->cck, ARRAY_SIZE(dest->cck), val,
target_power, txs_delta, &max_power);
val = mt76_get_of_array(np, "rates-ofdm",
&len, ARRAY_SIZE(dest->ofdm));
mt76_apply_array_limit(dest->ofdm, ARRAY_SIZE(dest->ofdm), val,
target_power, txs_delta, &max_power);
val = mt76_get_of_array(np, "rates-mcs", &len, mcs_rates + 1);
mt76_apply_multi_array_limit(dest->mcs[0], ARRAY_SIZE(dest->mcs[0]),
ARRAY_SIZE(dest->mcs), val, len,
target_power, txs_delta, &max_power);
val = mt76_get_of_array(np, "rates-ru", &len, ru_rates + 1);
mt76_apply_multi_array_limit(dest->ru[0], ARRAY_SIZE(dest->ru[0]),
ARRAY_SIZE(dest->ru), val, len,
target_power, txs_delta, &max_power);
return max_power;
}
EXPORT_SYMBOL_GPL(mt76_get_rate_power_limits);
int
mt76_eeprom_init(struct mt76_dev *dev, int len)
{
@@ -112,6 +331,6 @@ mt76_eeprom_init(struct mt76_dev *dev, int len)
if (!dev->eeprom.data)
return -ENOMEM;
return !mt76_get_of_eeprom(dev, len);
return !mt76_get_of_eeprom(dev, dev->eeprom.data, 0, len);
}
EXPORT_SYMBOL_GPL(mt76_eeprom_init);
@@ -428,6 +428,9 @@ mt76_alloc_device(struct device *pdev, unsigned int size,
mutex_init(&dev->mcu.mutex);
dev->tx_worker.fn = mt76_tx_worker;
spin_lock_init(&dev->token_lock);
idr_init(&dev->token);
INIT_LIST_HEAD(&dev->txwi_cache);
for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++)
-4
View File
@@ -99,10 +99,6 @@ int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
dev_kfree_skb(skb);
} while (ret == -EAGAIN);
/* notify driver code to reset the mcu */
if (ret == -ETIMEDOUT && dev->mcu_ops->mcu_reset)
dev->mcu_ops->mcu_reset(dev);
out:
mutex_unlock(&dev->mcu.mutex);
+68 -9
View File
@@ -17,12 +17,14 @@
#include "util.h"
#include "testmode.h"
#define MT_MCU_RING_SIZE 32
#define MT_RX_BUF_SIZE 2048
#define MT_SKB_HEAD_LEN 128
#define MT_MCU_RING_SIZE 32
#define MT_RX_BUF_SIZE 2048
#define MT_SKB_HEAD_LEN 128
#define MT_MAX_NON_AQL_PKT 16
#define MT_TXQ_FREE_THR 32
#define MT_MAX_NON_AQL_PKT 16
#define MT_TXQ_FREE_THR 32
#define MT76_TOKEN_FREE_THR 64
struct mt76_dev;
struct mt76_phy;
@@ -166,11 +168,11 @@ struct mt76_mcu_ops {
int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
struct mt76_reg_pair *rp, int len);
int (*mcu_restart)(struct mt76_dev *dev);
void (*mcu_reset)(struct mt76_dev *dev);
};
struct mt76_queue_ops {
int (*init)(struct mt76_dev *dev);
int (*init)(struct mt76_dev *dev,
int (*poll)(struct napi_struct *napi, int budget));
int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
int idx, int n_desc, int bufsize,
@@ -331,6 +333,8 @@ struct mt76_driver_ops {
u32 drv_flags;
u32 survey_flags;
u16 txwi_size;
u16 token_size;
u8 mcs_rates;
void (*update_survey)(struct mt76_dev *dev);
@@ -538,7 +542,7 @@ struct mt76_testmode_data {
struct sk_buff *tx_skb;
u32 tx_count;
u16 tx_msdu_len;
u16 tx_mpdu_len;
u8 tx_rate_mode;
u8 tx_rate_idx;
@@ -657,6 +661,10 @@ struct mt76_dev {
struct mt76_worker tx_worker;
struct napi_struct tx_napi;
spinlock_t token_lock;
struct idr token;
int token_count;
wait_queue_head_t tx_wait;
struct sk_buff_head status_list;
@@ -711,6 +719,13 @@ struct mt76_dev {
};
};
struct mt76_power_limits {
s8 cck[4];
s8 ofdm[8];
s8 mcs[4][10];
s8 ru[7][12];
};
enum mt76_phy_type {
MT_PHY_TYPE_CCK,
MT_PHY_TYPE_OFDM,
@@ -794,7 +809,7 @@ static inline u16 mt76_rev(struct mt76_dev *dev)
#define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
#define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
#define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76))
#define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
#define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
#define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__)
@@ -829,6 +844,7 @@ void mt76_seq_puts_array(struct seq_file *file, const char *str,
int mt76_eeprom_init(struct mt76_dev *dev, int len);
void mt76_eeprom_override(struct mt76_phy *phy);
int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len);
struct mt76_queue *
mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
@@ -1006,6 +1022,7 @@ void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
void mt76_txq_schedule_all(struct mt76_phy *phy);
void mt76_tx_worker_run(struct mt76_dev *dev);
void mt76_tx_worker(struct mt76_worker *w);
void mt76_release_buffered_frames(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
@@ -1074,6 +1091,7 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
struct netlink_callback *cb, void *data, int len);
int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
{
@@ -1194,4 +1212,45 @@ mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
struct ieee80211_channel *chan,
struct mt76_power_limits *dest,
s8 target_power);
struct mt76_txwi_cache *
mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
{
spin_lock_bh(&dev->token_lock);
__mt76_set_tx_blocked(dev, blocked);
spin_unlock_bh(&dev->token_lock);
}
static inline int
mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
{
int token;
spin_lock_bh(&dev->token_lock);
token = idr_alloc(&dev->token, *ptxwi, 0, dev->drv->token_size,
GFP_ATOMIC);
spin_unlock_bh(&dev->token_lock);
return token;
}
static inline struct mt76_txwi_cache *
mt76_token_put(struct mt76_dev *dev, int token)
{
struct mt76_txwi_cache *txwi;
spin_lock_bh(&dev->token_lock);
txwi = idr_remove(&dev->token, token);
spin_unlock_bh(&dev->token_lock);
return txwi;
}
#endif
@@ -219,7 +219,7 @@ int mt7603_dma_init(struct mt7603_dev *dev)
return ret;
mt76_wr(dev, MT_DELAY_INT_CFG, 0);
ret = mt76_init_queues(dev);
ret = mt76_init_queues(dev, mt76_dma_rx_poll);
if (ret)
return ret;
@@ -1445,6 +1445,8 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
mt76_queue_rx_reset(dev, i);
}
mt76_tx_status_check(&dev->mt76, NULL, true);
mt7603_dma_sched_reset(dev);
mt7603_mac_dma_start(dev);
@@ -21,9 +21,8 @@ mt7603_mcu_parse_response(struct mt76_dev *mdev, int cmd,
struct mt7603_mcu_rxd *rxd;
if (!skb) {
dev_err(mdev->dev,
"MCU message %d (seq %d) timed out\n",
cmd, seq);
dev_err(mdev->dev, "MCU message %02x (seq %d) timed out\n",
abs(cmd), seq);
dev->mcu_hang = MT7603_WATCHDOG_TIMEOUT;
return -ETIMEDOUT;
}
@@ -69,6 +69,7 @@ static int
mt7615_pm_set(void *data, u64 val)
{
struct mt7615_dev *dev = data;
struct mt76_connac_pm *pm = &dev->pm;
int ret = 0;
if (!mt7615_wait_for_mcu_init(dev))
@@ -77,6 +78,9 @@ mt7615_pm_set(void *data, u64 val)
if (!mt7615_firmware_offload(dev) || !mt76_is_mmio(&dev->mt76))
return -EOPNOTSUPP;
if (val == pm->enable)
return 0;
mt7615_mutex_acquire(dev);
if (dev->phy.n_beacon_vif) {
@@ -84,7 +88,11 @@ mt7615_pm_set(void *data, u64 val)
goto out;
}
dev->pm.enable = val;
if (!pm->enable) {
pm->stats.last_wake_event = jiffies;
pm->stats.last_doze_event = jiffies;
}
pm->enable = val;
out:
mt7615_mutex_release(dev);
@@ -103,6 +111,26 @@ mt7615_pm_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(fops_pm, mt7615_pm_get, mt7615_pm_set, "%lld\n");
static int
mt7615_pm_stats(struct seq_file *s, void *data)
{
struct mt7615_dev *dev = dev_get_drvdata(s->private);
struct mt76_connac_pm *pm = &dev->pm;
unsigned long awake_time = pm->stats.awake_time;
unsigned long doze_time = pm->stats.doze_time;
if (!test_bit(MT76_STATE_PM, &dev->mphy.state))
awake_time += jiffies - pm->stats.last_wake_event;
else
doze_time += jiffies - pm->stats.last_doze_event;
seq_printf(s, "awake time: %14u\ndoze time: %15u\n",
jiffies_to_msecs(awake_time),
jiffies_to_msecs(doze_time));
return 0;
}
static int
mt7615_pm_idle_timeout_set(void *data, u64 val)
{
@@ -515,6 +543,8 @@ int mt7615_init_debugfs(struct mt7615_dev *dev)
debugfs_create_file("runtime-pm", 0600, dir, dev, &fops_pm);
debugfs_create_file("idle-timeout", 0600, dir, dev,
&fops_pm_idle_timeout);
debugfs_create_devm_seqfile(dev->mt76.dev, "runtime_pm_stats", dir,
mt7615_pm_stats);
debugfs_create_devm_seqfile(dev->mt76.dev, "radio", dir,
mt7615_radio_read);

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