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Merge tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

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Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for v5.5.

  It is pretty much business as usual, the most interesting thing I
  think is the pin controller for a new Intel chip called Lightning
  Mountain, which is according to news reports some kind of embedded
  network processor and what is surprising about it is that Intel have
  decided to use device tree to describe the system rather than ACPI
  that they have traditionally favored.

  Core changes:

   - Avoid taking direct references to device tree-supplied device
     names: these may changed at runtime under certain circumstances to
     kstrdup them.

  GPIO related:

   - Work is ongoing to move to passing the irqchip along as a templated
     struct gpio_irq_chip when adding a standard gpiolib-based irqchip
     to a GPIO controller, a few patches in this cycle switches a few
     pin control drivers over to using this method.

  New hardware support:

   - Intel Lightning Mountain SoC pin controller and GPIO support, a
     first Intel platform to use device tree rather than ACPI to
     configure the system. News reports says that this SoC is a network
     processor.

   - Qualcomm MSM8976 and MSM8956

   - Qualcomm PMIC GPIO now also supports PM6150 and PM6150L

   - Qualcomm SPMI MPP and SPMI GPIO for PM8950 and PMI8950

   - Rockchip RK3308

   - Renesas R8A77961

   - Allwinner Meson-A1

  Driver improvements:

   - get_multiple and set_multiple support for the AT91-PIO4 driver.

   - Convert Qualcomm SSBI GPIO to use the hierarchical IRQ helpers in
     the GPIOlib irqchip"

* tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
  pinctrl: ingenic: Add OTG VBUS pin for the JZ4770
  pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config
  pinctrl: Fix Kconfig indentation
  pinctrl: lewisburg: Update pin list according to v1.1v6
  MAINTAINERS: Replace my email by one @kernel.org
  pinctrl: armada-37xx: Fix irq mask access in armada_37xx_irq_set_type()
  dt-bindings: pinctrl: intel: Add for new SoC
  pinctrl: Add pinmux & GPIO controller driver for a new SoC
  pinctrl: rza1: remove unnecessary static inline function
  pinctrl: meson: add pinctrl driver support for Meson-A1 SoC
  pinctrl: meson: add a new callback for SoCs fixup
  pinctrl: nomadik: db8500: Add mc0_a_2 pin group without direction control
  dt-bindings: pinctrl: Convert generic pin mux and config properties to schema
  pinctrl: cherryview: Missed type change to unsigned int
  pinctrl: intel: Missed type change to unsigned int
  pinctrl: use devm_platform_ioremap_resource() to simplify code
  pinctrl: just return if no valid maps
  dt-bindings: pinctrl: qcom-pmic-mpp: Add support for PM/PMI8950
  pinctrl: qcom: spmi-mpp: Add PM/PMI8950 compatible strings
  dt-bindings: pinctrl: qcom-pmic-gpio: Add support for PM/PMI8950
  ...
This commit is contained in:
Linus Torvalds
2019-11-27 10:00:33 -08:00
parent 3d9e3501a0 ae75b53e08
commit dc5fa46568
113 changed files with 6416 additions and 1664 deletions
Download Patch File Download Diff File Expand all files Collapse all files

243
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Pin Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
"#gpio-cells":
const: 3
description:
GPIO consumers must use three arguments, first the number of the
bank, then the pin number inside that bank, and finally the GPIO
flags.
"#interrupt-cells":
const: 3
description:
Interrupts consumers must use three arguments, first the number
of the bank, then the pin number inside that bank, and finally
the interrupts flags.
compatible:
enum:
- allwinner,sun4i-a10-pinctrl
- allwinner,sun5i-a10s-pinctrl
- allwinner,sun5i-a13-pinctrl
- allwinner,sun6i-a31-pinctrl
- allwinner,sun6i-a31-r-pinctrl
- allwinner,sun6i-a31s-pinctrl
- allwinner,sun7i-a20-pinctrl
- allwinner,sun8i-a23-pinctrl
- allwinner,sun8i-a23-r-pinctrl
- allwinner,sun8i-a33-pinctrl
- allwinner,sun8i-a83t-pinctrl
- allwinner,sun8i-a83t-r-pinctrl
- allwinner,sun8i-h3-pinctrl
- allwinner,sun8i-h3-r-pinctrl
- allwinner,sun8i-r40-pinctrl
- allwinner,sun8i-v3-pinctrl
- allwinner,sun8i-v3s-pinctrl
- allwinner,sun9i-a80-pinctrl
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,sun50i-h6-pinctrl
- allwinner,sun50i-h6-r-pinctrl
- allwinner,suniv-f1c100s-pinctrl
- nextthing,gr8-pinctrl
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 5
description:
One interrupt per external interrupt bank supported on the
controller, sorted by bank number ascending order.
clocks:
items:
- description: Bus Clock
- description: High Frequency Oscillator
- description: Low Frequency Oscillator
clock-names:
items:
- const: apb
- const: hosc
- const: losc
resets:
maxItems: 1
gpio-controller: true
interrupt-controller: true
gpio-line-names: true
input-debounce:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
maxItems: 5
description:
Debouncing periods in microseconds, one period per interrupt
bank found in the controller
patternProperties:
# It's pretty scary, but the basic idea is that:
# - One node name can start with either s- or r- for PRCM nodes,
# - Then, the name itself can be any repetition of <string>- (to
# accomodate with nodes like uart4-rts-cts-pins), where each
# string can be either starting with 'p' but in a string longer
# than 3, or something that doesn't start with 'p',
# - Then, the bank name is optional and will be between pa and pg,
# pl or pm. Some pins groups that have several options will have
# the pin numbers then,
# - Finally, the name will end with either -pin or pins.
"^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
type: object
properties:
pins: true
function: true
bias-disable: true
bias-pull-up: true
bias-pull-down: true
drive-strength:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 10, 20, 30, 40 ]
required:
- pins
- function
additionalProperties: false
"^vcc-p[a-hlm]-supply$":
description:
Power supplies for pin banks.
required:
- "#gpio-cells"
- "#interrupt-cells"
- compatible
- reg
- interrupts
- clocks
- clock-names
- gpio-controller
- interrupt-controller
allOf:
# FIXME: We should have the pin bank supplies here, but not a lot of
# boards are defining it at the moment so it would generate a lot of
# warnings.
- if:
properties:
compatible:
enum:
- allwinner,sun9i-a80-pinctrl
then:
properties:
interrupts:
minItems: 5
maxItems: 5
else:
if:
properties:
compatible:
enum:
- allwinner,sun6i-a31-pinctrl
- allwinner,sun6i-a31s-pinctrl
- allwinner,sun50i-h6-pinctrl
then:
properties:
interrupts:
minItems: 4
maxItems: 4
else:
if:
properties:
compatible:
enum:
- allwinner,sun8i-a23-pinctrl
- allwinner,sun8i-a83t-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,suniv-f1c100s-pinctrl
then:
properties:
interrupts:
minItems: 3
maxItems: 3
else:
if:
properties:
compatible:
enum:
- allwinner,sun6i-a31-r-pinctrl
- allwinner,sun8i-a33-pinctrl
- allwinner,sun8i-h3-pinctrl
- allwinner,sun8i-v3-pinctrl
- allwinner,sun8i-v3s-pinctrl
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-h6-r-pinctrl
then:
properties:
interrupts:
minItems: 2
maxItems: 2
else:
properties:
interrupts:
minItems: 1
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun5i-ccu.h>
pio: pinctrl@1c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <28>;
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
uart1_pe_pins: uart1-pe-pins {
pins = "PE10", "PE11";
function = "uart1";
};
uart1_pg_pins: uart1-pg-pins {
pins = "PG3", "PG4";
function = "uart1";
};
};

164
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
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@@ -1,164 +0,0 @@
* Allwinner A1X Pin Controller
The pins controlled by sunXi pin controller are organized in banks,
each bank has 32 pins. Each pin has 7 multiplexing functions, with
the first two functions being GPIO in and out. The configuration on
the pins includes drive strength and pull-up.
Required properties:
- compatible: Should be one of the following (depending on your SoC):
"allwinner,sun4i-a10-pinctrl"
"allwinner,sun5i-a10s-pinctrl"
"allwinner,sun5i-a13-pinctrl"
"allwinner,sun6i-a31-pinctrl"
"allwinner,sun6i-a31s-pinctrl"
"allwinner,sun6i-a31-r-pinctrl"
"allwinner,sun7i-a20-pinctrl"
"allwinner,sun8i-a23-pinctrl"
"allwinner,sun8i-a23-r-pinctrl"
"allwinner,sun8i-a33-pinctrl"
"allwinner,sun9i-a80-pinctrl"
"allwinner,sun9i-a80-r-pinctrl"
"allwinner,sun8i-a83t-pinctrl"
"allwinner,sun8i-a83t-r-pinctrl"
"allwinner,sun8i-h3-pinctrl"
"allwinner,sun8i-h3-r-pinctrl"
"allwinner,sun8i-r40-pinctrl"
"allwinner,sun8i-v3-pinctrl"
"allwinner,sun8i-v3s-pinctrl"
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
"allwinner,sun50i-h6-pinctrl"
"allwinner,sun50i-h6-r-pinctrl"
"allwinner,suniv-f1c100s-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
- clocks: phandle to the clocks feeding the pin controller:
- "apb": the gated APB parent clock
- "hosc": the high frequency oscillator in the system
- "losc": the low frequency oscillator in the system
Note: For backward compatibility reasons, the hosc and losc clocks are only
required if you need to use the optional input-debounce property. Any new
device tree should set them.
Each pin bank, depending on the SoC, can have an associated regulator:
- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs
- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs
- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs
- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs
- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs
- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs
- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs
- vcc-ph-supply: for the A31, A31s and A80 SoCs
- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs
- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs
Optional properties:
- input-debounce: Array of debouncing periods in microseconds. One period per
irq bank found in the controller. 0 if no setup required.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, drive strength and pullups. If one of these options is
not set, its actual value will be unspecified.
Allwinner A1X Pin Controller supports the generic pin multiplexing and
configuration bindings. For details on each properties, you can refer to
./pinctrl-bindings.txt.
Required sub-node properties:
- pins
- function
Optional sub-node properties:
- bias-disable
- bias-pull-up
- bias-pull-down
- drive-strength
*** Deprecated pin configuration and multiplexing binding
Required subnode-properties:
- allwinner,pins: List of strings containing the pin name.
- allwinner,function: Function to mux the pins listed above to.
Optional subnode-properties:
- allwinner,drive: Integer. Represents the current sent to the pin
0: 10 mA
1: 20 mA
2: 30 mA
3: 40 mA
- allwinner,pull: Integer.
0: No resistor
1: Pull-up resistor
2: Pull-down resistor
Examples:
pio: pinctrl@1c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
uart1_pins_a: uart1@0 {
allwinner,pins = "PE10", "PE11";
allwinner,function = "uart1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart1_pins_b: uart1@1 {
allwinner,pins = "PG3", "PG4";
allwinner,function = "uart1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
GPIO and interrupt controller
-----------------------------
This hardware also acts as a GPIO controller and an interrupt
controller.
Consumers that would want to refer to one or the other (or both)
should provide through the usual *-gpios and interrupts properties a
cell with 3 arguments, first the number of the bank, then the pin
inside that bank, and finally the flags for the GPIO/interrupts.
Example:
xio: gpio@38 {
compatible = "nxp,pcf8574a";
reg = <0x38>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&pio>;
interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
};

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Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
maintainers:
- Rahul Tanwar <rahul.tanwar@linux.intel.com>
description: |
Pinmux & GPIO controller controls pin multiplexing & configuration including
GPIO function selection & GPIO attributes configuration.
Please refer to [1] for details of the common pinctrl bindings used by the
client devices.
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
properties:
compatible:
const: intel,lgm-io
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
function:
$ref: /schemas/types.yaml#/definitions/string
description:
A string containing the name of the function to mux to the group.
groups:
$ref: /schemas/types.yaml#/definitions/string-array
description:
An array of strings identifying the list of groups.
pins:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
List of pins to select with this function.
pinmux:
description: The applicable mux group.
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32-array"
bias-pull-up:
type: boolean
bias-pull-down:
type: boolean
drive-strength:
description: |
Selects the drive strength for the specified pins in mA.
0: 2 mA
1: 4 mA
2: 8 mA
3: 12 mA
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 3]
slew-rate:
type: boolean
description: |
Sets slew rate for specified pins.
0: slow slew
1: fast slew
drive-open-drain:
type: boolean
output-enable:
type: boolean
required:
- function
- groups
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
# Pinmux controller node
- |
pinctrl: pinctrl@e2880000 {
compatible = "intel,lgm-pinctrl";
reg = <0xe2880000 0x100000>;
uart0-pins {
pins = <64>, /* UART_RX0 */
<65>; /* UART_TX0 */
function = "CONSOLE_UART0";
pinmux = <1>,
<1>;
groups = "CONSOLE_UART0";
};
};
...

1
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
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@@ -15,6 +15,7 @@ Required properties for the root node:
"amlogic,meson-axg-aobus-pinctrl"
"amlogic,meson-g12a-periphs-pinctrl"
"amlogic,meson-g12a-aobus-pinctrl"
"amlogic,meson-a1-periphs-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===

140
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic pin configuration node schema
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
Many data items that are represented in a pin configuration node are common
and generic. Pin control bindings should use the properties defined below
where they are applicable; not all of these properties are relevant or useful
for all hardware or binding structures. Each individual binding document
should state which of these generic properties, if any, are used, and the
structure of the DT nodes that contain these properties.
properties:
bias-disable:
type: boolean
description: disable any pin bias
bias-high-impedance:
type: boolean
description: high impedance mode ("third-state", "floating")
bias-bus-hold:
type: boolean
description: latch weakly
bias-pull-up:
oneOf:
- type: boolean
- $ref: /schemas/types.yaml#/definitions/uint32
description: pull up the pin. Takes as optional argument on hardware
supporting it the pull strength in Ohm.
bias-pull-down:
oneOf:
- type: boolean
- $ref: /schemas/types.yaml#/definitions/uint32
description: pull down the pin. Takes as optional argument on hardware
supporting it the pull strength in Ohm.
bias-pull-pin-default:
oneOf:
- type: boolean
- $ref: /schemas/types.yaml#/definitions/uint32
description: use pin-default pull state. Takes as optional argument on
hardware supporting it the pull strength in Ohm.
drive-push-pull:
type: boolean
description: drive actively high and low
drive-open-drain:
type: boolean
description: drive with open drain
drive-open-source:
type: boolean
description: drive with open source
drive-strength:
$ref: /schemas/types.yaml#/definitions/uint32
description: sink or source at most X mA
drive-strength-microamp:
description: sink or source at most X uA
input-enable:
type: boolean
description: enable input on pin (no effect on output, such as
enabling an input buffer)
input-disable:
type: boolean
description: disable input on pin (no effect on output, such as
disabling an input buffer)
input-schmitt-enable:
type: boolean
description: enable schmitt-trigger mode
input-schmitt-disable:
type: boolean
description: disable schmitt-trigger mode
input-debounce:
$ref: /schemas/types.yaml#/definitions/uint32
description: Takes the debounce time in usec as argument or 0 to disable
debouncing
power-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: select between different power supplies
low-power-enable:
type: boolean
description: enable low power mode
low-power-disable:
type: boolean
description: disable low power mode
output-disable:
type: boolean
description: disable output on a pin (such as disable an output buffer)
output-enable:
type: boolean
description: enable output on a pin without actively driving it
(such as enabling an output buffer)
output-low:
type: boolean
description: set the pin to output mode with low level
output-high:
type: boolean
description: set the pin to output mode with high level
sleep-hardware-state:
type: boolean
description: indicate this is sleep related state which will be
programmed into the registers for the sleep state.
slew-rate:
$ref: /schemas/types.yaml#/definitions/uint32
description: set the slew rate
skew-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
this affects the expected clock skew on input pins
and the delay before latching a value to an output
pin. Typically indicates how many double-inverters are
used to delay the signal.

192
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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@@ -141,196 +141,8 @@ controller device.
== Generic pin multiplexing node content ==
pin multiplexing nodes:
function - the mux function to select
groups - the list of groups to select with this function
(either this or "pins" must be specified)
pins - the list of pins to select with this function (either
this or "groups" must be specified)
Example:
state_0_node_a {
uart0 {
function = "uart0";
groups = "u0rxtx", "u0rtscts";
};
};
state_1_node_a {
spi0 {
function = "spi0";
groups = "spi0pins";
};
};
state_2_node_a {
function = "i2c0";
pins = "mfio29", "mfio30";
};
Optionally an alternative binding can be used if more suitable depending on the
pin controller hardware. For hardware where there is a large number of identical
pin controller instances, naming each pin and function can easily become
unmaintainable. This is especially the case if the same controller is used for
different pins and functions depending on the SoC revision and packaging.
For cases like this, the pin controller driver may use pinctrl-pin-array helper
binding with a hardware based index and a number of pin configuration values:
pincontroller {
... /* Standard DT properties for the device itself elided */
#pinctrl-cells = <2>;
state_0_node_a {
pinctrl-pin-array = <
0 A_DELAY_PS(0) G_DELAY_PS(120)
4 A_DELAY_PS(0) G_DELAY_PS(360)
...
>;
};
...
};
Above #pinctrl-cells specifies the number of value cells in addition to the
index of the registers. This is similar to the interrupts-extended binding with
one exception. There is no need to specify the phandle for each entry as that
is already known as the defined pins are always children of the pin controller
node. Further having the phandle pointing to another pin controller would not
currently work as the pinctrl framework uses named modes to group pins for each
pin control device.
The index for pinctrl-pin-array must relate to the hardware for the pinctrl
registers, and must not be a virtual index of pin instances. The reason for
this is to avoid mapping of the index in the dts files and the pin controller
driver as it can change.
For hardware where pin multiplexing configurations have to be specified for
each single pin the number of required sub-nodes containing "pin" and
"function" properties can quickly escalate and become hard to write and
maintain.
For cases like this, the pin controller driver may use the pinmux helper
property, where the pin identifier is provided with mux configuration settings
in a pinmux group. A pinmux group consists of the pin identifier and mux
settings represented as a single integer or an array of integers.
The pinmux property accepts an array of pinmux groups, each of them describing
a single pin multiplexing configuration.
pincontroller {
state_0_node_a {
pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
};
};
Each individual pin controller driver bindings documentation shall specify
how pin IDs and pin multiplexing configuration are defined and assembled
together in a pinmux group.
See pinmux-node.yaml
== Generic pin configuration node content ==
Many data items that are represented in a pin configuration node are common
and generic. Pin control bindings should use the properties defined below
where they are applicable; not all of these properties are relevant or useful
for all hardware or binding structures. Each individual binding document
should state which of these generic properties, if any, are used, and the
structure of the DT nodes that contain these properties.
Supported generic properties are:
pins - the list of pins that properties in the node
apply to (either this, "group" or "pinmux" has to be
specified)
group - the group to apply the properties to, if the driver
supports configuration of whole groups rather than
individual pins (either this, "pins" or "pinmux" has
to be specified)
pinmux - the list of numeric pin ids and their mux settings
that properties in the node apply to (either this,
"pins" or "groups" have to be specified)
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
bias-pull-up - pull up the pin
bias-pull-down - pull down the pin
bias-pull-pin-default - use pin-default pull state
drive-push-pull - drive actively high and low
drive-open-drain - drive with open drain
drive-open-source - drive with open source
drive-strength - sink or source at most X mA
drive-strength-microamp - sink or source at most X uA
input-enable - enable input on pin (no effect on output, such as
enabling an input buffer)
input-disable - disable input on pin (no effect on output, such as
disabling an input buffer)
input-schmitt-enable - enable schmitt-trigger mode
input-schmitt-disable - disable schmitt-trigger mode
input-debounce - debounce mode with debound time X
power-source - select between different power supplies
low-power-enable - enable low power mode
low-power-disable - disable low power mode
output-disable - disable output on a pin (such as disable an output
buffer)
output-enable - enable output on a pin without actively driving it
(such as enabling an output buffer)
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
sleep-hardware-state - indicate this is sleep related state which will be programmed
into the registers for the sleep state.
slew-rate - set the slew rate
skew-delay - this affects the expected clock skew on input pins
and the delay before latching a value to an output
pin. Typically indicates how many double-inverters are
used to delay the signal.
For example:
state_0_node_a {
cts_rxd {
pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
bias-pull-up;
};
};
state_1_node_a {
rts_txd {
pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
output-high;
};
};
state_2_node_a {
foo {
group = "foo-group";
bias-pull-up;
};
};
state_3_node_a {
mux {
pinmux = <GPIOx_PINm_MUXn>, <GPIOx_PINj_MUXk)>;
input-enable;
};
};
Some of the generic properties take arguments. For those that do, the
arguments are described below.
- pins takes a list of pin names or IDs as a required argument. The specific
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- pinmux takes a list of pin IDs and mux settings as required argument. The
specific bindings for the hardware defines:
- How pin IDs and mux settings are defined and assembled together in a single
integer or an array of integers.
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
- drive-strength takes as argument the target strength in mA.
- drive-strength-microamp takes as argument the target strength in uA.
- input-debounce takes the debounce time in usec as argument
or 0 to disable debouncing
More in-depth documentation on these parameters can be found in
<include/linux/pinctrl/pinconf-generic.h>
See pincfg-node.yaml

132
Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml Normal file
View File

@@ -0,0 +1,132 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic pin multiplexing node schema
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
The contents of the pin configuration child nodes are defined by the binding
for the individual pin controller device. The pin configuration nodes need not
be direct children of the pin controller device; they may be grandchildren,
for example. Whether this is legal, and whether there is any interaction
between the child and intermediate parent nodes, is again defined entirely by
the binding for the individual pin controller device.
While not required to be used, there are 3 generic forms of pin muxing nodes
which pin controller devices can use.
pin multiplexing nodes:
Example:
state_0_node_a {
uart0 {
function = "uart0";
groups = "u0rxtx", "u0rtscts";
};
};
state_1_node_a {
spi0 {
function = "spi0";
groups = "spi0pins";
};
};
state_2_node_a {
function = "i2c0";
pins = "mfio29", "mfio30";
};
Optionally an alternative binding can be used if more suitable depending on the
pin controller hardware. For hardware where there is a large number of identical
pin controller instances, naming each pin and function can easily become
unmaintainable. This is especially the case if the same controller is used for
different pins and functions depending on the SoC revision and packaging.
For cases like this, the pin controller driver may use pinctrl-pin-array helper
binding with a hardware based index and a number of pin configuration values:
pincontroller {
... /* Standard DT properties for the device itself elided */
#pinctrl-cells = <2>;
state_0_node_a {
pinctrl-pin-array = <
0 A_DELAY_PS(0) G_DELAY_PS(120)
4 A_DELAY_PS(0) G_DELAY_PS(360)
...
>;
};
...
};
Above #pinctrl-cells specifies the number of value cells in addition to the
index of the registers. This is similar to the interrupts-extended binding with
one exception. There is no need to specify the phandle for each entry as that
is already known as the defined pins are always children of the pin controller
node. Further having the phandle pointing to another pin controller would not
currently work as the pinctrl framework uses named modes to group pins for each
pin control device.
The index for pinctrl-pin-array must relate to the hardware for the pinctrl
registers, and must not be a virtual index of pin instances. The reason for
this is to avoid mapping of the index in the dts files and the pin controller
driver as it can change.
For hardware where pin multiplexing configurations have to be specified for
each single pin the number of required sub-nodes containing "pin" and
"function" properties can quickly escalate and become hard to write and
maintain.
For cases like this, the pin controller driver may use the pinmux helper
property, where the pin identifier is provided with mux configuration settings
in a pinmux group. A pinmux group consists of the pin identifier and mux
settings represented as a single integer or an array of integers.
The pinmux property accepts an array of pinmux groups, each of them describing
a single pin multiplexing configuration.
pincontroller {
state_0_node_a {
pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
};
};
Each individual pin controller driver bindings documentation shall specify
how pin IDs and pin multiplexing configuration are defined and assembled
together in a pinmux group.
properties:
function:
$ref: /schemas/types.yaml#/definitions/string
description: The mux function to select
pins:
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- $ref: /schemas/types.yaml#/definitions/string-array
description:
The list of pin identifiers that properties in the node apply to. The
specific binding for the hardware defines whether the entries are integers
or strings, and their meaning.
group:
$ref: /schemas/types.yaml#/definitions/string-array
description:
the group to apply the properties to, if the driver supports
configuration of whole groups rather than individual pins (either
this, "pins" or "pinmux" has to be specified)
pinmux:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
description:
The list of numeric pin ids and their mux settings that properties in the
node apply to (either this, "pins" or "groups" have to be specified)
pinctrl-pin-array:
$ref: /schemas/types.yaml#/definitions/uint32-array

183
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.txt Normal file
View File

@@ -0,0 +1,183 @@
Qualcomm MSM8976 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8956 and MSM8976 platforms.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8976-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio145
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data,
sdc2_clk, sdc2_cmd, sdc2_data,
sdc3_clk, sdc3_cmd, sdc3_data
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
uim1_present, uim2_data, uim2_clk, uim2_reset,
uim2_present, ts_xvdd, mipi_dsi0, us_euro, ts_resout,
ts_sample, sec_mi2s_mclk_b, pri_mi2s, codec_reset,
cdc_pdm0, us_emitter, pri_mi2s_mclk_b, pri_mi2s_mclk_c,
lpass_slimbus, lpass_slimbus0, lpass_slimbus1, codec_int1,
codec_int2, wcss_bt, sdc3, wcss_wlan2, wcss_wlan1,
wcss_wlan0, wcss_wlan, wcss_fm, key_volp, key_snapshot,
key_focus, key_home, pwr_down, dmic0_clk, hdmi_int,
dmic0_data, wsa_vi, wsa_en, blsp_spi8, wsa_irq, blsp_i2c8,
pa_indicator, modem_tsync, ssbi_wtr1, gsm1_tx, gsm0_tx,
sdcard_det, sec_mi2s, ss_switch,
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,msm8976-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 145>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1_uart2_active: blsp1_uart2_active {
mux {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "blsp_uart2";
};
config {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
};
};

8
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
View File

@@ -15,14 +15,18 @@ PMIC's from Qualcomm.
"qcom,pm8917-gpio"
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pm8950-gpio"
"qcom,pm8994-gpio"
"qcom,pm8998-gpio"
"qcom,pma8084-gpio"
"qcom,pmi8950-gpio"
"qcom,pmi8994-gpio"
"qcom,pmi8998-gpio"
"qcom,pms405-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
"qcom,pm6150-gpio"
"qcom,pm6150l-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@@ -91,15 +95,19 @@ to specify in a pin configuration subnode:
gpio1-gpio38 for pm8917
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio8 for pm8950 (hole on gpio3)
gpio1-gpio22 for pm8994
gpio1-gpio26 for pm8998
gpio1-gpio22 for pma8084
gpio1-gpio2 for pmi8950
gpio1-gpio10 for pmi8994
gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10)
gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, gpio7
and gpio8)
gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
gpio1-gpio12 for pm8150l (hole on gpio7)
gpio1-gpio10 for pm6150
gpio1-gpio12 for pm6150l
- function:
Usage: required

4
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
View File

@@ -16,6 +16,8 @@ of PMIC's from Qualcomm.
"qcom,pm8917-mpp",
"qcom,pm8921-mpp",
"qcom,pm8941-mpp",
"qcom,pm8950-mpp",
"qcom,pmi8950-mpp",
"qcom,pm8994-mpp",
"qcom,pma8084-mpp",
@@ -80,6 +82,8 @@ to specify in a pin configuration subnode:
mpp1-mpp4 for pm8841
mpp1-mpp4 for pm8916
mpp1-mpp8 for pm8941
mpp1-mpp4 for pm8950
mpp1-mpp4 for pmi8950
mpp1-mpp4 for pma8084
- function:

4
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
View File

@@ -18,6 +18,7 @@ Required Properties:
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
@@ -27,7 +28,8 @@ Required Properties:
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller.
- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.

1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@@ -29,6 +29,7 @@ Required properties for iomux controller:
"rockchip,rk3188-pinctrl": for Rockchip RK3188
"rockchip,rk3228-pinctrl": for Rockchip RK3228
"rockchip,rk3288-pinctrl": for Rockchip RK3288
"rockchip,rk3308-pinctrl": for Rockchip RK3308
"rockchip,rk3328-pinctrl": for Rockchip RK3328
"rockchip,rk3368-pinctrl": for Rockchip RK3368
"rockchip,rk3399-pinctrl": for Rockchip RK3399

2
MAINTAINERS
View File

@@ -12975,7 +12975,7 @@ F: Documentation/devicetree/bindings/pinctrl/fsl,*
PIN CONTROLLER - INTEL
M: Mika Westerberg <mika.westerberg@linux.intel.com>
M: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
M: Andy Shevchenko <andy@kernel.org>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
S: Maintained
F: drivers/pinctrl/intel/

2
arch/sh/include/cpu-sh4/cpu/sh7734.h
View File

@@ -134,7 +134,7 @@ enum {
GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
GPIO_FN_RD_WR, GPIO_FN_TCLK0,
GPIO_FN_RD_WR, GPIO_FN_TCLK0, GPIO_FN_CAN_CLK_B, GPIO_FN_ET0_ETXD4,
GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
GPIO_FN_ET0_ETXD3_A,
GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,

36
drivers/pinctrl/Kconfig
View File

@@ -32,15 +32,15 @@ config DEBUG_PINCTRL
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
config PINCTRL_ARTPEC6
bool "Axis ARTPEC-6 pin controller driver"
depends on MACH_ARTPEC6
select PINMUX
select GENERIC_PINCONF
help
This is the driver for the Axis ARTPEC-6 pin controller. This driver
supports pin function multiplexing as well as pin bias and drive
strength configuration. Device tree integration instructions can be
found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
bool "Axis ARTPEC-6 pin controller driver"
depends on MACH_ARTPEC6
select PINMUX
select GENERIC_PINCONF
help
This is the driver for the Axis ARTPEC-6 pin controller. This driver
supports pin function multiplexing as well as pin bias and drive
strength configuration. Device tree integration instructions can be
found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
config PINCTRL_AS3722
tristate "Pinctrl and GPIO driver for ams AS3722 PMIC"
@@ -420,4 +420,22 @@ config PINCTRL_TB10X
depends on OF && ARC_PLAT_TB10X
select GPIOLIB
config PINCTRL_EQUILIBRIUM
tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
select PINMUX
select PINCONF
select GPIOLIB
select GPIO_GENERIC
select GPIOLIB_IRQCHIP
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
help
Equilibrium pinctrl driver is a pinctrl & GPIO driver for Intel Lightning
Mountain network processor SoC that supports both the linux GPIO and pin
control frameworks. It provides interfaces to setup pinmux, assign desired
pin functions, configure GPIO attributes for LGM SoC pins. Pinmux and
pinconf settings are retrieved from device tree.
endif

1
drivers/pinctrl/Makefile
View File

@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
obj-y += actions/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/

4
drivers/pinctrl/actions/pinctrl-owl.c
View File

@@ -915,7 +915,6 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl)
int owl_pinctrl_probe(struct platform_device *pdev,
struct owl_pinctrl_soc_data *soc_data)
{
struct resource *res;
struct owl_pinctrl *pctrl;
int ret, i;
@@ -923,8 +922,7 @@ int owl_pinctrl_probe(struct platform_device *pdev,
if (!pctrl)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pctrl->base = devm_ioremap_resource(&pdev->dev, res);
pctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->base))
return PTR_ERR(pctrl->base);

4
drivers/pinctrl/bcm/pinctrl-bcm281xx.c
View File

@@ -1400,12 +1400,10 @@ static struct pinctrl_desc bcm281xx_pinctrl_desc = {
static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
{
struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
struct resource *res;
struct pinctrl_dev *pctl;
/* So far We can assume there is only 1 bank of registers */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pdata->reg_base)) {
dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
return -ENODEV;

7
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
View File

@@ -940,7 +940,6 @@ static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
static int cygnus_pinmux_probe(struct platform_device *pdev)
{
struct cygnus_pinctrl *pinctrl;
struct resource *res;
int i, ret;
struct pinctrl_pin_desc *pins;
unsigned num_pins = ARRAY_SIZE(cygnus_pins);
@@ -953,15 +952,13 @@ static int cygnus_pinmux_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pinctrl);
spin_lock_init(&pinctrl->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res);
pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pinctrl->base0)) {
dev_err(&pdev->dev, "unable to map I/O space\n");
return PTR_ERR(pinctrl->base0);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
pinctrl->base1 = devm_ioremap_resource(&pdev->dev, res);
pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(pinctrl->base1)) {
dev_err(&pdev->dev, "unable to map I/O space\n");
return PTR_ERR(pinctrl->base1);

5
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
View File

@@ -795,8 +795,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
chip->dev = dev;
platform_set_drvdata(pdev, chip);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
chip->base = devm_ioremap_resource(dev, res);
chip->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(chip->base)) {
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->base);
@@ -850,7 +849,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
struct gpio_irq_chip *girq;
irqc = &chip->irqchip;
irqc->name = "bcm-iproc-gpio";
irqc->name = dev_name(dev);
irqc->irq_ack = iproc_gpio_irq_ack;
irqc->irq_mask = iproc_gpio_irq_mask;
irqc->irq_unmask = iproc_gpio_irq_unmask;

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