mirror of
https://github.com/ukui/kernel.git
synced 2026-03-09 10:07:04 -07:00
Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon: - Errata workarounds for Qualcomm's Falkor CPU - Qualcomm L2 Cache PMU driver - Qualcomm SMCCC firmware quirk - Support for DEBUG_VIRTUAL - CPU feature detection for userspace via MRS emulation - Preliminary work for the Statistical Profiling Extension - Misc cleanups and non-critical fixes * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (74 commits) arm64/kprobes: consistently handle MRS/MSR with XZR arm64: cpufeature: correctly handle MRS to XZR arm64: traps: correctly handle MRS/MSR with XZR arm64: ptrace: add XZR-safe regs accessors arm64: include asm/assembler.h in entry-ftrace.S arm64: fix warning about swapper_pg_dir overflow arm64: Work around Falkor erratum 1003 arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 arm64: arch_timer: document Hisilicon erratum 161010101 arm64: use is_vmalloc_addr arm64: use linux/sizes.h for constants arm64: uaccess: consistently check object sizes perf: add qcom l2 cache perf events driver arm64: remove wrong CONFIG_PROC_SYSCTL ifdef ARM: smccc: Update HVC comment to describe new quirk parameter arm64: do not trace atomic operations ACPI/IORT: Fix the error return code in iort_add_smmu_platform_device() ACPI/IORT: Fix iort_node_get_id() mapping entries indexing arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA perf: xgene: Include module.h ...
This commit is contained in:
Linus Torvalds
240
Documentation/arm64/cpu-feature-registers.txt
Normal file
240
Documentation/arm64/cpu-feature-registers.txt
Normal file
@@ -0,0 +1,240 @@
|
||||
ARM64 CPU Feature Registers
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===========================
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Author: Suzuki K Poulose <suzuki.poulose@arm.com>
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This file describes the ABI for exporting the AArch64 CPU ID/feature
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registers to userspace. The availability of this ABI is advertised
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via the HWCAP_CPUID in HWCAPs.
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1. Motivation
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||||
---------------
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The ARM architecture defines a set of feature registers, which describe
|
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the capabilities of the CPU/system. Access to these system registers is
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restricted from EL0 and there is no reliable way for an application to
|
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extract this information to make better decisions at runtime. There is
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limited information available to the application via HWCAPs, however
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there are some issues with their usage.
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a) Any change to the HWCAPs requires an update to userspace (e.g libc)
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to detect the new changes, which can take a long time to appear in
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distributions. Exposing the registers allows applications to get the
|
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information without requiring updates to the toolchains.
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b) Access to HWCAPs is sometimes limited (e.g prior to libc, or
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when ld is initialised at startup time).
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c) HWCAPs cannot represent non-boolean information effectively. The
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architecture defines a canonical format for representing features
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in the ID registers; this is well defined and is capable of
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representing all valid architecture variations.
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2. Requirements
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-----------------
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a) Safety :
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Applications should be able to use the information provided by the
|
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infrastructure to run safely across the system. This has greater
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implications on a system with heterogeneous CPUs.
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The infrastructure exports a value that is safe across all the
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available CPU on the system.
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e.g, If at least one CPU doesn't implement CRC32 instructions, while
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others do, we should report that the CRC32 is not implemented.
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Otherwise an application could crash when scheduled on the CPU
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which doesn't support CRC32.
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b) Security :
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Applications should only be able to receive information that is
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relevant to the normal operation in userspace. Hence, some of the
|
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fields are masked out(i.e, made invisible) and their values are set to
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indicate the feature is 'not supported'. See Section 4 for the list
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of visible features. Also, the kernel may manipulate the fields
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based on what it supports. e.g, If FP is not supported by the
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kernel, the values could indicate that the FP is not available
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(even when the CPU provides it).
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c) Implementation Defined Features
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The infrastructure doesn't expose any register which is
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IMPLEMENTATION DEFINED as per ARMv8-A Architecture.
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d) CPU Identification :
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MIDR_EL1 is exposed to help identify the processor. On a
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heterogeneous system, this could be racy (just like getcpu()). The
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process could be migrated to another CPU by the time it uses the
|
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register value, unless the CPU affinity is set. Hence, there is no
|
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guarantee that the value reflects the processor that it is
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currently executing on. The REVIDR is not exposed due to this
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constraint, as REVIDR makes sense only in conjunction with the
|
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MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs
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at:
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/sys/devices/system/cpu/cpu$ID/regs/identification/
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\- midr
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\- revidr
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3. Implementation
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--------------------
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The infrastructure is built on the emulation of the 'MRS' instruction.
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Accessing a restricted system register from an application generates an
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exception and ends up in SIGILL being delivered to the process.
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The infrastructure hooks into the exception handler and emulates the
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operation if the source belongs to the supported system register space.
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The infrastructure emulates only the following system register space:
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Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
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|
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(See Table C5-6 'System instruction encodings for non-Debug System
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register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
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registers).
|
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|
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The following rules are applied to the value returned by the
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infrastructure:
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a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0.
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b) The value of a reserved field is populated with the reserved
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value as defined by the architecture.
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c) The value of a 'visible' field holds the system wide safe value
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for the particular feature (except for MIDR_EL1, see section 4).
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d) All other fields (i.e, invisible fields) are set to indicate
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the feature is missing (as defined by the architecture).
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4. List of registers with visible features
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-------------------------------------------
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1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
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x--------------------------------------------------x
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| Name | bits | visible |
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|--------------------------------------------------|
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| RES0 | [63-32] | n |
|
||||
|--------------------------------------------------|
|
||||
| RDM | [31-28] | y |
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|--------------------------------------------------|
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| ATOMICS | [23-20] | y |
|
||||
|--------------------------------------------------|
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||||
| CRC32 | [19-16] | y |
|
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|--------------------------------------------------|
|
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| SHA2 | [15-12] | y |
|
||||
|--------------------------------------------------|
|
||||
| SHA1 | [11-8] | y |
|
||||
|--------------------------------------------------|
|
||||
| AES | [7-4] | y |
|
||||
|--------------------------------------------------|
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||||
| RES0 | [3-0] | n |
|
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x--------------------------------------------------x
|
||||
|
||||
|
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2) ID_AA64PFR0_EL1 - Processor Feature Register 0
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x--------------------------------------------------x
|
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| Name | bits | visible |
|
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|--------------------------------------------------|
|
||||
| RES0 | [63-28] | n |
|
||||
|--------------------------------------------------|
|
||||
| GIC | [27-24] | n |
|
||||
|--------------------------------------------------|
|
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| AdvSIMD | [23-20] | y |
|
||||
|--------------------------------------------------|
|
||||
| FP | [19-16] | y |
|
||||
|--------------------------------------------------|
|
||||
| EL3 | [15-12] | n |
|
||||
|--------------------------------------------------|
|
||||
| EL2 | [11-8] | n |
|
||||
|--------------------------------------------------|
|
||||
| EL1 | [7-4] | n |
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||||
|--------------------------------------------------|
|
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| EL0 | [3-0] | n |
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x--------------------------------------------------x
|
||||
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|
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3) MIDR_EL1 - Main ID Register
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x--------------------------------------------------x
|
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| Name | bits | visible |
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|--------------------------------------------------|
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| Implementer | [31-24] | y |
|
||||
|--------------------------------------------------|
|
||||
| Variant | [23-20] | y |
|
||||
|--------------------------------------------------|
|
||||
| Architecture | [19-16] | y |
|
||||
|--------------------------------------------------|
|
||||
| PartNum | [15-4] | y |
|
||||
|--------------------------------------------------|
|
||||
| Revision | [3-0] | y |
|
||||
x--------------------------------------------------x
|
||||
|
||||
NOTE: The 'visible' fields of MIDR_EL1 will contain the value
|
||||
as available on the CPU where it is fetched and is not a system
|
||||
wide safe value.
|
||||
|
||||
Appendix I: Example
|
||||
---------------------------
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||||
|
||||
/*
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||||
* Sample program to demonstrate the MRS emulation ABI.
|
||||
*
|
||||
* Copyright (C) 2015-2016, ARM Ltd
|
||||
*
|
||||
* Author: Suzuki K Poulose <suzuki.poulose@arm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/hwcap.h>
|
||||
#include <stdio.h>
|
||||
#include <sys/auxv.h>
|
||||
|
||||
#define get_cpu_ftr(id) ({ \
|
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unsigned long __val; \
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asm("mrs %0, "#id : "=r" (__val)); \
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||||
printf("%-20s: 0x%016lx\n", #id, __val); \
|
||||
})
|
||||
|
||||
int main(void)
|
||||
{
|
||||
|
||||
if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
|
||||
fputs("CPUID registers unavailable\n", stderr);
|
||||
return 1;
|
||||
}
|
||||
|
||||
get_cpu_ftr(ID_AA64ISAR0_EL1);
|
||||
get_cpu_ftr(ID_AA64ISAR1_EL1);
|
||||
get_cpu_ftr(ID_AA64MMFR0_EL1);
|
||||
get_cpu_ftr(ID_AA64MMFR1_EL1);
|
||||
get_cpu_ftr(ID_AA64PFR0_EL1);
|
||||
get_cpu_ftr(ID_AA64PFR1_EL1);
|
||||
get_cpu_ftr(ID_AA64DFR0_EL1);
|
||||
get_cpu_ftr(ID_AA64DFR1_EL1);
|
||||
|
||||
get_cpu_ftr(MIDR_EL1);
|
||||
get_cpu_ftr(MPIDR_EL1);
|
||||
get_cpu_ftr(REVIDR_EL1);
|
||||
|
||||
#if 0
|
||||
/* Unexposed register access causes SIGILL */
|
||||
get_cpu_ftr(ID_MMFR0_EL1);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -42,24 +42,29 @@ file acts as a registry of software workarounds in the Linux Kernel and
|
||||
will be updated when new workarounds are committed and backported to
|
||||
stable kernels.
|
||||
|
||||
| Implementor | Component | Erratum ID | Kconfig |
|
||||
+----------------+-----------------+-----------------+-------------------------+
|
||||
| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
|
||||
| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
|
||||
| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
|
||||
| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
|
||||
| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
|
||||
| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
|
||||
| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
|
||||
| ARM | Cortex-A57 | #852523 | N/A |
|
||||
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
|
||||
| ARM | Cortex-A72 | #853709 | N/A |
|
||||
| ARM | MMU-500 | #841119,#826419 | N/A |
|
||||
| | | | |
|
||||
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
|
||||
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
|
||||
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
|
||||
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
|
||||
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
|
||||
| | | | |
|
||||
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
|
||||
| Implementor | Component | Erratum ID | Kconfig |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
|
||||
| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
|
||||
| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
|
||||
| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
|
||||
| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
|
||||
| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
|
||||
| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
|
||||
| ARM | Cortex-A57 | #852523 | N/A |
|
||||
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
|
||||
| ARM | Cortex-A72 | #853709 | N/A |
|
||||
| ARM | MMU-500 | #841119,#826419 | N/A |
|
||||
| | | | |
|
||||
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
|
||||
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
|
||||
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
|
||||
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
|
||||
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
|
||||
| | | | |
|
||||
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
|
||||
| | | | |
|
||||
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
|
||||
| | | | |
|
||||
| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
|
||||
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
|
||||
|
||||
38
Documentation/perf/qcom_l2_pmu.txt
Normal file
38
Documentation/perf/qcom_l2_pmu.txt
Normal file
@@ -0,0 +1,38 @@
|
||||
Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
|
||||
=====================================================================
|
||||
|
||||
This driver supports the L2 cache clusters found in Qualcomm Technologies
|
||||
Centriq SoCs. There are multiple physical L2 cache clusters, each with their
|
||||
own PMU. Each cluster has one or more CPUs associated with it.
|
||||
|
||||
There is one logical L2 PMU exposed, which aggregates the results from
|
||||
the physical PMUs.
|
||||
|
||||
The driver provides a description of its available events and configuration
|
||||
options in sysfs, see /sys/devices/l2cache_0.
|
||||
|
||||
The "format" directory describes the format of the events.
|
||||
|
||||
Events can be envisioned as a 2-dimensional array. Each column represents
|
||||
a group of events. There are 8 groups. Only one entry from each
|
||||
group can be in use at a time. If multiple events from the same group
|
||||
are specified, the conflicting events cannot be counted at the same time.
|
||||
|
||||
Events are specified as 0xCCG, where CC is 2 hex digits specifying
|
||||
the code (array row) and G specifies the group (column) 0-7.
|
||||
|
||||
In addition there is a cycle counter event specified by the value 0xFE
|
||||
which is outside the above scheme.
|
||||
|
||||
The driver provides a "cpumask" sysfs attribute which contains a mask
|
||||
consisting of one CPU per cluster which will be used to handle all the PMU
|
||||
events on that cluster.
|
||||
|
||||
Examples for use with perf:
|
||||
|
||||
perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
|
||||
|
||||
perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
|
||||
|
||||
The driver does not support sampling, therefore "perf record" will
|
||||
not work. Per-task perf sessions are not supported.
|
||||
@@ -178,6 +178,6 @@ EXPORT_SYMBOL(__pv_offset);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_SMCCC
|
||||
EXPORT_SYMBOL(arm_smccc_smc);
|
||||
EXPORT_SYMBOL(arm_smccc_hvc);
|
||||
EXPORT_SYMBOL(__arm_smccc_smc);
|
||||
EXPORT_SYMBOL(__arm_smccc_hvc);
|
||||
#endif
|
||||
|
||||
@@ -581,9 +581,5 @@ static struct platform_driver armv6_pmu_driver = {
|
||||
.probe = armv6_pmu_device_probe,
|
||||
};
|
||||
|
||||
static int __init register_armv6_pmu_driver(void)
|
||||
{
|
||||
return platform_driver_register(&armv6_pmu_driver);
|
||||
}
|
||||
device_initcall(register_armv6_pmu_driver);
|
||||
builtin_platform_driver(armv6_pmu_driver);
|
||||
#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */
|
||||
|
||||
@@ -2034,9 +2034,5 @@ static struct platform_driver armv7_pmu_driver = {
|
||||
.probe = armv7_pmu_device_probe,
|
||||
};
|
||||
|
||||
static int __init register_armv7_pmu_driver(void)
|
||||
{
|
||||
return platform_driver_register(&armv7_pmu_driver);
|
||||
}
|
||||
device_initcall(register_armv7_pmu_driver);
|
||||
builtin_platform_driver(armv7_pmu_driver);
|
||||
#endif /* CONFIG_CPU_V7 */
|
||||
|
||||
@@ -767,9 +767,5 @@ static struct platform_driver xscale_pmu_driver = {
|
||||
.probe = xscale_pmu_device_probe,
|
||||
};
|
||||
|
||||
static int __init register_xscale_pmu_driver(void)
|
||||
{
|
||||
return platform_driver_register(&xscale_pmu_driver);
|
||||
}
|
||||
device_initcall(register_xscale_pmu_driver);
|
||||
builtin_platform_driver(xscale_pmu_driver);
|
||||
#endif /* CONFIG_CPU_XSCALE */
|
||||
|
||||
@@ -46,17 +46,19 @@ UNWIND( .fnend)
|
||||
/*
|
||||
* void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
|
||||
* unsigned long a3, unsigned long a4, unsigned long a5,
|
||||
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res)
|
||||
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
|
||||
* struct arm_smccc_quirk *quirk)
|
||||
*/
|
||||
ENTRY(arm_smccc_smc)
|
||||
ENTRY(__arm_smccc_smc)
|
||||
SMCCC SMCCC_SMC
|
||||
ENDPROC(arm_smccc_smc)
|
||||
ENDPROC(__arm_smccc_smc)
|
||||
|
||||
/*
|
||||
* void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
|
||||
* unsigned long a3, unsigned long a4, unsigned long a5,
|
||||
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res)
|
||||
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
|
||||
* struct arm_smccc_quirk *quirk)
|
||||
*/
|
||||
ENTRY(arm_smccc_hvc)
|
||||
ENTRY(__arm_smccc_hvc)
|
||||
SMCCC SMCCC_HVC
|
||||
ENDPROC(arm_smccc_hvc)
|
||||
ENDPROC(__arm_smccc_hvc)
|
||||
|
||||
@@ -6,6 +6,7 @@ config ARM64
|
||||
select ACPI_MCFG if ACPI
|
||||
select ACPI_SPCR_TABLE if ACPI
|
||||
select ARCH_CLOCKSOURCE_DATA
|
||||
select ARCH_HAS_DEBUG_VIRTUAL
|
||||
select ARCH_HAS_DEVMEM_IS_ALLOWED
|
||||
select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
|
||||
select ARCH_HAS_ELF_RANDOMIZE
|
||||
@@ -479,6 +480,34 @@ config CAVIUM_ERRATUM_27456
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
config QCOM_FALKOR_ERRATUM_1003
|
||||
bool "Falkor E1003: Incorrect translation due to ASID change"
|
||||
default y
|
||||
select ARM64_PAN if ARM64_SW_TTBR0_PAN
|
||||
help
|
||||
On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
|
||||
and BADDR are changed together in TTBRx_EL1. The workaround for this
|
||||
issue is to use a reserved ASID in cpu_do_switch_mm() before
|
||||
switching to the new ASID. Saying Y here selects ARM64_PAN if
|
||||
ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
|
||||
maintaining the E1003 workaround in the software PAN emulation code
|
||||
would be an unnecessary complication. The affected Falkor v1 CPU
|
||||
implements ARMv8.1 hardware PAN support and using hardware PAN
|
||||
support versus software PAN emulation is mutually exclusive at
|
||||
runtime.
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
config QCOM_FALKOR_ERRATUM_1009
|
||||
bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
|
||||
default y
|
||||
help
|
||||
On Falkor v1, the CPU may prematurely complete a DSB following a
|
||||
TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
|
||||
one more time to fix the issue.
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
@@ -614,6 +643,10 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
|
||||
def_bool y
|
||||
depends on NUMA
|
||||
|
||||
config HOLES_IN_ZONE
|
||||
def_bool y
|
||||
depends on NUMA
|
||||
|
||||
source kernel/Kconfig.preempt
|
||||
source kernel/Kconfig.hz
|
||||
|
||||
@@ -1010,7 +1043,7 @@ source "fs/Kconfig.binfmt"
|
||||
config COMPAT
|
||||
bool "Kernel support for 32-bit EL0"
|
||||
depends on ARM64_4K_PAGES || EXPERT
|
||||
select COMPAT_BINFMT_ELF
|
||||
select COMPAT_BINFMT_ELF if BINFMT_ELF
|
||||
select HAVE_UID16
|
||||
select OLD_SIGSUSPEND3
|
||||
select COMPAT_OLD_SIGACTION
|
||||
|
||||
@@ -84,6 +84,14 @@ config DEBUG_ALIGN_RODATA
|
||||
|
||||
If in doubt, say N.
|
||||
|
||||
config DEBUG_EFI
|
||||
depends on EFI && DEBUG_INFO
|
||||
bool "UEFI debugging"
|
||||
help
|
||||
Enable this option to include EFI specific debugging features into
|
||||
the kernel that are only useful when using a debug build of the
|
||||
UEFI firmware
|
||||
|
||||
source "drivers/hwtracing/coresight/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/cpufeature.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/ptrace.h>
|
||||
@@ -440,6 +441,28 @@ alternative_endif
|
||||
mrs \rd, sp_el0
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Errata workaround prior to TTBR0_EL1 update
|
||||
*
|
||||
* val: TTBR value with new BADDR, preserved
|
||||
* tmp0: temporary register, clobbered
|
||||
* tmp1: other temporary register, clobbered
|
||||
*/
|
||||
.macro pre_ttbr0_update_workaround, val, tmp0, tmp1
|
||||
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
|
||||
alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
|
||||
mrs \tmp0, ttbr0_el1
|
||||
mov \tmp1, #FALKOR_RESERVED_ASID
|
||||
bfi \tmp0, \tmp1, #48, #16 // reserved ASID + old BADDR
|
||||
msr ttbr0_el1, \tmp0
|
||||
isb
|
||||
bfi \tmp0, \val, #0, #48 // reserved ASID + new BADDR
|
||||
msr ttbr0_el1, \tmp0
|
||||
isb
|
||||
alternative_else_nop_endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Errata workaround post TTBR0_EL1 update.
|
||||
*/
|
||||
|
||||
@@ -35,7 +35,9 @@
|
||||
#define ARM64_HYP_OFFSET_LOW 14
|
||||
#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
|
||||
#define ARM64_HAS_NO_FPSIMD 16
|
||||
#define ARM64_WORKAROUND_REPEAT_TLBI 17
|
||||
#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
|
||||
|
||||
#define ARM64_NCAPS 17
|
||||
#define ARM64_NCAPS 19
|
||||
|
||||
#endif /* __ASM_CPUCAPS_H */
|
||||
|
||||
@@ -29,7 +29,20 @@
|
||||
#include <linux/jump_label.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
/* CPU feature register tracking */
|
||||
/*
|
||||
* CPU feature register tracking
|
||||
*
|
||||
* The safe value of a CPUID feature field is dependent on the implications
|
||||
* of the values assigned to it by the architecture. Based on the relationship
|
||||
* between the values, the features are classified into 3 types - LOWER_SAFE,
|
||||
* HIGHER_SAFE and EXACT.
|
||||
*
|
||||
* The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
|
||||
* for HIGHER_SAFE. It is expected that all CPUs have the same value for
|
||||
* a field when EXACT is specified, failing which, the safe value specified
|
||||
* in the table is chosen.
|
||||
*/
|
||||
|
||||
enum ftr_type {
|
||||
FTR_EXACT, /* Use a predefined safe value */
|
||||
FTR_LOWER_SAFE, /* Smaller value is safe */
|
||||
@@ -42,8 +55,12 @@ enum ftr_type {
|
||||
#define FTR_SIGNED true /* Value should be treated as signed */
|
||||
#define FTR_UNSIGNED false /* Value should be treated as unsigned */
|
||||
|
||||
#define FTR_VISIBLE true /* Feature visible to the user space */
|
||||
#define FTR_HIDDEN false /* Feature is hidden from the user */
|
||||
|
||||
struct arm64_ftr_bits {
|
||||
bool sign; /* Value is signed ? */
|
||||
bool visible;
|
||||
bool strict; /* CPU Sanity check: strict matching required ? */
|
||||
enum ftr_type type;
|
||||
u8 shift;
|
||||
@@ -59,7 +76,9 @@ struct arm64_ftr_bits {
|
||||
struct arm64_ftr_reg {
|
||||
const char *name;
|
||||
u64 strict_mask;
|
||||
u64 user_mask;
|
||||
u64 sys_val;
|
||||
u64 user_val;
|
||||
const struct arm64_ftr_bits *ftr_bits;
|
||||
};
|
||||
|
||||
@@ -159,6 +178,11 @@ static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
|
||||
return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
|
||||
}
|
||||
|
||||
static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
|
||||
{
|
||||
return (reg->user_val | (reg->sys_val & reg->user_mask));
|
||||
}
|
||||
|
||||
static inline int __attribute_const__
|
||||
cpuid_feature_extract_field(u64 features, int field, bool sign)
|
||||
{
|
||||
|
||||
@@ -56,6 +56,9 @@
|
||||
(0xf << MIDR_ARCHITECTURE_SHIFT) | \
|
||||
((partnum) << MIDR_PARTNUM_SHIFT))
|
||||
|
||||
#define MIDR_CPU_VAR_REV(var, rev) \
|
||||
(((var) << MIDR_VARIANT_SHIFT) | (rev))
|
||||
|
||||
#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
|
||||
MIDR_ARCHITECTURE_MASK)
|
||||
|
||||
@@ -71,6 +74,7 @@
|
||||
#define ARM_CPU_IMP_APM 0x50
|
||||
#define ARM_CPU_IMP_CAVIUM 0x43
|
||||
#define ARM_CPU_IMP_BRCM 0x42
|
||||
#define ARM_CPU_IMP_QCOM 0x51
|
||||
|
||||
#define ARM_CPU_PART_AEM_V8 0xD0F
|
||||
#define ARM_CPU_PART_FOUNDATION 0xD00
|
||||
@@ -84,10 +88,13 @@
|
||||
|
||||
#define BRCM_CPU_PART_VULCAN 0x516
|
||||
|
||||
#define QCOM_CPU_PART_FALKOR_V1 0x800
|
||||
|
||||
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
|
||||
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
|
||||
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
|
||||
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
|
||||
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
@@ -332,6 +332,8 @@ bool aarch64_insn_is_branch(u32 insn);
|
||||
u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
|
||||
u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
|
||||
u32 insn, u64 imm);
|
||||
u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
|
||||
u32 insn);
|
||||
u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
|
||||
enum aarch64_insn_branch_type type);
|
||||
u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
|
||||
|
||||
@@ -188,6 +188,9 @@
|
||||
#define CPTR_EL2_DEFAULT 0x000033ff
|
||||
|
||||
/* Hyp Debug Configuration Register bits */
|
||||
#define MDCR_EL2_TPMS (1 << 14)
|
||||
#define MDCR_EL2_E2PB_MASK (UL(0x3))
|
||||
#define MDCR_EL2_E2PB_SHIFT (UL(12))
|
||||
#define MDCR_EL2_TDRA (1 << 11)
|
||||
#define MDCR_EL2_TDOSA (1 << 10)
|
||||
#define MDCR_EL2_TDA (1 << 9)
|
||||
|
||||
@@ -229,7 +229,12 @@ struct kvm_vcpu_arch {
|
||||
|
||||
/* Pointer to host CPU context */
|
||||
kvm_cpu_context_t *host_cpu_context;
|
||||
struct kvm_guest_debug_arch host_debug_state;
|
||||
struct {
|
||||
/* {Break,watch}point registers */
|
||||
struct kvm_guest_debug_arch regs;
|
||||
/* Statistical profiling extension */
|
||||
u64 pmscr_el1;
|
||||
} host_debug_state;
|
||||
|
||||
/* VGIC state */
|
||||
struct vgic_cpu vgic_cpu;
|
||||
|
||||
@@ -47,7 +47,7 @@
|
||||
* If the page is in the bottom half, we have to use the top half. If
|
||||
* the page is in the top half, we have to use the bottom half:
|
||||
*
|
||||
* T = __virt_to_phys(__hyp_idmap_text_start)
|
||||
* T = __pa_symbol(__hyp_idmap_text_start)
|
||||
* if (T & BIT(VA_BITS - 1))
|
||||
* HYP_VA_MIN = 0 //idmap in upper half
|
||||
* else
|
||||
@@ -271,7 +271,7 @@ static inline void __kvm_flush_dcache_pud(pud_t pud)
|
||||
kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);
|
||||
}
|
||||
|
||||
#define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x))
|
||||
#define kvm_virt_to_phys(x) __pa_symbol(x)
|
||||
|
||||
void kvm_set_way_flush(struct kvm_vcpu *vcpu);
|
||||
void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
|
||||
|
||||
@@ -19,7 +19,7 @@
|
||||
__asm__(".arch_extension lse");
|
||||
|
||||
/* Move the ll/sc atomics out-of-line */
|
||||
#define __LL_SC_INLINE
|
||||
#define __LL_SC_INLINE notrace
|
||||
#define __LL_SC_PREFIX(x) __ll_sc_##x
|
||||
#define __LL_SC_EXPORT(x) EXPORT_SYMBOL(__LL_SC_PREFIX(x))
|
||||
|
||||
|
||||
@@ -101,25 +101,6 @@
|
||||
#define KASAN_SHADOW_SIZE (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical vs virtual RAM address space conversion. These are
|
||||
* private definitions which should NOT be used outside memory.h
|
||||
* files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
|
||||
*/
|
||||
#define __virt_to_phys(x) ({ \
|
||||
phys_addr_t __x = (phys_addr_t)(x); \
|
||||
__x & BIT(VA_BITS - 1) ? (__x & ~PAGE_OFFSET) + PHYS_OFFSET : \
|
||||
(__x - kimage_voffset); })
|
||||
|
||||
#define __phys_to_virt(x) ((unsigned long)((x) - PHYS_OFFSET) | PAGE_OFFSET)
|
||||
#define __phys_to_kimg(x) ((unsigned long)((x) + kimage_voffset))
|
||||
|
||||
/*
|
||||
* Convert a page to/from a physical address
|
||||
*/
|
||||
#define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page)))
|
||||
#define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys)))
|
||||
|
||||
/*
|
||||
* Memory types available.
|
||||
*/
|
||||
@@ -186,6 +167,48 @@ static inline unsigned long kaslr_offset(void)
|
||||
*/
|
||||
#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
|
||||
|
||||
/*
|
||||
* Physical vs virtual RAM address space conversion. These are
|
||||
* private definitions which should NOT be used outside memory.h
|
||||
* files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* The linear kernel range starts in the middle of the virtual adddress
|
||||
* space. Testing the top bit for the start of the region is a
|
||||
* sufficient check.
|
||||
*/
|
||||
#define __is_lm_address(addr) (!!((addr) & BIT(VA_BITS - 1)))
|
||||
|
||||
#define __lm_to_phys(addr) (((addr) & ~PAGE_OFFSET) + PHYS_OFFSET)
|
||||
#define __kimg_to_phys(addr) ((addr) - kimage_voffset)
|
||||
|
||||
#define __virt_to_phys_nodebug(x) ({ \
|
||||
phys_addr_t __x = (phys_addr_t)(x); \
|
||||
__is_lm_address(__x) ? __lm_to_phys(__x) : \
|
||||
__kimg_to_phys(__x); \
|
||||
})
|
||||
|
||||
#define __pa_symbol_nodebug(x) __kimg_to_phys((phys_addr_t)(x))
|
||||
|
||||
#ifdef CONFIG_DEBUG_VIRTUAL
|
||||
extern phys_addr_t __virt_to_phys(unsigned long x);
|
||||
extern phys_addr_t __phys_addr_symbol(unsigned long x);
|
||||
#else
|
||||
#define __virt_to_phys(x) __virt_to_phys_nodebug(x)
|
||||
#define __phys_addr_symbol(x) __pa_symbol_nodebug(x)
|
||||
#endif
|
||||
|
||||
#define __phys_to_virt(x) ((unsigned long)((x) - PHYS_OFFSET) | PAGE_OFFSET)
|
||||
#define __phys_to_kimg(x) ((unsigned long)((x) + kimage_voffset))
|
||||
|
||||
/*
|
||||
* Convert a page to/from a physical address
|
||||
*/
|
||||
#define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page)))
|
||||
#define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys)))
|
||||
|
||||
/*
|
||||
* Note: Drivers should NOT use these. They are the wrong
|
||||
* translation for translating DMA addresses. Use the driver
|
||||
@@ -207,9 +230,12 @@ static inline void *phys_to_virt(phys_addr_t x)
|
||||
* Drivers should NOT use these either.
|
||||
*/
|
||||
#define __pa(x) __virt_to_phys((unsigned long)(x))
|
||||
#define __pa_symbol(x) __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0))
|
||||
#define __pa_nodebug(x) __virt_to_phys_nodebug((unsigned long)(x))
|
||||
#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
|
||||
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
|
||||
#define virt_to_pfn(x) __phys_to_pfn(__virt_to_phys(x))
|
||||
#define virt_to_pfn(x) __phys_to_pfn(__virt_to_phys((unsigned long)(x)))
|
||||
#define sym_to_pfn(x) __phys_to_pfn(__pa_symbol(x))
|
||||
|
||||
/*
|
||||
* virt_to_page(k) convert a _valid_ virtual address to struct page *
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user