mirror of
https://github.com/ukui/kernel.git
synced 2026-03-09 10:07:04 -07:00
Merge tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.7 kernel cycle.
There are no core changes this time, only driver developments:
- New driver for the Dialog Semiconductor DA9062 Power Management
Integrated Circuit (PMIC).
- Renesas SH-PFC has improved consistency, with group and register
checks in the configuration checker.
- New subdriver for the Qualcomm IPQ6018.
- Add the RGMII pin control functionality to Qualcomm IPQ8064.
- Performance and code quality cleanups in the Mediatek driver.
- Improve the Broadcom BCM2835 support to cover all the GPIOs that
exist in it.
- The Allwinner/Sunxi driver properly masks non-wakeup IRQs on
suspend.
- Add some missing groups and functions to the Ingenic driver.
- Convert some of the Freescale device tree bindings to use the new
and all improved JSON YAML markup.
- Refactorings and support for the SFIO/GPIO in the Tegra194 SoC
driver.
- Support high impedance mode in the Spreadtrum/Unisoc driver"
* tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits)
pinctrl: qcom: fix compilation error
pinctrl: qcom: use scm_call to route GPIO irq to Apps
pinctrl: sprd: Add pin high impedance mode support
pinctrl: sprd: Use the correct pin output configuration
pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
pinctrl: tegra: Renumber the GG.0 and GG.1 pins
pinctrl: tegra: Do not add default pin range on Tegra194
pinctrl: tegra: Pass struct tegra_pmx for pin range check
pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
pinctrl: tegra: Fix whitespace issues for improved readability
pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow
pinctrl: freescale: drop the dependency on ARM64 for i.MX8M
Revert "pinctrl: mvebu: armada-37xx: use use platform api"
dt-bindings: pinctrl: at91: Fix a typo ("descibe")
pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm
pinctrl: sprd: Fix the kconfig warning
pinctrl: ingenic: add hdmi-ddc pin control group
pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member
pinctrl: sprd: Allow the SPRD pinctrl driver building into a module
pinctrl: Export some needed symbols at module load time
...
This commit is contained in:
Linus Torvalds
@@ -38,7 +38,7 @@ Bank: 3 (A, B and C)
|
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0xffffffff 0x7fff3ccf /* pioB */
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0xffffffff 0x007fffff /* pioC */
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For each peripheral/bank we will descibe in a u32 if a pin can be
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For each peripheral/bank we will describe in a u32 if a pin can be
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configured in it by putting 1 to the pin bit (1 << pin)
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Let's take the pioA on peripheral B
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@@ -1,36 +0,0 @@
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* Freescale IMX8MM IOMUX Controller
|
||||
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||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx8mm-iomuxc"
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- reg: should contain the base physical address and size of the iomuxc
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registers.
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||||
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||||
Required properties in sub-nodes:
|
||||
- fsl,pins: each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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input_val> are specified using a PIN_FUNC_ID macro, which can be found in
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<arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last integer CONFIG is
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the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini
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Reference Manual for detailed CONFIG settings.
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Examples:
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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};
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mm-iomuxc";
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reg = <0x0 0x30330000 0x0 0x10000>;
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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>;
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};
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};
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@@ -0,0 +1,82 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX8MM IOMUX Controller
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maintainers:
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- Anson Huang <Anson.Huang@nxp.com>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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const: fsl,imx8mm-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX8M Mini Reference Manual for detailed CONFIG settings.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-matrix
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- items:
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||||
items:
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- description: |
|
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"mux_reg" indicates the offset of mux register.
|
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- description: |
|
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"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
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- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
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- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
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- description: |
|
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"pad_setting" indicates the pad configuration value to be applied.
|
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required:
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- fsl,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mm-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_uart2: uart2grp {
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fsl,pins =
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<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
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<0x240 0x4A8 0x000 0x0 0x0 0x140>;
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};
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};
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||||
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...
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@@ -1,39 +0,0 @@
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* Freescale IMX8MN IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx8mn-iomuxc"
|
||||
- reg: should contain the base physical address and size of the iomuxc
|
||||
registers.
|
||||
|
||||
Required properties in sub-nodes:
|
||||
- fsl,pins: each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
||||
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
|
||||
<arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last integer CONFIG is
|
||||
the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
|
||||
Reference Manual for detailed CONFIG settings.
|
||||
|
||||
Examples:
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||||
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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};
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mn-iomuxc";
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reg = <0x0 0x30330000 0x0 0x10000>;
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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||||
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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||||
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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||||
MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
|
||||
MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
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MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
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||||
>;
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||||
};
|
||||
};
|
||||
@@ -0,0 +1,82 @@
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||||
# SPDX-License-Identifier: GPL-2.0
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||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX8MN IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mn-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
- items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mn-iomuxc";
|
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reg = <0x30330000 0x10000>;
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins =
|
||||
<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
|
||||
<0x240 0x4A8 0x000 0x0 0x0 0x140>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -30,8 +30,6 @@ patternProperties:
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
@@ -39,6 +37,22 @@ patternProperties:
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
- items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
@@ -59,10 +73,9 @@ examples:
|
||||
reg = <0x30330000 0x10000>;
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
0x228 0x488 0x5F0 0x0 0x6 0x49
|
||||
0x228 0x488 0x000 0x0 0x0 0x49
|
||||
>;
|
||||
fsl,pins =
|
||||
<0x228 0x488 0x5F0 0x0 0x6 0x49>,
|
||||
<0x228 0x488 0x000 0x0 0x0 0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -1,36 +0,0 @@
|
||||
* Freescale IMX8MQ IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx8mq-iomuxc"
|
||||
- reg: should contain the base physical address and size of the iomuxc
|
||||
registers.
|
||||
|
||||
Required properties in sub-nodes:
|
||||
- fsl,pins: each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
||||
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
|
||||
imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is
|
||||
the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad
|
||||
Reference Manual for detailed CONFIG settings.
|
||||
|
||||
Examples:
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
};
|
||||
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x0 0x30330000 0x0 0x10000>;
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
||||
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,82 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX8MQ IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mq-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX8M Quad Reference Manual for detailed CONFIG settings.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
- items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins =
|
||||
<0x234 0x49C 0x4F4 0x0 0x0 0x49>,
|
||||
<0x238 0x4A0 0x4F4 0x0 0x0 0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq6018-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. IPQ6018 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Sricharan R <sricharan@codeaurora.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
IPQ6018 platform.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,ipq6018-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description:
|
||||
Specifies the PIN numbers and Flags, as defined in defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pinmux$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
allOf:
|
||||
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
|
||||
sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
|
||||
qdsd_data3 ]
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
|
||||
atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac,
|
||||
atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0,
|
||||
atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp1_i2c,
|
||||
blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp6_i2c, blsp1_spi,
|
||||
blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi,
|
||||
blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi,
|
||||
blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi,
|
||||
blsp6_spi, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
|
||||
cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
|
||||
cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v,
|
||||
dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass,
|
||||
flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
|
||||
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0,
|
||||
gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2,
|
||||
ldo_en, ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc,
|
||||
nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2, pri_mi2s,
|
||||
pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
|
||||
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
|
||||
pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1,
|
||||
qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
|
||||
qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
|
||||
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
|
||||
qdss_tracedata_a, qdss_tracedata_b, reset_n, sd_card, sd_write,
|
||||
sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3,
|
||||
uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq6018-pinctrl";
|
||||
reg = <0x01000000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 80>;
|
||||
|
||||
serial3-pinmux {
|
||||
pins = "gpio44", "gpio45";
|
||||
function = "blsp2_uart";
|
||||
drive-strength = <8>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
+19
-18
@@ -2743,8 +2743,8 @@ L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
|
||||
L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/pinctrl/aspeed/
|
||||
F: Documentation/devicetree/bindings/pinctrl/aspeed,*
|
||||
F: drivers/pinctrl/aspeed/
|
||||
|
||||
ASPEED SCU INTERRUPT CONTROLLER DRIVER
|
||||
M: Eddie James <eajames@linux.ibm.com>
|
||||
@@ -4958,6 +4958,7 @@ F: drivers/leds/leds-da90??.c
|
||||
F: drivers/mfd/da903x.c
|
||||
F: drivers/mfd/da90??-*.c
|
||||
F: drivers/mfd/da91??-*.c
|
||||
F: drivers/pinctrl/pinctrl-da90??.c
|
||||
F: drivers/power/supply/da9052-battery.c
|
||||
F: drivers/power/supply/da91??-*.c
|
||||
F: drivers/regulator/da903x.c
|
||||
@@ -13267,21 +13268,13 @@ K: \b(clone_args|kernel_clone_args)\b
|
||||
PIN CONTROL SUBSYSTEM
|
||||
M: Linus Walleij <linus.walleij@linaro.org>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
|
||||
F: Documentation/devicetree/bindings/pinctrl/
|
||||
F: Documentation/driver-api/pinctl.rst
|
||||
F: drivers/pinctrl/
|
||||
F: include/linux/pinctrl/
|
||||
|
||||
PIN CONTROLLER - MICROCHIP AT91
|
||||
M: Ludovic Desroches <ludovic.desroches@microchip.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/pinctrl/pinctrl-at91*
|
||||
F: drivers/gpio/gpio-sama5d2-piobu.c
|
||||
|
||||
PIN CONTROLLER - FREESCALE
|
||||
M: Dong Aisheng <aisheng.dong@nxp.com>
|
||||
M: Fabio Estevam <festevam@gmail.com>
|
||||
@@ -13290,14 +13283,14 @@ M: Stefan Agner <stefan@agner.ch>
|
||||
R: Pengutronix Kernel Team <kernel@pengutronix.de>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/pinctrl/freescale/
|
||||
F: Documentation/devicetree/bindings/pinctrl/fsl,*
|
||||
F: drivers/pinctrl/freescale/
|
||||
|
||||
PIN CONTROLLER - INTEL
|
||||
M: Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
M: Andy Shevchenko <andy@kernel.org>
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
|
||||
F: drivers/pinctrl/intel/
|
||||
|
||||
PIN CONTROLLER - MEDIATEK
|
||||
@@ -13308,18 +13301,26 @@ F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
|
||||
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
|
||||
F: drivers/pinctrl/mediatek/
|
||||
|
||||
PIN CONTROLLER - MICROCHIP AT91
|
||||
M: Ludovic Desroches <ludovic.desroches@microchip.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/gpio/gpio-sama5d2-piobu.c
|
||||
F: drivers/pinctrl/pinctrl-at91*
|
||||
|
||||
PIN CONTROLLER - QUALCOMM
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
S: Maintained
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pinctrl/qcom,*.txt
|
||||
F: drivers/pinctrl/qcom/
|
||||
|
||||
PIN CONTROLLER - RENESAS
|
||||
M: Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
L: linux-renesas-soc@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
|
||||
F: drivers/pinctrl/pinctrl-rz*
|
||||
F: drivers/pinctrl/sh-pfc/
|
||||
|
||||
@@ -13329,12 +13330,12 @@ M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
|
||||
Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
|
||||
F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
|
||||
F: drivers/pinctrl/samsung/
|
||||
F: include/dt-bindings/pinctrl/samsung.h
|
||||
F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
|
||||
|
||||
PIN CONTROLLER - SINGLE
|
||||
M: Tony Lindgren <tony@atomide.com>
|
||||
@@ -13347,8 +13348,8 @@ F: drivers/pinctrl/pinctrl-single.c
|
||||
PIN CONTROLLER - ST SPEAR
|
||||
M: Viresh Kumar <vireshk@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
S: Maintained
|
||||
W: http://www.st.com/spear
|
||||
F: drivers/pinctrl/spear/
|
||||
|
||||
PISTACHIO SOC SUPPORT
|
||||
|
||||
@@ -149,6 +149,7 @@ struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip,
|
||||
|
||||
return &gdev->descs[hwnum];
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gpiochip_get_desc);
|
||||
|
||||
/**
|
||||
* desc_to_gpio - convert a GPIO descriptor to the integer namespace
|
||||
|
||||
@@ -126,6 +126,18 @@ config PINCTRL_DA850_PUPD
|
||||
Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control
|
||||
pullup/pulldown pin groups.
|
||||
|
||||
config PINCTRL_DA9062
|
||||
tristate "Dialog Semiconductor DA9062 PMIC pinctrl and GPIO Support"
|
||||
depends on MFD_DA9062
|
||||
select GPIOLIB
|
||||
help
|
||||
The Dialog DA9062 PMIC provides multiple GPIOs that can be muxed for
|
||||
different functions. This driver bundles a pinctrl driver to select the
|
||||
function muxing and a GPIO driver to handle the GPIO when the GPIO
|
||||
function is selected.
|
||||
|
||||
Say yes to enable pinctrl and GPIO support for the DA9062 PMIC.
|
||||
|
||||
config PINCTRL_DIGICOLOR
|
||||
bool
|
||||
depends on OF && (ARCH_DIGICOLOR || COMPILE_TEST)
|
||||
|
||||
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
|
||||
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
|
||||
obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
|
||||
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
|
||||
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
|
||||
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
|
||||
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
|
||||
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -37,12 +37,10 @@
|
||||
|
||||
#define MODULE_NAME "pinctrl-bcm2835"
|
||||
#define BCM2835_NUM_GPIOS 54
|
||||
#define BCM2711_NUM_GPIOS 58
|
||||
#define BCM2835_NUM_BANKS 2
|
||||
#define BCM2835_NUM_IRQS 3
|
||||
|
||||
#define BCM2835_PIN_BITMAP_SZ \
|
||||
DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
|
||||
|
||||
/* GPIO register offsets */
|
||||
#define GPFSEL0 0x0 /* Function Select */
|
||||
#define GPSET0 0x1c /* Pin Output Set */
|
||||
@@ -81,10 +79,11 @@ struct bcm2835_pinctrl {
|
||||
|
||||
/* note: locking assumes each bank will have its own unsigned long */
|
||||
unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
|
||||
unsigned int irq_type[BCM2835_NUM_GPIOS];
|
||||
unsigned int irq_type[BCM2711_NUM_GPIOS];
|
||||
|
||||
struct pinctrl_dev *pctl_dev;
|
||||
struct gpio_chip gpio_chip;
|
||||
struct pinctrl_desc pctl_desc;
|
||||
struct pinctrl_gpio_range gpio_range;
|
||||
|
||||
raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
|
||||
@@ -147,6 +146,10 @@ static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
|
||||
BCM2835_GPIO_PIN(51),
|
||||
BCM2835_GPIO_PIN(52),
|
||||
BCM2835_GPIO_PIN(53),
|
||||
BCM2835_GPIO_PIN(54),
|
||||
BCM2835_GPIO_PIN(55),
|
||||
BCM2835_GPIO_PIN(56),
|
||||
BCM2835_GPIO_PIN(57),
|
||||
};
|
||||
|
||||
/* one pin per group */
|
||||
@@ -205,6 +208,10 @@ static const char * const bcm2835_gpio_groups[] = {
|
||||
"gpio51",
|
||||
"gpio52",
|
||||
"gpio53",
|
||||
"gpio54",
|
||||
"gpio55",
|
||||
"gpio56",
|
||||
"gpio57",
|
||||
};
|
||||
|
||||
enum bcm2835_fsel {
|
||||
@@ -322,7 +329,10 @@ static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offse
|
||||
if (fsel > BCM2835_FSEL_GPIO_OUT)
|
||||
return -EINVAL;
|
||||
|
||||
return (fsel == BCM2835_FSEL_GPIO_IN);
|
||||
if (fsel == BCM2835_FSEL_GPIO_IN)
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
}
|
||||
|
||||
static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
@@ -355,6 +365,22 @@ static const struct gpio_chip bcm2835_gpio_chip = {
|
||||
.can_sleep = false,
|
||||
};
|
||||
|
||||
static const struct gpio_chip bcm2711_gpio_chip = {
|
||||
.label = "pinctrl-bcm2711",
|
||||
.owner = THIS_MODULE,
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.direction_input = bcm2835_gpio_direction_input,
|
||||
.direction_output = bcm2835_gpio_direction_output,
|
||||
.get_direction = bcm2835_gpio_get_direction,
|
||||
.get = bcm2835_gpio_get,
|
||||
.set = bcm2835_gpio_set,
|
||||
.set_config = gpiochip_generic_config,
|
||||
.base = -1,
|
||||
.ngpio = BCM2711_NUM_GPIOS,
|
||||
.can_sleep = false,
|
||||
};
|
||||
|
||||
static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
|
||||
unsigned int bank, u32 mask)
|
||||
{
|
||||
@@ -401,7 +427,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
|
||||
bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
|
||||
bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
|
||||
break;
|
||||
case 2: /* IRQ2 covers GPIOs 46-53 */
|
||||
case 2: /* IRQ2 covers GPIOs 46-57 */
|
||||
bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
|
||||
break;
|
||||
}
|
||||
@@ -620,7 +646,7 @@ static struct irq_chip bcm2835_gpio_irq_chip = {
|
||||
|
||||
static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
return ARRAY_SIZE(bcm2835_gpio_groups);
|
||||
return BCM2835_NUM_GPIOS;
|
||||
}
|
||||
|
||||
static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
|
||||
@@ -778,7 +804,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
|
||||
if (err)
|
||||
goto out;
|
||||
if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
|
||||
if (pin >= pc->pctl_desc.npins) {
|
||||
dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
|
||||
np, pin);
|
||||
err = -EINVAL;
|
||||
@@ -854,7 +880,7 @@ static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
{
|
||||
/* every pin can do every function */
|
||||
*groups = bcm2835_gpio_groups;
|
||||
*num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
|
||||
*num_groups = BCM2835_NUM_GPIOS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1054,29 +1080,62 @@ static const struct pinconf_ops bcm2711_pinconf_ops = {
|
||||
.pin_config_set = bcm2711_pinconf_set,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc bcm2835_pinctrl_desc = {
|
||||
static const struct pinctrl_desc bcm2835_pinctrl_desc = {
|
||||
.name = MODULE_NAME,
|
||||
.pins = bcm2835_gpio_pins,
|
||||
.npins = ARRAY_SIZE(bcm2835_gpio_pins),
|
||||
.npins = BCM2835_NUM_GPIOS,
|
||||
.pctlops = &bcm2835_pctl_ops,
|
||||
.pmxops = &bcm2835_pmx_ops,
|
||||
.confops = &bcm2835_pinconf_ops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
|
||||
static const struct pinctrl_desc bcm2711_pinctrl_desc = {
|
||||
.name = "pinctrl-bcm2711",
|
||||
.pins = bcm2835_gpio_pins,
|
||||
.npins = BCM2711_NUM_GPIOS,
|
||||
.pctlops = &bcm2835_pctl_ops,
|
||||
.pmxops = &bcm2835_pmx_ops,
|
||||
.confops = &bcm2711_pinconf_ops,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
|
||||
.name = MODULE_NAME,
|
||||
.npins = BCM2835_NUM_GPIOS,
|
||||
};
|
||||
|
||||
static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
|
||||
.name = "pinctrl-bcm2711",
|
||||
.npins = BCM2711_NUM_GPIOS,
|
||||
};
|
||||
|
||||
struct bcm_plat_data {
|
||||
const struct gpio_chip *gpio_chip;
|
||||
const struct pinctrl_desc *pctl_desc;
|
||||
const struct pinctrl_gpio_range *gpio_range;
|
||||
};
|
||||
|
||||
static const struct bcm_plat_data bcm2835_plat_data = {
|
||||
.gpio_chip = &bcm2835_gpio_chip,
|
||||
.pctl_desc = &bcm2835_pinctrl_desc,
|
||||
.gpio_range = &bcm2835_pinctrl_gpio_range,
|
||||
};
|
||||
|
||||
static const struct bcm_plat_data bcm2711_plat_data = {
|
||||
.gpio_chip = &bcm2711_gpio_chip,
|
||||
.pctl_desc = &bcm2711_pinctrl_desc,
|
||||
.gpio_range = &bcm2711_pinctrl_gpio_range,
|
||||
};
|
||||
|
||||
static const struct of_device_id bcm2835_pinctrl_match[] = {
|
||||
{
|
||||
.compatible = "brcm,bcm2835-gpio",
|
||||
.data = &bcm2835_pinconf_ops,
|
||||
.data = &bcm2835_plat_data,
|
||||
},
|
||||
{
|
||||
.compatible = "brcm,bcm2711-gpio",
|
||||
.data = &bcm2711_pinconf_ops,
|
||||
.data = &bcm2711_plat_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
@@ -1085,14 +1144,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct bcm_plat_data *pdata;
|
||||
struct bcm2835_pinctrl *pc;
|
||||
struct gpio_irq_chip *girq;
|
||||
struct resource iomem;
|
||||
int err, i;
|
||||
const struct of_device_id *match;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
|
||||
|
||||
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
|
||||
if (!pc)
|
||||
@@ -1111,7 +1171,13 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(pc->base))
|
||||
return PTR_ERR(pc->base);
|
||||
|
||||
pc->gpio_chip = bcm2835_gpio_chip;
|
||||
match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
|
||||
if (!match)
|
||||
return -EINVAL;
|
||||
|
||||
pdata = match->data;
|
||||
|
||||
pc->gpio_chip = *pdata->gpio_chip;
|
||||
pc->gpio_chip.parent = dev;
|
||||
pc->gpio_chip.of_node = np;
|
||||
|
||||
@@ -1162,19 +1228,14 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
|
||||
return err;
|
||||
}
|
||||
|
||||
match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
|
||||
if (match) {
|
||||
bcm2835_pinctrl_desc.confops =
|
||||
(const struct pinconf_ops *)match->data;
|
||||
}
|
||||
|
||||
pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
|
||||
pc->pctl_desc = *pdata->pctl_desc;
|
||||
pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
|
||||
if (IS_ERR(pc->pctl_dev)) {
|
||||
gpiochip_remove(&pc->gpio_chip);
|
||||
return PTR_ERR(pc->pctl_dev);
|
||||
}
|
||||
|
||||
pc->gpio_range = bcm2835_pinctrl_gpio_range;
|
||||
pc->gpio_range = *pdata->gpio_range;
|
||||
pc->gpio_range.base = pc->gpio_chip.base;
|
||||
pc->gpio_range.gc = &pc->gpio_chip;
|
||||
pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
|
||||
|
||||
@@ -363,7 +363,10 @@ static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
|
||||
unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
|
||||
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
|
||||
|
||||
return !(readl(chip->base + offset) & BIT(shift));
|
||||
if (readl(chip->base + offset) & BIT(shift))
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
|
||||
|
||||
@@ -176,6 +176,7 @@ const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
|
||||
|
||||
return desc->name;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pin_get_name);
|
||||
|
||||
/* Deletes a range of pin descriptors */
|
||||
static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev,
|
||||
|
||||
@@ -125,28 +125,28 @@ config PINCTRL_IMX7ULP
|
||||
|
||||
config PINCTRL_IMX8MM
|
||||
bool "IMX8MM pinctrl driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
depends on ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mm pinctrl driver
|
||||
|
||||
config PINCTRL_IMX8MN
|
||||
bool "IMX8MN pinctrl driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
depends on ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mn pinctrl driver
|
||||
|
||||
config PINCTRL_IMX8MP
|
||||
bool "IMX8MP pinctrl driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
depends on ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mp pinctrl driver
|
||||
|
||||
config PINCTRL_IMX8MQ
|
||||
bool "IMX8MQ pinctrl driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
depends on ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mq pinctrl driver
|
||||
|
||||
@@ -1070,15 +1070,12 @@ static const struct mtk_pin_soc mt6765_data = {
|
||||
.ngrps = ARRAY_SIZE(mtk_pins_mt6765),
|
||||
.eint_hw = &mt6765_eint_hw,
|
||||
.gpio_m = 0,
|
||||
.ies_present = true,
|
||||
.base_names = mt6765_pinctrl_register_base_names,
|
||||
.nbase_names = ARRAY_SIZE(mt6765_pinctrl_register_base_names),
|
||||
.bias_disable_set = mtk_pinconf_bias_disable_set,
|
||||
.bias_disable_get = mtk_pinconf_bias_disable_get,
|
||||
.bias_set = mtk_pinconf_bias_set,
|
||||
.bias_get = mtk_pinconf_bias_get,
|
||||
.drive_set = mtk_pinconf_drive_set_rev1,
|
||||
.drive_get = mtk_pinconf_drive_get_rev1,
|
||||
.bias_set_combo = mtk_pinconf_bias_set_combo,
|
||||
.bias_get_combo = mtk_pinconf_bias_get_combo,
|
||||
.drive_set = mtk_pinconf_drive_set_raw,
|
||||
.drive_get = mtk_pinconf_drive_get_raw,
|
||||
.adv_pull_get = mtk_pinconf_adv_pull_get,
|
||||
.adv_pull_set = mtk_pinconf_adv_pull_set,
|
||||
};
|
||||
|
||||
@@ -554,13 +554,10 @@ static const struct mtk_pin_soc mt8183_data = {
|
||||
.ngrps = ARRAY_SIZE(mtk_pins_mt8183),
|
||||
.eint_hw = &mt8183_eint_hw,
|
||||
.gpio_m = 0,
|
||||
.ies_present = true,
|
||||
.base_names = mt8183_pinctrl_register_base_names,
|
||||
.nbase_names = ARRAY_SIZE(mt8183_pinctrl_register_base_names),
|
||||
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
|
||||
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
|
||||
.bias_set = mtk_pinconf_bias_set_rev1,
|
||||
.bias_get = mtk_pinconf_bias_get_rev1,
|
||||
.bias_set_combo = mtk_pinconf_bias_set_combo,
|
||||
.bias_get_combo = mtk_pinconf_bias_get_combo,
|
||||
.drive_set = mtk_pinconf_drive_set_rev1,
|
||||
.drive_get = mtk_pinconf_drive_get_rev1,
|
||||
.adv_pull_get = mtk_pinconf_adv_pull_get,
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user