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Merge branch 'for-next/perf' into for-next/core
* for-next/perf: (25 commits) perf/marvell: Fix !CONFIG_OF build for CN10K DDR PMU driver drivers/perf: Add Apple icestorm/firestorm CPU PMU driver drivers/perf: arm_pmu: Handle 47 bit counters arm64: perf: Consistently make all event numbers as 16-bits arm64: perf: Expose some Armv9 common events under sysfs perf/marvell: cn10k DDR perf event core ownership perf/marvell: cn10k DDR perfmon event overflow handling perf/marvell: CN10k DDR performance monitor support dt-bindings: perf: marvell: cn10k ddr performance monitor perf/arm-cmn: Update watchpoint format perf/arm-cmn: Hide XP PUB events for CMN-600 perf: replace bitmap_weight with bitmap_empty where appropriate perf: Replace acpi_bus_get_device() perf/marvell_cn10k: Fix unused variable warning when W=1 and CONFIG_OF=n perf/arm-cmn: Make arm_cmn_debugfs static perf: MARVELL_CN10K_TAD_PMU should depend on ARCH_THUNDER perf/arm-ccn: Use platform_get_irq() to get the interrupt irqchip/apple-aic: Move PMU-specific registers to their own include file arm64: dts: apple: Add t8303 PMU nodes arm64: dts: apple: Add t8103 PMU interrupt affinities ...
This commit is contained in:
Will Deacon
@@ -20,6 +20,8 @@ properties:
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items:
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- enum:
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- apm,potenza-pmu
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- apple,firestorm-pmu
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- apple,icestorm-pmu
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- arm,armv8-pmuv3 # Only for s/w models
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- arm,arm1136-pmu
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- arm,arm1176-pmu
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@@ -56,6 +56,8 @@ properties:
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- 1: virtual HV timer
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- 2: physical guest timer
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- 3: virtual guest timer
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- 4: 'efficient' CPU PMU
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- 5: 'performance' CPU PMU
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The 3rd cell contains the interrupt flags. This is normally
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IRQ_TYPE_LEVEL_HIGH (4).
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@@ -68,6 +70,35 @@ properties:
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power-domains:
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maxItems: 1
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affinities:
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type: object
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additionalProperties: false
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description:
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FIQ affinity can be expressed as a single "affinities" node,
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containing a set of sub-nodes, one per FIQ with a non-default
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affinity.
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patternProperties:
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"^.+-affinity$":
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type: object
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additionalProperties: false
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properties:
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apple,fiq-index:
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description:
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The interrupt number specified as a FIQ, and for which
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the affinity is not the default.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 5
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cpus:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Should be a list of phandles to CPU nodes (as described in
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Documentation/devicetree/bindings/arm/cpus.yaml).
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required:
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- fiq-index
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- cpus
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required:
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- compatible
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- '#interrupt-cells'
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@@ -0,0 +1,37 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell CN10K DDR performance monitor
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maintainers:
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- Bharat Bhushan <bbhushan2@marvell.com>
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properties:
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compatible:
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items:
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- enum:
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- marvell,cn10k-ddr-pmu
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pmu@87e1c0000000 {
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compatible = "marvell,cn10k-ddr-pmu";
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reg = <0x87e1 0xc0000000 0x0 0x10000>;
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};
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};
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@@ -97,6 +97,18 @@
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<AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-e {
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compatible = "apple,icestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-p {
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compatible = "apple,firestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
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};
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -213,6 +225,18 @@
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interrupt-controller;
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reg = <0x2 0x3b100000 0x0 0x8000>;
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power-domains = <&ps_aic>;
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affinities {
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e-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_E>;
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cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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p-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_P>;
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cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
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};
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};
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};
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pmgr: power-management@23b700000 {
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@@ -0,0 +1,64 @@
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// SPDX-License-Identifier: GPL-2.0
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#ifndef __ASM_APPLE_M1_PMU_h
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#define __ASM_APPLE_M1_PMU_h
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#include <linux/bits.h>
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#include <asm/sysreg.h>
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/* Counters */
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#define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0)
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#define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0)
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#define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0)
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#define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0)
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#define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0)
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#define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0)
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#define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0)
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#define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0)
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#define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0)
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#define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0)
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/* Core PMC control register */
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#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0)
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#define PMCR0_CNT_ENABLE_0_7 GENMASK(7, 0)
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#define PMCR0_IMODE GENMASK(10, 8)
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#define PMCR0_IMODE_OFF 0
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#define PMCR0_IMODE_PMI 1
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#define PMCR0_IMODE_AIC 2
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#define PMCR0_IMODE_HALT 3
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#define PMCR0_IMODE_FIQ 4
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#define PMCR0_IACT BIT(11)
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#define PMCR0_PMI_ENABLE_0_7 GENMASK(19, 12)
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#define PMCR0_STOP_CNT_ON_PMI BIT(20)
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#define PMCR0_CNT_GLOB_L2C_EVT BIT(21)
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#define PMCR0_DEFER_PMI_TO_ERET BIT(22)
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#define PMCR0_ALLOW_CNT_EN_EL0 BIT(30)
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#define PMCR0_CNT_ENABLE_8_9 GENMASK(33, 32)
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#define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44)
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#define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0)
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#define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8)
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#define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16)
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#define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40)
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#define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48)
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#define SYS_IMP_APL_PMCR2_EL1 sys_reg(3, 1, 15, 2, 0)
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#define SYS_IMP_APL_PMCR3_EL1 sys_reg(3, 1, 15, 3, 0)
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#define SYS_IMP_APL_PMCR4_EL1 sys_reg(3, 1, 15, 4, 0)
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#define SYS_IMP_APL_PMESR0_EL1 sys_reg(3, 1, 15, 5, 0)
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#define PMESR0_EVT_CNT_2 GENMASK(7, 0)
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#define PMESR0_EVT_CNT_3 GENMASK(15, 8)
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#define PMESR0_EVT_CNT_4 GENMASK(23, 16)
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#define PMESR0_EVT_CNT_5 GENMASK(31, 24)
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#define SYS_IMP_APL_PMESR1_EL1 sys_reg(3, 1, 15, 6, 0)
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#define PMESR1_EVT_CNT_6 GENMASK(7, 0)
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#define PMESR1_EVT_CNT_7 GENMASK(15, 8)
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#define PMESR1_EVT_CNT_8 GENMASK(23, 16)
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#define PMESR1_EVT_CNT_9 GENMASK(31, 24)
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#define SYS_IMP_APL_PMSR_EL1 sys_reg(3, 1, 15, 13, 0)
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#define PMSR_OVERFLOW GENMASK(9, 0)
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#endif /* __ASM_APPLE_M1_PMU_h */
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+153
-139
@@ -15,70 +15,70 @@
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/*
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* Common architectural and microarchitectural event numbers.
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*/
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#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x01
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#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x02
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04
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#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x05
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#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x06
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#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x07
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#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x08
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#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09
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#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x0A
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#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x0B
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#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x0C
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#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x0D
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#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x0E
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#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x0F
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10
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#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11
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#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12
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#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x14
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x15
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x16
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x17
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x18
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#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19
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#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x1A
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#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x1B
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#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x1C
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#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D
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#define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20
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#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22
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#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23
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#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24
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#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25
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#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x2E
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x30
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#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x31
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x32
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x33
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#define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x34
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#define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x35
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
|
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
|
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#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
|
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
|
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#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
|
||||
#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
|
||||
#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005
|
||||
#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006
|
||||
#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007
|
||||
#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008
|
||||
#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009
|
||||
#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x000A
|
||||
#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x000B
|
||||
#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x000C
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x000D
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x000E
|
||||
#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x000F
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x0010
|
||||
#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x0011
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x0012
|
||||
#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x0013
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x0014
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x0015
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x0016
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x0017
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x0018
|
||||
#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x0019
|
||||
#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x001A
|
||||
#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x001B
|
||||
#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x001C
|
||||
#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x001D
|
||||
#define ARMV8_PMUV3_PERFCTR_CHAIN 0x001E
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x001F
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x0020
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x0021
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x0022
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x0023
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x0024
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x0025
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x0026
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x0027
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x0028
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x0029
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x002A
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x002B
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x002C
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x002D
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x002E
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x002F
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x0030
|
||||
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x0031
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x0032
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x0033
|
||||
#define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x0034
|
||||
#define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x0035
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x0036
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x0037
|
||||
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x0038
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x0039
|
||||
#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x003A
|
||||
#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x003B
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL 0x003C
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x003D
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x003E
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x003F
|
||||
|
||||
/* Statistical profiling extension microarchitectural events */
|
||||
#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
|
||||
@@ -96,6 +96,20 @@
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
|
||||
|
||||
/* Trace buffer events */
|
||||
#define ARMV8_PMUV3_PERFCTR_TRB_WRAP 0x400C
|
||||
#define ARMV8_PMUV3_PERFCTR_TRB_TRIG 0x400E
|
||||
|
||||
/* Trace unit events */
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0 0x4010
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 0x4011
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2 0x4012
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3 0x4013
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4 0x4018
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5 0x4019
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6 0x401A
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7 0x401B
|
||||
|
||||
/* additional latency from alignment events */
|
||||
#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
|
||||
#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
|
||||
@@ -107,91 +121,91 @@
|
||||
#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
|
||||
|
||||
/* ARMv8 recommended implementation defined event types */
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x42
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x44
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x45
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x46
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x47
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x48
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x0040
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x0042
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x0044
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x0045
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x0046
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x0047
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x0048
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x50
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x51
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x52
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x53
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x0050
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x0051
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x0052
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x0053
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x56
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x57
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x58
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x0056
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x0057
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x0058
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x5C
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x5D
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x5E
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x5F
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x62
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x63
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x64
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x65
|
||||
#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x66
|
||||
#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x67
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x68
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x69
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x6A
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x005C
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x005D
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x005E
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x005F
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x0062
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x0063
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x0064
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x0065
|
||||
#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x0066
|
||||
#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x0067
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x0068
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x0069
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x006A
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x6C
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x6D
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x6E
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x6F
|
||||
#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x70
|
||||
#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x71
|
||||
#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x72
|
||||
#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x73
|
||||
#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x74
|
||||
#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x75
|
||||
#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x76
|
||||
#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x77
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x78
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x79
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x7A
|
||||
#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x006C
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x006D
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x006E
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x006F
|
||||
#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x0070
|
||||
#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x0071
|
||||
#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x0072
|
||||
#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x0073
|
||||
#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x0074
|
||||
#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x0075
|
||||
#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x0076
|
||||
#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x0077
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x0078
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x0079
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x007A
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x7C
|
||||
#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x7D
|
||||
#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x7E
|
||||
#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x007C
|
||||
#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x007D
|
||||
#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x007E
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x81
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x82
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x83
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x84
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x0081
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x0082
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x0083
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x0084
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x86
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x87
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x88
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x0086
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x0087
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x0088
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x8A
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x8B
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x8C
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x8D
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x8E
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x8F
|
||||
#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x90
|
||||
#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x91
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x008A
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x008B
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x008C
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x008D
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x008E
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x008F
|
||||
#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x0090
|
||||
#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x0091
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0xA0
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0xA1
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0xA2
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0xA3
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0x00A0
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0x00A1
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0x00A2
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0x00A3
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0xA6
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0xA7
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0xA8
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0x00A6
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0x00A7
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0x00A8
|
||||
|
||||
/*
|
||||
* Per-CPU PMCR: config reg
|
||||
|
||||
@@ -242,6 +242,16 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
|
||||
ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
|
||||
ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
|
||||
ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
|
||||
ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP),
|
||||
ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG),
|
||||
ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0),
|
||||
ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1),
|
||||
ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2),
|
||||
ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3),
|
||||
ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4),
|
||||
ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5),
|
||||
ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6),
|
||||
ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7),
|
||||
ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
|
||||
ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
|
||||
ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
|
||||
|
||||
@@ -55,6 +55,7 @@
|
||||
#include <linux/limits.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/apple_m1_pmu.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/sysreg.h>
|
||||
#include <asm/virt.h>
|
||||
@@ -109,16 +110,6 @@
|
||||
* Note: sysreg-based IPIs are not supported yet.
|
||||
*/
|
||||
|
||||
/* Core PMC control register */
|
||||
#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0)
|
||||
#define PMCR0_IMODE GENMASK(10, 8)
|
||||
#define PMCR0_IMODE_OFF 0
|
||||
#define PMCR0_IMODE_PMI 1
|
||||
#define PMCR0_IMODE_AIC 2
|
||||
#define PMCR0_IMODE_HALT 3
|
||||
#define PMCR0_IMODE_FIQ 4
|
||||
#define PMCR0_IACT BIT(11)
|
||||
|
||||
/* IPI request registers */
|
||||
#define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0)
|
||||
#define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1)
|
||||
@@ -155,7 +146,7 @@
|
||||
#define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4)
|
||||
#define UPMSR_IACT BIT(0)
|
||||
|
||||
#define AIC_NR_FIQ 4
|
||||
#define AIC_NR_FIQ 6
|
||||
#define AIC_NR_SWIPI 32
|
||||
|
||||
/*
|
||||
@@ -177,6 +168,9 @@ struct aic_irq_chip {
|
||||
void __iomem *base;
|
||||
struct irq_domain *hw_domain;
|
||||
struct irq_domain *ipi_domain;
|
||||
struct {
|
||||
cpumask_t aff;
|
||||
} *fiq_aff[AIC_NR_FIQ];
|
||||
int nr_hw;
|
||||
};
|
||||
|
||||
@@ -412,16 +406,15 @@ static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)
|
||||
aic_irqc->nr_hw + AIC_TMR_EL02_VIRT);
|
||||
}
|
||||
|
||||
if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) ==
|
||||
(FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) {
|
||||
/*
|
||||
* Not supported yet, let's figure out how to handle this when
|
||||
* we implement these proprietary performance counters. For now,
|
||||
* just mask it and move on.
|
||||
*/
|
||||
pr_err_ratelimited("PMC FIQ fired. Masking.\n");
|
||||
sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,
|
||||
FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF));
|
||||
if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) {
|
||||
int irq;
|
||||
if (cpumask_test_cpu(smp_processor_id(),
|
||||
&aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff))
|
||||
irq = AIC_CPU_PMU_P;
|
||||
else
|
||||
irq = AIC_CPU_PMU_E;
|
||||
generic_handle_domain_irq(aic_irqc->hw_domain,
|
||||
aic_irqc->nr_hw + irq);
|
||||
}
|
||||
|
||||
if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ &&
|
||||
@@ -461,7 +454,18 @@ static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq,
|
||||
handle_fasteoi_irq, NULL, NULL);
|
||||
irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
|
||||
} else {
|
||||
irq_set_percpu_devid(irq);
|
||||
int fiq = hw - ic->nr_hw;
|
||||
|
||||
switch (fiq) {
|
||||
case AIC_CPU_PMU_P:
|
||||
case AIC_CPU_PMU_E:
|
||||
irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff);
|
||||
break;
|
||||
default:
|
||||
irq_set_percpu_devid(irq);
|
||||
break;
|
||||
}
|
||||
|
||||
irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data,
|
||||
handle_percpu_devid_irq, NULL, NULL);
|
||||
}
|
||||
@@ -793,12 +797,50 @@ static struct gic_kvm_info vgic_info __initdata = {
|
||||
.no_hw_deactivation = true,
|
||||
};
|
||||
|
||||
static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node *aff)
|
||||
{
|
||||
int i, n;
|
||||
u32 fiq;
|
||||
|
||||
if (of_property_read_u32(aff, "apple,fiq-index", &fiq) ||
|
||||
WARN_ON(fiq >= AIC_NR_FIQ) || ic->fiq_aff[fiq])
|
||||
return;
|
||||
|
||||
n = of_property_count_elems_of_size(aff, "cpus", sizeof(u32));
|
||||
if (WARN_ON(n < 0))
|
||||
return;
|
||||
|
||||
ic->fiq_aff[fiq] = kzalloc(sizeof(ic->fiq_aff[fiq]), GFP_KERNEL);
|
||||
if (!ic->fiq_aff[fiq])
|
||||
return;
|
||||
|
||||
for (i = 0; i < n; i++) {
|
||||
struct device_node *cpu_node;
|
||||
u32 cpu_phandle;
|
||||
int cpu;
|
||||
|
||||
if (of_property_read_u32_index(aff, "cpus", i, &cpu_phandle))
|
||||
continue;
|
||||
|
||||
cpu_node = of_find_node_by_phandle(cpu_phandle);
|
||||
if (WARN_ON(!cpu_node))
|
||||
continue;
|
||||
|
||||
cpu = of_cpu_node_to_id(cpu_node);
|
||||
if (WARN_ON(cpu < 0))
|
||||
continue;
|
||||
|
||||
cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff);
|
||||
}
|
||||
}
|
||||
|
||||
static int __init aic_of_ic_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
int i;
|
||||
void __iomem *regs;
|
||||
u32 info;
|
||||
struct aic_irq_chip *irqc;
|
||||
struct device_node *affs;
|
||||
|
||||
regs = of_iomap(node, 0);
|
||||
if (WARN_ON(!regs))
|
||||
@@ -832,6 +874,14 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
affs = of_get_child_by_name(node, "affinities");
|
||||
if (affs) {
|
||||
struct device_node *chld;
|
||||
|
||||
for_each_child_of_node(affs, chld)
|
||||
build_fiq_affinity(irqc, chld);
|
||||
}
|
||||
|
||||
set_handle_irq(aic_handle_irq);
|
||||
set_handle_fiq(aic_handle_fiq);
|
||||
|
||||
|
||||
+15
-1
@@ -141,11 +141,25 @@ config ARM_DMC620_PMU
|
||||
|
||||
config MARVELL_CN10K_TAD_PMU
|
||||
tristate "Marvell CN10K LLC-TAD PMU"
|
||||
depends on ARM64 || (COMPILE_TEST && 64BIT)
|
||||
depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
|
||||
help
|
||||
Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
|
||||
performance monitors on CN10K family silicons.
|
||||
|
||||
config APPLE_M1_CPU_PMU
|
||||
bool "Apple M1 CPU PMU support"
|
||||
depends on ARM_PMU && ARCH_APPLE
|
||||
help
|
||||
Provides support for the non-architectural CPU PMUs present on
|
||||
the Apple M1 SoCs and derivatives.
|
||||
|
||||
source "drivers/perf/hisilicon/Kconfig"
|
||||
|
||||
config MARVELL_CN10K_DDR_PMU
|
||||
tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
|
||||
depends on ARM64 || (COMPILE_TEST && 64BIT)
|
||||
help
|
||||
Enable perf support for Marvell DDR Performance monitoring
|
||||
event on CN10K platform.
|
||||
|
||||
endmenu
|
||||
|
||||
@@ -15,3 +15,5 @@ obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
|
||||
obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
|
||||
obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o
|
||||
obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o
|
||||
obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o
|
||||
obj-$(CONFIG_APPLE_M1_CPU_PMU) += apple_m1_cpu_pmu.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1096,7 +1096,7 @@ static void cci_pmu_enable(struct pmu *pmu)
|
||||
{
|
||||
struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
|
||||
struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
|
||||
int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs);
|
||||
bool enabled = !bitmap_empty(hw_events->used_mask, cci_pmu->num_cntrs);
|
||||
unsigned long flags;
|
||||
|
||||
if (!enabled)
|
||||
|
||||
@@ -1460,8 +1460,7 @@ static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
|
||||
static int arm_ccn_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct arm_ccn *ccn;
|
||||
struct resource *res;
|
||||
unsigned int irq;
|
||||
int irq;
|
||||
int err;
|
||||
|
||||
ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
|
||||
@@ -1474,10 +1473,9 @@ static int arm_ccn_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(ccn->base))
|
||||
return PTR_ERR(ccn->base);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
irq = res->start;
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
/* Check if we can use the interrupt */
|
||||
writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
|
||||
|
||||
+16
-7
@@ -71,9 +71,11 @@
|
||||
#define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18)
|
||||
#define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18,17)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(6)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_GRP BIT(4)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8)
|
||||
#define CMN600_WPn_CONFIG_WP_COMBINE BIT(6)
|
||||
#define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1)
|
||||
#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0)
|
||||
#define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08)
|
||||
@@ -155,6 +157,7 @@
|
||||
#define CMN_CONFIG_WP_COMBINE GENMASK_ULL(27, 24)
|
||||
#define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48)
|
||||
#define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51)
|
||||
/* Note that we don't yet support the tertiary match group on newer IPs */
|
||||
#define CMN_CONFIG_WP_GRP BIT_ULL(56)
|
||||
#define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(57)
|
||||
#define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0)
|
||||
@@ -353,7 +356,7 @@ static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct dentry *arm_cmn_debugfs;
|
||||
static struct dentry *arm_cmn_debugfs;
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static const char *arm_cmn_device_type(u8 type)
|
||||
@@ -595,6 +598,9 @@ static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
|
||||
if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3)))
|
||||
return 0;
|
||||
|
||||
if (chan == 4 && cmn->model == CMN600)
|
||||
return 0;
|
||||
|
||||
if ((chan == 5 && cmn->rsp_vc_num < 2) ||
|
||||
(chan == 6 && cmn->dat_vc_num < 2))
|
||||
return 0;
|
||||
@@ -905,15 +911,18 @@ static u32 arm_cmn_wp_config(struct perf_event *event)
|
||||
u32 grp = CMN_EVENT_WP_GRP(event);
|
||||
u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
|
||||
u32 combine = CMN_EVENT_WP_COMBINE(event);
|
||||
bool is_cmn600 = to_cmn(event->pmu)->model == CMN600;
|
||||
|
||||
config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
|
||||
FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
|
||||
FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
|
||||
FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE, exc) |
|
||||
FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
|
||||
if (exc)
|
||||
config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
|
||||
CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
|
||||
if (combine && !grp)
|
||||
config |= CMN_DTM_WPn_CONFIG_WP_COMBINE;
|
||||
|
||||
config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
|
||||
CMN_DTM_WPn_CONFIG_WP_COMBINE;
|
||||
return config;
|
||||
}
|
||||
|
||||
|
||||
@@ -109,6 +109,8 @@ static inline u64 arm_pmu_event_max_period(struct perf_event *event)
|
||||
{
|
||||
if (event->hw.flags & ARMPMU_EVT_64BIT)
|
||||
return GENMASK_ULL(63, 0);
|
||||
else if (event->hw.flags & ARMPMU_EVT_47BIT)
|
||||
return GENMASK_ULL(46, 0);
|
||||
else
|
||||
return GENMASK_ULL(31, 0);
|
||||
}
|
||||
@@ -524,7 +526,7 @@ static void armpmu_enable(struct pmu *pmu)
|
||||
{
|
||||
struct arm_pmu *armpmu = to_arm_pmu(pmu);
|
||||
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
||||
int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
|
||||
bool enabled = !bitmap_empty(hw_events->used_mask, armpmu->num_events);
|
||||
|
||||
/* For task-bound events we may be called on other CPUs */
|
||||
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
||||
@@ -785,7 +787,7 @@ static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
|
||||
{
|
||||
struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
|
||||
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
||||
int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
|
||||
bool enabled = !bitmap_empty(hw_events->used_mask, armpmu->num_events);
|
||||
|
||||
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
||||
return NOTIFY_DONE;
|
||||
|
||||
@@ -393,7 +393,7 @@ EXPORT_SYMBOL_GPL(hisi_uncore_pmu_read);
|
||||
void hisi_uncore_pmu_enable(struct pmu *pmu)
|
||||
{
|
||||
struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
|
||||
int enabled = bitmap_weight(hisi_pmu->pmu_events.used_mask,
|
||||
bool enabled = !bitmap_empty(hisi_pmu->pmu_events.used_mask,
|
||||
hisi_pmu->num_counters);
|
||||
|
||||
if (!enabled)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -368,10 +368,12 @@ static int tad_pmu_remove(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id tad_pmu_of_match[] = {
|
||||
{ .compatible = "marvell,cn10k-tad-pmu", },
|
||||
{},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_driver tad_pmu_driver = {
|
||||
.driver = {
|
||||
|
||||
@@ -887,13 +887,11 @@ static struct tx2_uncore_pmu *tx2_uncore_pmu_init_dev(struct device *dev,
|
||||
static acpi_status tx2_uncore_pmu_add(acpi_handle handle, u32 level,
|
||||
void *data, void **return_value)
|
||||
{
|
||||
struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
|
||||
struct tx2_uncore_pmu *tx2_pmu;
|
||||
struct acpi_device *adev;
|
||||
enum tx2_uncore_type type;
|
||||
|
||||
if (acpi_bus_get_device(handle, &adev))
|
||||
return AE_OK;
|
||||
if (acpi_bus_get_status(adev) || !adev->status.present)
|
||||
if (!adev || acpi_bus_get_status(adev) || !adev->status.present)
|
||||
return AE_OK;
|
||||
|
||||
type = get_tx2_pmu_type(adev);
|
||||
|
||||
@@ -867,7 +867,7 @@ static void xgene_perf_pmu_enable(struct pmu *pmu)
|
||||
{
|
||||
struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
|
||||
struct xgene_pmu *xgene_pmu = pmu_dev->parent;
|
||||
int enabled = bitmap_weight(pmu_dev->cntr_assign_mask,
|
||||
bool enabled = !bitmap_empty(pmu_dev->cntr_assign_mask,
|
||||
pmu_dev->max_counters);
|
||||
|
||||
if (!enabled)
|
||||
@@ -1549,14 +1549,12 @@ static const struct acpi_device_id *xgene_pmu_acpi_match_type(
|
||||
static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,
|
||||
void *data, void **return_value)
|
||||
{
|
||||
struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
|
||||
const struct acpi_device_id *acpi_id;
|
||||
struct xgene_pmu *xgene_pmu = data;
|
||||
struct xgene_pmu_dev_ctx *ctx;
|
||||
struct acpi_device *adev;
|
||||
|
||||
if (acpi_bus_get_device(handle, &adev))
|
||||
return AE_OK;
|
||||
if (acpi_bus_get_status(adev) || !adev->status.present)
|
||||
if (!adev || acpi_bus_get_status(adev) || !adev->status.present)
|
||||
return AE_OK;
|
||||
|
||||
acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user