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clk: rockchip: Add clock controller for the rk3308

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Add the clock tree definition for the new RK3308 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Finley Xiao
2019-09-03 19:59:47 +08:00
committed by Heiko Stuebner
parent efb7740f25
commit ac68dfd3c4
3 changed files with 969 additions and 0 deletions
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1
drivers/clk/rockchip/Makefile
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@@ -20,6 +20,7 @@ obj-y += clk-rk3128.o
obj-y += clk-rk3188.o
obj-y += clk-rk3228.o
obj-y += clk-rk3288.o
obj-y += clk-rk3308.o
obj-y += clk-rk3328.o
obj-y += clk-rk3368.o
obj-y += clk-rk3399.o

955
drivers/clk/rockchip/clk-rk3308.c Normal file
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File diff suppressed because it is too large Load Diff

13
drivers/clk/rockchip/clk.h
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@@ -121,6 +121,19 @@ struct clk;
#define RK3288_EMMC_CON0 0x218
#define RK3288_EMMC_CON1 0x21c
#define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
#define RK3308_GLB_SRST_FST 0xb8
#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
#define RK3308_MODE_CON 0xa0
#define RK3308_SDMMC_CON0 0x480
#define RK3308_SDMMC_CON1 0x484
#define RK3308_SDIO_CON0 0x488
#define RK3308_SDIO_CON1 0x48c
#define RK3308_EMMC_CON0 0x490
#define RK3308_EMMC_CON1 0x494
#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)