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drm/nouveau/disp: add common channel class handling

Browse Source 
Replaces a bunch of unnecessarily duplicated boilerplate in per-chipset
code with a simpler, common, implementation.

Channel "awaken" notify code is completely gone for now.  KMS has never
made use of it so far, and event notify handling is about to be changed
in general anyway.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ben Skeggs
2022-06-01 20:46:29 +10:00
committed by Dave Airlie
parent 7bcf89eed4
commit 889fcbe949
42 changed files with 457 additions and 828 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/nouveau/dispnv50/base507c.c
+3 -14
View File
@@ -21,8 +21,7 @@
*/
#include "base.h"
#include <nvif/cl507c.h>
#include <nvif/event.h>
#include <nvif/if0014.h>
#include <nvif/push507c.h>
#include <nvif/timer.h>
@@ -306,8 +305,8 @@ base507c_new_(const struct nv50_wndw_func *func, const u32 *format,
struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data,
struct nv50_wndw **pwndw)
{
struct nv50_disp_base_channel_dma_v0 args = {
.head = head,
struct nvif_disp_chan_v0 args = {
.id = head,
};
struct nouveau_display *disp = nouveau_display(drm->dev);
struct nv50_disp *disp50 = nv50_disp(drm->dev);
@@ -328,16 +327,6 @@ base507c_new_(const struct nv50_wndw_func *func, const u32 *format,
return ret;
}
ret = nvif_notify_ctor(&wndw->wndw.base.user, "kmsBaseNtfy",
wndw->notify.func, false,
NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
&(struct nvif_notify_uevent_req) {},
sizeof(struct nvif_notify_uevent_req),
sizeof(struct nvif_notify_uevent_rep),
&wndw->notify);
if (ret)
return ret;
wndw->ntfy = NV50_DISP_BASE_NTFY(wndw->id);
wndw->sema = NV50_DISP_BASE_SEM0(wndw->id);
wndw->data = 0x00000000;
drivers/gpu/drm/nouveau/dispnv50/core507d.c
+2 -2
View File
@@ -22,7 +22,7 @@
#include "core.h"
#include "head.h"
#include <nvif/cl507d.h>
#include <nvif/if0014.h>
#include <nvif/push507c.h>
#include <nvif/timer.h>
@@ -157,7 +157,7 @@ int
core507d_new_(const struct nv50_core_func *func, struct nouveau_drm *drm,
s32 oclass, struct nv50_core **pcore)
{
struct nv50_disp_core_channel_dma_v0 args = {};
struct nvif_disp_chan_v0 args = {};
struct nv50_disp *disp = nv50_disp(drm->dev);
struct nv50_core *core;
int ret;
drivers/gpu/drm/nouveau/dispnv50/curs507a.c
+3 -3
View File
@@ -23,7 +23,7 @@
#include "core.h"
#include "head.h"
#include <nvif/cl507a.h>
#include <nvif/if0014.h>
#include <nvif/timer.h>
#include <nvhw/class/cl507a.h>
@@ -150,8 +150,8 @@ curs507a_new_(const struct nv50_wimm_func *func, struct nouveau_drm *drm,
int head, s32 oclass, u32 interlock_data,
struct nv50_wndw **pwndw)
{
struct nv50_disp_cursor_v0 args = {
.head = head,
struct nvif_disp_chan_v0 args = {
.id = head,
};
struct nv50_disp *disp = nv50_disp(drm->dev);
struct nv50_wndw *wndw;
drivers/gpu/drm/nouveau/dispnv50/disp.c
+2 -2
View File
@@ -48,8 +48,8 @@
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include <nvif/cl5070.h>
#include <nvif/cl507d.h>
#include <nvif/event.h>
#include <nvif/if0014.h>
#include <nvif/timer.h>
#include <nvhw/class/cl507c.h>
@@ -231,7 +231,7 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
struct nv50_dmac *dmac)
{
struct nouveau_cli *cli = (void *)device->object.client;
struct nv50_disp_core_channel_dma_v0 *args = data;
struct nvif_disp_chan_v0 *args = data;
u8 type = NVIF_MEM_COHERENT;
int ret;
drivers/gpu/drm/nouveau/dispnv50/oimm507b.c
+3 -3
View File
@@ -21,14 +21,14 @@
*/
#include "oimm.h"
#include <nvif/cl507b.h>
#include <nvif/if0014.h>
static int
oimm507b_init_(const struct nv50_wimm_func *func, struct nouveau_drm *drm,
s32 oclass, struct nv50_wndw *wndw)
{
struct nv50_disp_overlay_v0 args = {
.head = wndw->id,
struct nvif_disp_chan_v0 args = {
.id = wndw->id,
};
struct nv50_disp *disp = nv50_disp(drm->dev);
int ret;
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
+3 -14
View File
@@ -26,8 +26,7 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_plane_helper.h>
#include <nvif/cl507e.h>
#include <nvif/event.h>
#include <nvif/if0014.h>
#include <nvif/push507c.h>
#include <nvhw/class/cl507e.h>
@@ -147,8 +146,8 @@ ovly507e_new_(const struct nv50_wndw_func *func, const u32 *format,
struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data,
struct nv50_wndw **pwndw)
{
struct nv50_disp_overlay_channel_dma_v0 args = {
.head = head,
struct nvif_disp_chan_v0 args = {
.id = head,
};
struct nv50_disp *disp = nv50_disp(drm->dev);
struct nv50_wndw *wndw;
@@ -169,16 +168,6 @@ ovly507e_new_(const struct nv50_wndw_func *func, const u32 *format,
return ret;
}
ret = nvif_notify_ctor(&wndw->wndw.base.user, "kmsOvlyNtfy",
wndw->notify.func, false,
NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT,
&(struct nvif_notify_uevent_req) {},
sizeof(struct nvif_notify_uevent_req),
sizeof(struct nvif_notify_uevent_rep),
&wndw->notify);
if (ret)
return ret;
wndw->ntfy = NV50_DISP_OVLY_NTFY(wndw->id);
wndw->sema = NV50_DISP_OVLY_SEM0(wndw->id);
wndw->data = 0x00000000;
drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c
+3 -4
View File
@@ -23,7 +23,7 @@
#include "atom.h"
#include "wndw.h"
#include <nvif/clc37b.h>
#include <nvif/if0014.h>
#include <nvif/pushc37b.h>
#include <nvhw/class/clc37b.h>
@@ -68,9 +68,8 @@ static int
wimmc37b_init_(const struct nv50_wimm_func *func, struct nouveau_drm *drm,
s32 oclass, struct nv50_wndw *wndw)
{
struct nvc37b_window_imm_channel_dma_v0 args = {
.pushbuf = 0xb0007b00 | wndw->id,
.index = wndw->id,
struct nvif_disp_chan_v0 args = {
.id = wndw->id,
};
struct nv50_disp *disp = nv50_disp(drm->dev);
int ret;
drivers/gpu/drm/nouveau/dispnv50/wndw.c
-9
View File
@@ -644,7 +644,6 @@ nv50_wndw_destroy(struct drm_plane *plane)
nv50_wndw_ctxdma_del(ctxdma);
}
nvif_notify_dtor(&wndw->notify);
nv50_dmac_destroy(&wndw->wimm);
nv50_dmac_destroy(&wndw->wndw);
@@ -688,12 +687,6 @@ nv50_wndw = {
.format_mod_supported = nv50_plane_format_mod_supported,
};
static int
nv50_wndw_notify(struct nvif_notify *notify)
{
return NVIF_NOTIFY_KEEP;
}
static const u64 nv50_cursor_format_modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_INVALID,
@@ -747,8 +740,6 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
return ret;
}
wndw->notify.func = nv50_wndw_notify;
if (wndw->func->blend_set) {
ret = drm_plane_create_zpos_property(&wndw->plane,
nv50_wndw_zpos_default(&wndw->plane), 0, 254);
drivers/gpu/drm/nouveau/dispnv50/wndw.h
-3
View File
@@ -5,8 +5,6 @@
#include "atom.h"
#include "lut.h"
#include <nvif/notify.h>
struct nv50_wndw_ctxdma {
struct list_head head;
struct nvif_object object;
@@ -30,7 +28,6 @@ struct nv50_wndw {
struct nv50_dmac wndw;
struct nv50_dmac wimm;
struct nvif_notify notify;
u16 ntfy;
u16 sema;
u32 data;
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
+3 -4
View File
@@ -26,7 +26,7 @@
#include <drm/drm_plane_helper.h>
#include <nouveau_bo.h>
#include <nvif/clc37e.h>
#include <nvif/if0014.h>
#include <nvif/pushc37b.h>
#include <nvhw/class/clc37e.h>
@@ -351,9 +351,8 @@ wndwc37e_new_(const struct nv50_wndw_func *func, struct nouveau_drm *drm,
enum drm_plane_type type, int index, s32 oclass, u32 heads,
struct nv50_wndw **pwndw)
{
struct nvc37e_window_channel_dma_v0 args = {
.pushbuf = 0xb0007e00 | index,
.index = index,
struct nvif_disp_chan_v0 args = {
.id = index,
};
struct nv50_disp *disp = nv50_disp(drm->dev);
struct nv50_wndw *wndw;
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
-1
View File
@@ -26,7 +26,6 @@
#include <drm/drm_plane_helper.h>
#include <nouveau_bo.h>
#include <nvif/clc37e.h>
#include <nvif/pushc37b.h>
#include <nvhw/class/clc57e.h>
drivers/gpu/drm/nouveau/include/nvif/cl507a.h
-12
View File
@@ -1,12 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507A_H__
#define __NVIF_CL507A_H__
struct nv50_disp_cursor_v0 {
__u8 version;
__u8 head;
__u8 pad02[6];
};
#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
#endif
drivers/gpu/drm/nouveau/include/nvif/cl507b.h
-12
View File
@@ -1,12 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507B_H__
#define __NVIF_CL507B_H__
struct nv50_disp_overlay_v0 {
__u8 version;
__u8 head;
__u8 pad02[6];
};
#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
#endif
drivers/gpu/drm/nouveau/include/nvif/cl507c.h
-13
View File
@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507C_H__
#define __NVIF_CL507C_H__
struct nv50_disp_base_channel_dma_v0 {
__u8 version;
__u8 head;
__u8 pad02[6];
__u64 pushbuf;
};
#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
#endif
drivers/gpu/drm/nouveau/include/nvif/cl507d.h
-12
View File
@@ -1,12 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507D_H__
#define __NVIF_CL507D_H__
struct nv50_disp_core_channel_dma_v0 {
__u8 version;
__u8 pad01[7];
__u64 pushbuf;
};
#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
#endif
drivers/gpu/drm/nouveau/include/nvif/cl507e.h
-13
View File
@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CL507E_H__
#define __NVIF_CL507E_H__
struct nv50_disp_overlay_channel_dma_v0 {
__u8 version;
__u8 head;
__u8 pad02[6];
__u64 pushbuf;
};
#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
#endif
drivers/gpu/drm/nouveau/include/nvif/class.h
+48 -47
View File
@@ -33,6 +33,7 @@
#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
#define NVIF_CLASS_DISP /* if0010.h */ 0x80000010
#define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014
/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_NULL_CLASS 0x00000030
@@ -98,59 +99,59 @@
#define NV74_VP2 0x00007476
#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
#define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a
#define TU102_DISP_CURSOR /* cl507a.h */ 0x0000c57a
#define GA102_DISP_CURSOR /* cl507a.h */ 0x0000c67a
#define NV50_DISP_CURSOR /* if0014.h */ 0x0000507a
#define G82_DISP_CURSOR /* if0014.h */ 0x0000827a
#define GT214_DISP_CURSOR /* if0014.h */ 0x0000857a
#define GF110_DISP_CURSOR /* if0014.h */ 0x0000907a
#define GK104_DISP_CURSOR /* if0014.h */ 0x0000917a
#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a
#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a
#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a
#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b
#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b
#define GT214_DISP_OVERLAY /* if0014.h */ 0x0000857b
#define GF110_DISP_OVERLAY /* if0014.h */ 0x0000907b
#define GK104_DISP_OVERLAY /* if0014.h */ 0x0000917b
#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b
#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b
#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c67b
#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b
#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b
#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b
#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c
#define GT200_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000837c
#define GT214_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000857c
#define GF110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000907c
#define GK104_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000917c
#define GK110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000927c
#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
#define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
#define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
#define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
#define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d
#define TU102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d
#define GA102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c67d
#define NV50_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000507d
#define G82_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000827d
#define GT200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000837d
#define GT214_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000857d
#define GT206_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000887d
#define GF110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000907d
#define GK104_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000917d
#define GK110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000927d
#define GM107_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000947d
#define GM200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000957d
#define GP100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000977d
#define GP102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000987d
#define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d
#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
#define GT200_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000837e
#define GT214_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000857e
#define GF110_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000907e
#define GK104_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000917e
#define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e
#define TU102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e
#define GA102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c67e
#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e
#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e
#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e
#define NV50_TESLA 0x00005097
#define G82_TESLA 0x00008297
drivers/gpu/drm/nouveau/include/nvif/clc37b.h
-11
View File
@@ -1,11 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLC37B_H__
#define __NVIF_CLC37B_H__
struct nvc37b_window_imm_channel_dma_v0 {
__u8 version;
__u8 index;
__u8 pad02[6];
__u64 pushbuf;
};
#endif
drivers/gpu/drm/nouveau/include/nvif/clc37e.h
-13
View File
@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_CLC37E_H__
#define __NVIF_CLC37E_H__
struct nvc37e_window_channel_dma_v0 {
__u8 version;
__u8 index;
__u8 pad02[6];
__u64 pushbuf;
};
#define NVC37E_WINDOW_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
#endif
drivers/gpu/drm/nouveau/include/nvif/if0014.h
+13
View File
@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0014_H__
#define __NVIF_IF0014_H__
union nvif_disp_chan_args {
struct nvif_disp_chan_v0 {
__u8 version;
__u8 id;
__u8 pad02[6];
__u64 pushbuf;
} v0;
};
#endif

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