mirror of
https://github.com/ukui/kernel.git
synced 2026-03-09 10:07:04 -07:00
Merge branch 'from-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
Patches for 4.16 that are dependent on patches sent to 4.15-rc. These are small clean ups for the vmw_pvrdma and i40iw drivers. * 'from-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git: RDMA/vmw_pvrdma: Remove usage of BIT() from UAPI header RDMA/vmw_pvrdma: Use refcount_t instead of atomic_t RDMA/vmw_pvrdma: Use more specific sizeof in kcalloc RDMA/vmw_pvrdma: Clarify QP and CQ is_kernel logic RDMA/vmw_pvrdma: Add UAR SRQ macros in ABI header file i40iw: Change accelerated flag to bool
This commit is contained in:
@@ -1,6 +1,6 @@
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menuconfig INFINIBAND
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tristate "InfiniBand support"
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depends on HAS_IOMEM
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depends on HAS_IOMEM && HAS_DMA
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depends on NET
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depends on INET
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depends on m || IPV6 != m
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@@ -801,6 +801,7 @@ struct rdma_cm_id *rdma_create_id(struct net *net,
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INIT_LIST_HEAD(&id_priv->mc_list);
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get_random_bytes(&id_priv->seq_num, sizeof id_priv->seq_num);
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id_priv->id.route.addr.dev_addr.net = get_net(net);
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id_priv->seq_num &= 0x00ffffff;
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return &id_priv->id;
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}
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@@ -4453,7 +4454,7 @@ out:
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return skb->len;
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}
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static const struct rdma_nl_cbs cma_cb_table[] = {
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static const struct rdma_nl_cbs cma_cb_table[RDMA_NL_RDMA_CM_NUM_OPS] = {
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[RDMA_NL_RDMA_CM_ID_STATS] = { .dump = cma_get_id_stats},
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};
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@@ -1136,7 +1136,7 @@ struct net_device *ib_get_net_dev_by_params(struct ib_device *dev,
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}
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EXPORT_SYMBOL(ib_get_net_dev_by_params);
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static const struct rdma_nl_cbs ibnl_ls_cb_table[] = {
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static const struct rdma_nl_cbs ibnl_ls_cb_table[RDMA_NL_LS_NUM_OPS] = {
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[RDMA_NL_LS_OP_RESOLVE] = {
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.doit = ib_nl_handle_resolve_resp,
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.flags = RDMA_NL_ADMIN_PERM,
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@@ -1243,5 +1243,5 @@ static void __exit ib_core_cleanup(void)
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MODULE_ALIAS_RDMA_NETLINK(RDMA_NL_LS, 4);
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module_init(ib_core_init);
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subsys_initcall(ib_core_init);
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module_exit(ib_core_cleanup);
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@@ -80,7 +80,7 @@ const char *__attribute_const__ iwcm_reject_msg(int reason)
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}
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EXPORT_SYMBOL(iwcm_reject_msg);
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static struct rdma_nl_cbs iwcm_nl_cb_table[] = {
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static struct rdma_nl_cbs iwcm_nl_cb_table[RDMA_NL_IWPM_NUM_OPS] = {
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[RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb},
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[RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb},
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[RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb},
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@@ -303,7 +303,7 @@ out: cb->args[0] = idx;
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return skb->len;
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}
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static const struct rdma_nl_cbs nldev_cb_table[] = {
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static const struct rdma_nl_cbs nldev_cb_table[RDMA_NLDEV_NUM_OPS] = {
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[RDMA_NLDEV_CMD_GET] = {
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.doit = nldev_get_doit,
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.dump = nldev_get_dumpit,
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@@ -386,6 +386,9 @@ int ib_open_shared_qp_security(struct ib_qp *qp, struct ib_device *dev)
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if (ret)
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return ret;
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if (!qp->qp_sec)
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return 0;
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mutex_lock(&real_qp->qp_sec->mutex);
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ret = check_qp_port_pkey_settings(real_qp->qp_sec->ports_pkeys,
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qp->qp_sec);
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@@ -417,8 +420,17 @@ void ib_close_shared_qp_security(struct ib_qp_security *sec)
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int ib_create_qp_security(struct ib_qp *qp, struct ib_device *dev)
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{
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u8 i = rdma_start_port(dev);
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bool is_ib = false;
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int ret;
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while (i <= rdma_end_port(dev) && !is_ib)
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is_ib = rdma_protocol_ib(dev, i++);
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/* If this isn't an IB device don't create the security context */
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if (!is_ib)
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return 0;
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qp->qp_sec = kzalloc(sizeof(*qp->qp_sec), GFP_KERNEL);
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if (!qp->qp_sec)
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return -ENOMEM;
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@@ -441,6 +453,10 @@ EXPORT_SYMBOL(ib_create_qp_security);
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void ib_destroy_qp_security_begin(struct ib_qp_security *sec)
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{
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/* Return if not IB */
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if (!sec)
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return;
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mutex_lock(&sec->mutex);
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/* Remove the QP from the lists so it won't get added to
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@@ -470,6 +486,10 @@ void ib_destroy_qp_security_abort(struct ib_qp_security *sec)
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int ret;
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int i;
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/* Return if not IB */
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if (!sec)
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return;
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/* If a concurrent cache update is in progress this
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* QP security could be marked for an error state
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* transition. Wait for this to complete.
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@@ -505,6 +525,10 @@ void ib_destroy_qp_security_end(struct ib_qp_security *sec)
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{
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int i;
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/* Return if not IB */
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if (!sec)
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return;
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/* If a concurrent cache update is occurring we must
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* wait until this QP security structure is processed
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* in the QP to error flow before destroying it because
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@@ -557,7 +581,7 @@ int ib_security_modify_qp(struct ib_qp *qp,
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{
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int ret = 0;
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struct ib_ports_pkeys *tmp_pps;
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struct ib_ports_pkeys *new_pps;
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struct ib_ports_pkeys *new_pps = NULL;
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struct ib_qp *real_qp = qp->real_qp;
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bool special_qp = (real_qp->qp_type == IB_QPT_SMI ||
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real_qp->qp_type == IB_QPT_GSI ||
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@@ -565,18 +589,27 @@ int ib_security_modify_qp(struct ib_qp *qp,
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bool pps_change = ((qp_attr_mask & (IB_QP_PKEY_INDEX | IB_QP_PORT)) ||
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(qp_attr_mask & IB_QP_ALT_PATH));
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WARN_ONCE((qp_attr_mask & IB_QP_PORT &&
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rdma_protocol_ib(real_qp->device, qp_attr->port_num) &&
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!real_qp->qp_sec),
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"%s: QP security is not initialized for IB QP: %d\n",
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__func__, real_qp->qp_num);
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/* The port/pkey settings are maintained only for the real QP. Open
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* handles on the real QP will be in the shared_qp_list. When
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* enforcing security on the real QP all the shared QPs will be
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* checked as well.
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*/
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if (pps_change && !special_qp) {
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if (pps_change && !special_qp && real_qp->qp_sec) {
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mutex_lock(&real_qp->qp_sec->mutex);
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new_pps = get_new_pps(real_qp,
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qp_attr,
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qp_attr_mask);
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if (!new_pps) {
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mutex_unlock(&real_qp->qp_sec->mutex);
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return -ENOMEM;
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}
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/* Add this QP to the lists for the new port
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* and pkey settings before checking for permission
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* in case there is a concurrent cache update
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@@ -600,7 +633,7 @@ int ib_security_modify_qp(struct ib_qp *qp,
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qp_attr_mask,
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udata);
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if (pps_change && !special_qp) {
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if (new_pps) {
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/* Clean up the lists and free the appropriate
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* ports_pkeys structure.
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*/
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@@ -630,6 +663,9 @@ static int ib_security_pkey_access(struct ib_device *dev,
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u16 pkey;
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int ret;
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if (!rdma_protocol_ib(dev, port_num))
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return 0;
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ret = ib_get_cached_pkey(dev, port_num, pkey_index, &pkey);
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if (ret)
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return ret;
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@@ -663,6 +699,9 @@ int ib_mad_agent_security_setup(struct ib_mad_agent *agent,
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{
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int ret;
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if (!rdma_protocol_ib(agent->device, agent->port_num))
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return 0;
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ret = security_ib_alloc_security(&agent->security);
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if (ret)
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return ret;
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@@ -688,6 +727,9 @@ int ib_mad_agent_security_setup(struct ib_mad_agent *agent,
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void ib_mad_agent_security_cleanup(struct ib_mad_agent *agent)
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{
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if (!rdma_protocol_ib(agent->device, agent->port_num))
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return;
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security_ib_free_security(agent->security);
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if (agent->lsm_nb_reg)
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unregister_lsm_notifier(&agent->lsm_nb);
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@@ -695,8 +737,14 @@ void ib_mad_agent_security_cleanup(struct ib_mad_agent *agent)
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int ib_mad_enforce_security(struct ib_mad_agent_private *map, u16 pkey_index)
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{
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if (map->agent.qp->qp_type == IB_QPT_SMI && !map->agent.smp_allowed)
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return -EACCES;
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if (!rdma_protocol_ib(map->agent.device, map->agent.port_num))
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return 0;
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if (map->agent.qp->qp_type == IB_QPT_SMI) {
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if (!map->agent.smp_allowed)
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return -EACCES;
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return 0;
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}
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return ib_security_pkey_access(map->agent.device,
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map->agent.port_num,
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@@ -1968,6 +1968,12 @@ static int modify_qp(struct ib_uverbs_file *file,
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goto release_qp;
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}
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if ((cmd->base.attr_mask & IB_QP_ALT_PATH) &&
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!rdma_is_port_valid(qp->device, cmd->base.alt_port_num)) {
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ret = -EINVAL;
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goto release_qp;
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}
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attr->qp_state = cmd->base.qp_state;
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attr->cur_qp_state = cmd->base.cur_qp_state;
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attr->path_mtu = cmd->base.path_mtu;
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@@ -2065,8 +2071,8 @@ int ib_uverbs_ex_modify_qp(struct ib_uverbs_file *file,
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return -EOPNOTSUPP;
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if (ucore->inlen > sizeof(cmd)) {
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if (ib_is_udata_cleared(ucore, sizeof(cmd),
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ucore->inlen - sizeof(cmd)))
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if (!ib_is_udata_cleared(ucore, sizeof(cmd),
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ucore->inlen - sizeof(cmd)))
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return -EOPNOTSUPP;
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}
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@@ -1439,7 +1439,8 @@ int ib_close_qp(struct ib_qp *qp)
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spin_unlock_irqrestore(&real_qp->device->event_handler_lock, flags);
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atomic_dec(&real_qp->usecnt);
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ib_close_shared_qp_security(qp->qp_sec);
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if (qp->qp_sec)
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ib_close_shared_qp_security(qp->qp_sec);
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kfree(qp);
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return 0;
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@@ -395,6 +395,11 @@ next_cqe:
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static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq)
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{
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if (DRAIN_CQE(cqe)) {
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WARN_ONCE(1, "Unexpected DRAIN CQE qp id %u!\n", wq->sq.qid);
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return 0;
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}
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if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
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return 0;
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@@ -489,7 +494,7 @@ static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
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/*
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* Special cqe for drain WR completions...
|
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*/
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if (CQE_OPCODE(hw_cqe) == C4IW_DRAIN_OPCODE) {
|
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if (DRAIN_CQE(hw_cqe)) {
|
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*cookie = CQE_DRAIN_COOKIE(hw_cqe);
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||||
*cqe = *hw_cqe;
|
||||
goto skip_cqe;
|
||||
@@ -566,10 +571,10 @@ static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
|
||||
ret = -EAGAIN;
|
||||
goto skip_cqe;
|
||||
}
|
||||
if (unlikely((CQE_WRID_MSN(hw_cqe) != (wq->rq.msn)))) {
|
||||
if (unlikely(!CQE_STATUS(hw_cqe) &&
|
||||
CQE_WRID_MSN(hw_cqe) != wq->rq.msn)) {
|
||||
t4_set_wq_in_error(wq);
|
||||
hw_cqe->header |= htonl(CQE_STATUS_V(T4_ERR_MSN));
|
||||
goto proc_cqe;
|
||||
hw_cqe->header |= cpu_to_be32(CQE_STATUS_V(T4_ERR_MSN));
|
||||
}
|
||||
goto proc_cqe;
|
||||
}
|
||||
@@ -743,9 +748,6 @@ static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
|
||||
c4iw_invalidate_mr(qhp->rhp,
|
||||
CQE_WRID_FR_STAG(&cqe));
|
||||
break;
|
||||
case C4IW_DRAIN_OPCODE:
|
||||
wc->opcode = IB_WC_SEND;
|
||||
break;
|
||||
default:
|
||||
pr_err("Unexpected opcode %d in the CQE received for QPID=0x%0x\n",
|
||||
CQE_OPCODE(&cqe), CQE_QPID(&cqe));
|
||||
|
||||
@@ -693,8 +693,6 @@ static inline int to_ib_qp_state(int c4iw_qp_state)
|
||||
return IB_QPS_ERR;
|
||||
}
|
||||
|
||||
#define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
|
||||
|
||||
static inline u32 c4iw_ib_to_tpt_access(int a)
|
||||
{
|
||||
return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
|
||||
|
||||
@@ -790,21 +790,57 @@ static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
|
||||
static int ib_to_fw_opcode(int ib_opcode)
|
||||
{
|
||||
int opcode;
|
||||
|
||||
switch (ib_opcode) {
|
||||
case IB_WR_SEND_WITH_INV:
|
||||
opcode = FW_RI_SEND_WITH_INV;
|
||||
break;
|
||||
case IB_WR_SEND:
|
||||
opcode = FW_RI_SEND;
|
||||
break;
|
||||
case IB_WR_RDMA_WRITE:
|
||||
opcode = FW_RI_RDMA_WRITE;
|
||||
break;
|
||||
case IB_WR_RDMA_READ:
|
||||
case IB_WR_RDMA_READ_WITH_INV:
|
||||
opcode = FW_RI_READ_REQ;
|
||||
break;
|
||||
case IB_WR_REG_MR:
|
||||
opcode = FW_RI_FAST_REGISTER;
|
||||
break;
|
||||
case IB_WR_LOCAL_INV:
|
||||
opcode = FW_RI_LOCAL_INV;
|
||||
break;
|
||||
default:
|
||||
opcode = -EINVAL;
|
||||
}
|
||||
return opcode;
|
||||
}
|
||||
|
||||
static int complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
|
||||
{
|
||||
struct t4_cqe cqe = {};
|
||||
struct c4iw_cq *schp;
|
||||
unsigned long flag;
|
||||
struct t4_cq *cq;
|
||||
int opcode;
|
||||
|
||||
schp = to_c4iw_cq(qhp->ibqp.send_cq);
|
||||
cq = &schp->cq;
|
||||
|
||||
opcode = ib_to_fw_opcode(wr->opcode);
|
||||
if (opcode < 0)
|
||||
return opcode;
|
||||
|
||||
cqe.u.drain_cookie = wr->wr_id;
|
||||
cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
|
||||
CQE_OPCODE_V(C4IW_DRAIN_OPCODE) |
|
||||
CQE_OPCODE_V(opcode) |
|
||||
CQE_TYPE_V(1) |
|
||||
CQE_SWCQE_V(1) |
|
||||
CQE_DRAIN_V(1) |
|
||||
CQE_QPID_V(qhp->wq.sq.qid));
|
||||
|
||||
spin_lock_irqsave(&schp->lock, flag);
|
||||
@@ -819,6 +855,23 @@ static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
|
||||
schp->ibcq.cq_context);
|
||||
spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int complete_sq_drain_wrs(struct c4iw_qp *qhp, struct ib_send_wr *wr,
|
||||
struct ib_send_wr **bad_wr)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
while (wr) {
|
||||
ret = complete_sq_drain_wr(qhp, wr);
|
||||
if (ret) {
|
||||
*bad_wr = wr;
|
||||
break;
|
||||
}
|
||||
wr = wr->next;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
|
||||
@@ -833,9 +886,10 @@ static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
|
||||
|
||||
cqe.u.drain_cookie = wr->wr_id;
|
||||
cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
|
||||
CQE_OPCODE_V(C4IW_DRAIN_OPCODE) |
|
||||
CQE_OPCODE_V(FW_RI_SEND) |
|
||||
CQE_TYPE_V(0) |
|
||||
CQE_SWCQE_V(1) |
|
||||
CQE_DRAIN_V(1) |
|
||||
CQE_QPID_V(qhp->wq.sq.qid));
|
||||
|
||||
spin_lock_irqsave(&rchp->lock, flag);
|
||||
@@ -852,6 +906,14 @@ static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
|
||||
}
|
||||
}
|
||||
|
||||
static void complete_rq_drain_wrs(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
|
||||
{
|
||||
while (wr) {
|
||||
complete_rq_drain_wr(qhp, wr);
|
||||
wr = wr->next;
|
||||
}
|
||||
}
|
||||
|
||||
int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
|
||||
struct ib_send_wr **bad_wr)
|
||||
{
|
||||
@@ -868,9 +930,14 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
|
||||
|
||||
qhp = to_c4iw_qp(ibqp);
|
||||
spin_lock_irqsave(&qhp->lock, flag);
|
||||
if (t4_wq_in_error(&qhp->wq)) {
|
||||
|
||||
/*
|
||||
* If the qp has been flushed, then just insert a special
|
||||
* drain cqe.
|
||||
*/
|
||||
if (qhp->wq.flushed) {
|
||||
spin_unlock_irqrestore(&qhp->lock, flag);
|
||||
complete_sq_drain_wr(qhp, wr);
|
||||
err = complete_sq_drain_wrs(qhp, wr, bad_wr);
|
||||
return err;
|
||||
}
|
||||
num_wrs = t4_sq_avail(&qhp->wq);
|
||||
@@ -1011,9 +1078,14 @@ int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
|
||||
|
||||
qhp = to_c4iw_qp(ibqp);
|
||||
spin_lock_irqsave(&qhp->lock, flag);
|
||||
if (t4_wq_in_error(&qhp->wq)) {
|
||||
|
||||
/*
|
||||
* If the qp has been flushed, then just insert a special
|
||||
* drain cqe.
|
||||
*/
|
||||
if (qhp->wq.flushed) {
|
||||
spin_unlock_irqrestore(&qhp->lock, flag);
|
||||
complete_rq_drain_wr(qhp, wr);
|
||||
complete_rq_drain_wrs(qhp, wr);
|
||||
return err;
|
||||
}
|
||||
num_wrs = t4_rq_avail(&qhp->wq);
|
||||
@@ -1285,21 +1357,21 @@ static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
|
||||
spin_unlock_irqrestore(&rchp->lock, flag);
|
||||
|
||||
if (schp == rchp) {
|
||||
if (t4_clear_cq_armed(&rchp->cq) &&
|
||||
(rq_flushed || sq_flushed)) {
|
||||
if ((rq_flushed || sq_flushed) &&
|
||||
t4_clear_cq_armed(&rchp->cq)) {
|
||||
spin_lock_irqsave(&rchp->comp_handler_lock, flag);
|
||||
(*rchp->ibcq.comp_handler)(&rchp->ibcq,
|
||||
rchp->ibcq.cq_context);
|
||||
spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
|
||||
}
|
||||
} else {
|
||||
if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
|
||||
if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) {
|
||||
spin_lock_irqsave(&rchp->comp_handler_lock, flag);
|
||||
(*rchp->ibcq.comp_handler)(&rchp->ibcq,
|
||||
rchp->ibcq.cq_context);
|
||||
spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
|
||||
}
|
||||
if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
|
||||
if (sq_flushed && t4_clear_cq_armed(&schp->cq)) {
|
||||
spin_lock_irqsave(&schp->comp_handler_lock, flag);
|
||||
(*schp->ibcq.comp_handler)(&schp->ibcq,
|
||||
schp->ibcq.cq_context);
|
||||
|
||||
@@ -197,6 +197,11 @@ struct t4_cqe {
|
||||
#define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
|
||||
#define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
|
||||
|
||||
#define CQE_DRAIN_S 10
|
||||
#define CQE_DRAIN_M 0x1
|
||||
#define CQE_DRAIN_G(x) ((((x) >> CQE_DRAIN_S)) & CQE_DRAIN_M)
|
||||
#define CQE_DRAIN_V(x) ((x)<<CQE_DRAIN_S)
|
||||
|
||||
#define CQE_STATUS_S 5
|
||||
#define CQE_STATUS_M 0x1F
|
||||
#define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
|
||||
@@ -213,6 +218,7 @@ struct t4_cqe {
|
||||
#define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
|
||||
|
||||
#define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
|
||||
#define DRAIN_CQE(x) (CQE_DRAIN_G(be32_to_cpu((x)->header)))
|
||||
#define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
|
||||
#define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
|
||||
#define SQ_TYPE(x) (CQE_TYPE((x)))
|
||||
|
||||
@@ -1131,7 +1131,6 @@ struct hfi1_devdata {
|
||||
u16 pcie_lnkctl;
|
||||
u16 pcie_devctl2;
|
||||
u32 pci_msix0;
|
||||
u32 pci_lnkctl3;
|
||||
u32 pci_tph2;
|
||||
|
||||
/*
|
||||
|
||||
@@ -411,15 +411,12 @@ int restore_pci_variables(struct hfi1_devdata *dd)
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
|
||||
dd->pci_lnkctl3);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, dd->pci_tph2);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
|
||||
ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2,
|
||||
dd->pci_tph2);
|
||||
if (ret)
|
||||
goto error;
|
||||
}
|
||||
return 0;
|
||||
|
||||
error:
|
||||
@@ -469,15 +466,12 @@ int save_pci_variables(struct hfi1_devdata *dd)
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
|
||||
&dd->pci_lnkctl3);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
|
||||
ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2,
|
||||
&dd->pci_tph2);
|
||||
if (ret)
|
||||
goto error;
|
||||
}
|
||||
return 0;
|
||||
|
||||
error:
|
||||
|
||||
@@ -814,7 +814,7 @@ static inline void hfi1_make_rc_ack_16B(struct rvt_qp *qp,
|
||||
struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
|
||||
struct hfi1_16b_header *hdr = &opa_hdr->opah;
|
||||
struct ib_other_headers *ohdr;
|
||||
u32 bth0, bth1;
|
||||
u32 bth0, bth1 = 0;
|
||||
u16 len, pkey;
|
||||
u8 becn = !!is_fecn;
|
||||
u8 l4 = OPA_16B_L4_IB_LOCAL;
|
||||
|
||||
@@ -162,14 +162,10 @@ void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
|
||||
{
|
||||
int i;
|
||||
struct device *dev = hr_dev->dev;
|
||||
u32 bits_per_long = BITS_PER_LONG;
|
||||
|
||||
if (buf->nbufs == 1) {
|
||||
dma_free_coherent(dev, size, buf->direct.buf, buf->direct.map);
|
||||
} else {
|
||||
if (bits_per_long == 64 && buf->page_shift == PAGE_SHIFT)
|
||||
vunmap(buf->direct.buf);
|
||||
|
||||
for (i = 0; i < buf->nbufs; ++i)
|
||||
if (buf->page_list[i].buf)
|
||||
dma_free_coherent(dev, 1 << buf->page_shift,
|
||||
@@ -185,9 +181,7 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
|
||||
{
|
||||
int i = 0;
|
||||
dma_addr_t t;
|
||||
struct page **pages;
|
||||
struct device *dev = hr_dev->dev;
|
||||
u32 bits_per_long = BITS_PER_LONG;
|
||||
u32 page_size = 1 << page_shift;
|
||||
u32 order;
|
||||
|
||||
@@ -236,23 +230,6 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
|
||||
buf->page_list[i].map = t;
|
||||
memset(buf->page_list[i].buf, 0, page_size);
|
||||
}
|
||||
if (bits_per_long == 64 && page_shift == PAGE_SHIFT) {
|
||||
pages = kmalloc_array(buf->nbufs, sizeof(*pages),
|
||||
GFP_KERNEL);
|
||||
if (!pages)
|
||||
goto err_free;
|
||||
|
||||
for (i = 0; i < buf->nbufs; ++i)
|
||||
pages[i] = virt_to_page(buf->page_list[i].buf);
|
||||
|
||||
buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP,
|
||||
PAGE_KERNEL);
|
||||
kfree(pages);
|
||||
if (!buf->direct.buf)
|
||||
goto err_free;
|
||||
} else {
|
||||
buf->direct.buf = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -795,11 +795,9 @@ static inline struct hns_roce_qp
|
||||
|
||||
static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
|
||||
{
|
||||
u32 bits_per_long_val = BITS_PER_LONG;
|
||||
u32 page_size = 1 << buf->page_shift;
|
||||
|
||||
if ((bits_per_long_val == 64 && buf->page_shift == PAGE_SHIFT) ||
|
||||
buf->nbufs == 1)
|
||||
if (buf->nbufs == 1)
|
||||
return (char *)(buf->direct.buf) + offset;
|
||||
else
|
||||
return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
|
||||
|
||||
@@ -224,6 +224,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
|
||||
sg_init_table(chunk->mem, HNS_ROCE_HEM_CHUNK_LEN);
|
||||
chunk->npages = 0;
|
||||
chunk->nsg = 0;
|
||||
memset(chunk->buf, 0, sizeof(chunk->buf));
|
||||
list_add_tail(&chunk->list, &hem->chunk_list);
|
||||
}
|
||||
|
||||
@@ -240,8 +241,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
|
||||
if (!buf)
|
||||
goto fail;
|
||||
|
||||
sg_set_buf(mem, buf, PAGE_SIZE << order);
|
||||
WARN_ON(mem->offset);
|
||||
chunk->buf[chunk->npages] = buf;
|
||||
sg_dma_len(mem) = PAGE_SIZE << order;
|
||||
|
||||
++chunk->npages;
|
||||
@@ -267,8 +267,8 @@ void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
|
||||
list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) {
|
||||
for (i = 0; i < chunk->npages; ++i)
|
||||
dma_free_coherent(hr_dev->dev,
|
||||
chunk->mem[i].length,
|
||||
lowmem_page_address(sg_page(&chunk->mem[i])),
|
||||
sg_dma_len(&chunk->mem[i]),
|
||||
chunk->buf[i],
|
||||
sg_dma_address(&chunk->mem[i]));
|
||||
kfree(chunk);
|
||||
}
|
||||
@@ -722,11 +722,12 @@ void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
|
||||
struct hns_roce_hem_chunk *chunk;
|
||||
struct hns_roce_hem_mhop mhop;
|
||||
struct hns_roce_hem *hem;
|
||||
struct page *page = NULL;
|
||||
void *addr = NULL;
|
||||
unsigned long mhop_obj = obj;
|
||||
unsigned long obj_per_chunk;
|
||||
unsigned long idx_offset;
|
||||
int offset, dma_offset;
|
||||
int length;
|
||||
int i, j;
|
||||
u32 hem_idx = 0;
|
||||
|
||||
@@ -763,25 +764,25 @@ void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
|
||||
|
||||
list_for_each_entry(chunk, &hem->chunk_list, list) {
|
||||
for (i = 0; i < chunk->npages; ++i) {
|
||||
length = sg_dma_len(&chunk->mem[i]);
|
||||
if (dma_handle && dma_offset >= 0) {
|
||||
if (sg_dma_len(&chunk->mem[i]) >
|
||||
(u32)dma_offset)
|
||||
if (length > (u32)dma_offset)
|
||||
*dma_handle = sg_dma_address(
|
||||
&chunk->mem[i]) + dma_offset;
|
||||
dma_offset -= sg_dma_len(&chunk->mem[i]);
|
||||
dma_offset -= length;
|
||||
}
|
||||
|
||||
if (chunk->mem[i].length > (u32)offset) {
|
||||
page = sg_page(&chunk->mem[i]);
|
||||
if (length > (u32)offset) {
|
||||
addr = chunk->buf[i] + offset;
|
||||
goto out;
|
||||
}
|
||||
offset -= chunk->mem[i].length;
|
||||
offset -= length;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
mutex_unlock(&table->mutex);
|
||||
return page ? lowmem_page_address(page) + offset : NULL;
|
||||
return addr;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hns_roce_table_find);
|
||||
|
||||
|
||||
@@ -78,6 +78,7 @@ struct hns_roce_hem_chunk {
|
||||
int npages;
|
||||
int nsg;
|
||||
struct scatterlist mem[HNS_ROCE_HEM_CHUNK_LEN];
|
||||
void *buf[HNS_ROCE_HEM_CHUNK_LEN];
|
||||
};
|
||||
|
||||
struct hns_roce_hem {
|
||||
|
||||
@@ -1131,9 +1131,11 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
|
||||
{
|
||||
struct hns_roce_v2_mpt_entry *mpt_entry;
|
||||
struct scatterlist *sg;
|
||||
u64 page_addr;
|
||||
u64 *pages;
|
||||
int i, j;
|
||||
int len;
|
||||
int entry;
|
||||
int i;
|
||||
|
||||
mpt_entry = mb_buf;
|
||||
memset(mpt_entry, 0, sizeof(*mpt_entry));
|
||||
@@ -1191,14 +1193,20 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
|
||||
|
||||
i = 0;
|
||||
for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
|
||||
pages[i] = ((u64)sg_dma_address(sg)) >> 6;
|
||||
len = sg_dma_len(sg) >> PAGE_SHIFT;
|
||||
for (j = 0; j < len; ++j) {
|
||||
page_addr = sg_dma_address(sg) +
|
||||
(j << mr->umem->page_shift);
|
||||
pages[i] = page_addr >> 6;
|
||||
|
||||
/* Record the first 2 entry directly to MTPT table */
|
||||
if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
|
||||
break;
|
||||
i++;
|
||||
/* Record the first 2 entry directly to MTPT table */
|
||||
if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
|
||||
goto found;
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
found:
|
||||
mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
|
||||
roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
|
||||
V2_MPT_BYTE_56_PA0_H_S,
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user