mirror of
https://github.com/ukui/kernel.git
synced 2026-03-09 10:07:04 -07:00
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Olof Johansson: "Here's the first batch of fixes for this release cycle. Main diffstat here is the re-deletion of netx. I messed up and most likely didn't remove the files from the index when I test-merged this and saw conflicts, and from there on out 'git rerere' remembered the mistake and I missed checking it. Here it's done again as expected. Besides that: - A defconfig refresh + enabling of new drivers for u8500 - i.MX fixlets for i2c/SAI/pinmux - sleep.S build fix for Davinci - Broadcom devicetree build/warning fix" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: defconfig: u8500: Add new drivers ARM: defconfig: u8500: Refresh defconfig ARM: dts: bcm: bcm47094: add missing #cells for mdio-bus-mux ARM: davinci: fix sleep.S build error on ARMv4 arm64: dts: imx8mq: fix SAI compatible arm64: dts: imx8mm: Correct SAI3 RXC/TXFS pin's mux option #1 ARM: dts: imx6ul: fix clock frequency property name of I2C buses ARM: Delete netx a second time ARM: dts: imx7ulp: Fix usb-phy unit address format
This commit is contained in:
Linus Torvalds
@@ -1535,7 +1535,6 @@ config DEBUG_LL_INCLUDE
|
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DEBUG_IMX7D_UART
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default "debug/ks8695.S" if DEBUG_KS8695_UART
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default "debug/msm.S" if DEBUG_QCOM_UARTDM
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default "debug/netx.S" if DEBUG_NETX_UART
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default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
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default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
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default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
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@@ -1575,7 +1574,6 @@ config DEBUG_UART_8250
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config DEBUG_UART_PHYS
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hex "Physical base address of debug UART"
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default 0x00100a00 if DEBUG_NETX_UART
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default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
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default 0x01c28000 if DEBUG_SUNXI_UART0
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default 0x01c28400 if DEBUG_SUNXI_UART1
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@@ -1700,7 +1698,6 @@ config DEBUG_UART_PHYS
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DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
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DEBUG_LL_UART_EFM32 || \
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DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
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DEBUG_NETX_UART || \
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DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
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DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
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DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
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@@ -1717,7 +1714,6 @@ config DEBUG_UART_VIRT
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default 0xc881f000 if DEBUG_RV1108_UART2
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default 0xc8821000 if DEBUG_RV1108_UART1
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default 0xc8912000 if DEBUG_RV1108_UART0
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default 0xe0000a00 if DEBUG_NETX_UART
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default 0xe0010fe0 if ARCH_RPC
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default 0xf0000be0 if ARCH_EBSA110
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default 0xf0010000 if DEBUG_ASM9260_UART
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@@ -1822,7 +1818,6 @@ config DEBUG_UART_VIRT
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default DEBUG_UART_PHYS if !MMU
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depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
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DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
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DEBUG_NETX_UART || \
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DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
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DEBUG_S3C64XX_UART || \
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DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
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@@ -124,6 +124,9 @@
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};
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mdio-bus-mux {
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#address-cells = <1>;
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#size-cells = <0>;
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/* BIT(9) = 1 => external mdio */
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mdio_ext: mdio@200 {
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reg = <0x200>;
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@@ -112,7 +112,7 @@
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};
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&i2c2 {
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clock_frequency = <100000>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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@@ -156,7 +156,7 @@
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};
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&i2c2 {
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clock_frequency = <100000>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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@@ -148,7 +148,7 @@
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};
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&i2c2 {
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clock_frequency = <100000>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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@@ -43,7 +43,7 @@
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};
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&i2c2 {
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clock_frequency = <100000>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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@@ -43,7 +43,7 @@
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};
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&i2c2 {
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clock_frequency = <100000>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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@@ -58,7 +58,7 @@
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};
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&i2c3 {
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clock_frequency = <100000>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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@@ -186,7 +186,7 @@
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reg = <0x40330200 0x200>;
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};
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usbphy1: usb-phy@0x40350000 {
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usbphy1: usb-phy@40350000 {
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compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
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reg = <0x40350000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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@@ -4,17 +4,9 @@ CONFIG_NO_HZ_IDLE=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_KALLSYMS_ALL=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_ARCH_U8500=y
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CONFIG_MACH_HREFV60=y
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CONFIG_MACH_SNOWBALL=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=2
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CONFIG_PREEMPT=y
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CONFIG_AEABI=y
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CONFIG_HIGHMEM=y
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CONFIG_ARM_APPENDED_DTB=y
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CONFIG_ARM_ATAG_DTB_COMPAT=y
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@@ -25,6 +17,11 @@ CONFIG_CPU_IDLE=y
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CONFIG_ARM_U8500_CPUIDLE=y
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CONFIG_VFP=y
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CONFIG_NEON=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_CMA=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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@@ -47,7 +44,6 @@ CONFIG_SMSC911X=y
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CONFIG_SMSC_PHY=y
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CONFIG_CW1200=y
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CONFIG_CW1200_WLAN_SDIO=y
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# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
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CONFIG_INPUT_EVDEV=y
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# CONFIG_KEYBOARD_ATKBD is not set
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CONFIG_KEYBOARD_GPIO=y
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@@ -63,7 +59,6 @@ CONFIG_RMI4_CORE=y
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CONFIG_RMI4_I2C=y
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CONFIG_RMI4_F11=y
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# CONFIG_SERIO is not set
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CONFIG_VT_HW_CONSOLE_BINDING=y
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_AMBA_PL011=y
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CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
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@@ -72,6 +67,7 @@ CONFIG_SPI=y
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CONFIG_SPI_PL022=y
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CONFIG_GPIO_STMPE=y
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CONFIG_GPIO_TC3589X=y
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CONFIG_SENSORS_IIO_HWMON=y
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CONFIG_THERMAL=y
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CONFIG_CPU_THERMAL=y
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CONFIG_WATCHDOG=y
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@@ -79,6 +75,13 @@ CONFIG_MFD_STMPE=y
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CONFIG_MFD_TC3589X=y
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CONFIG_REGULATOR_AB8500=y
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CONFIG_REGULATOR_GPIO=y
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CONFIG_DRM=y
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CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
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CONFIG_DRM_LIMA=y
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CONFIG_DRM_MCDE=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_GENERIC=m
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CONFIG_LOGO=y
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CONFIG_SOUND=y
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CONFIG_SND=y
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CONFIG_SND_SOC=y
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@@ -87,6 +90,7 @@ CONFIG_SND_SOC_UX500_MACH_MOP500=y
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CONFIG_USB=y
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CONFIG_USB_MUSB_HDRC=y
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CONFIG_USB_MUSB_UX500=y
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CONFIG_MUSB_PIO_ONLY=y
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CONFIG_AB8500_USB=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_ETH=m
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@@ -103,6 +107,7 @@ CONFIG_RTC_DRV_AB8500=y
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CONFIG_RTC_DRV_PL031=y
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CONFIG_DMADEVICES=y
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CONFIG_STE_DMA40=y
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CONFIG_HWSPINLOCK=y
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CONFIG_HSEM_U8500=y
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CONFIG_IIO=y
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CONFIG_IIO_SW_TRIGGER=y
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@@ -126,20 +131,19 @@ CONFIG_NFS_FS=y
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CONFIG_ROOT_NFS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_CRYPTO_DEV_UX500=y
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CONFIG_CRYPTO_DEV_UX500_CRYP=y
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CONFIG_CRYPTO_DEV_UX500_HASH=y
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CONFIG_CRYPTO_DEV_UX500_DEBUG=y
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CONFIG_PRINTK_TIME=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_FS=y
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_DEBUG_KERNEL=y
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# CONFIG_SCHED_DEBUG is not set
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# CONFIG_DEBUG_PREEMPT is not set
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# CONFIG_FTRACE is not set
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CONFIG_DEBUG_USER=y
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CONFIG_CORESIGHT=y
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CONFIG_CORESIGHT_SINK_TPIU=y
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CONFIG_CORESIGHT_SINK_ETBV10=y
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CONFIG_CORESIGHT_SOURCE_ETM3X=y
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CONFIG_CRYPTO_DEV_UX500=y
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CONFIG_CRYPTO_DEV_UX500_CRYP=y
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CONFIG_CRYPTO_DEV_UX500_HASH=y
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CONFIG_CRYPTO_DEV_UX500_DEBUG=y
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@@ -24,6 +24,7 @@
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#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31)
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.text
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.arch armv5te
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/*
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* Move DaVinci into deep sleep state
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*
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@@ -1,22 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menu "NetX Implementations"
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depends on ARCH_NETX
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config MACH_NXDKN
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bool "Enable Hilscher nxdkn Eval Board support"
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help
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Board support for the Hilscher NetX Eval Board
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config MACH_NXDB500
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bool "Enable Hilscher nxdb500 Eval Board support"
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select ARM_AMBA
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help
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Board support for the Hilscher nxdb500 Eval Board
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config MACH_NXEB500HMI
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bool "Enable Hilscher nxeb500hmi Eval Board support"
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select ARM_AMBA
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help
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Board support for the Hilscher nxeb500hmi Eval Board
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endmenu
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@@ -1,13 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for the linux kernel.
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#
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# Object file lists.
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obj-y += time.o generic.o pfifo.o xc.o
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# Specific board support
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obj-$(CONFIG_MACH_NXDKN) += nxdkn.o
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obj-$(CONFIG_MACH_NXDB500) += nxdb500.o fb.o
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obj-$(CONFIG_MACH_NXEB500HMI) += nxeb500hmi.o fb.o
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@@ -1,3 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
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zreladdr-y += 0x80008000
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|
||||
@@ -1,65 +0,0 @@
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||||
// SPDX-License-Identifier: GPL-2.0-only
|
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/*
|
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* arch/arm/mach-netx/fb.c
|
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*
|
||||
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
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#include <linux/init.h>
|
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#include <linux/dma-mapping.h>
|
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#include <linux/amba/bus.h>
|
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#include <linux/amba/clcd.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/gfp.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#include <mach/netx-regs.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static struct clcd_panel *netx_panel;
|
||||
|
||||
void netx_clcd_enable(struct clcd_fb *fb)
|
||||
{
|
||||
}
|
||||
|
||||
int netx_clcd_setup(struct clcd_fb *fb)
|
||||
{
|
||||
dma_addr_t dma;
|
||||
|
||||
fb->panel = netx_panel;
|
||||
|
||||
fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, 1024 * 1024, &dma,
|
||||
GFP_KERNEL);
|
||||
if (!fb->fb.screen_base) {
|
||||
printk(KERN_ERR "CLCD: unable to map framebuffer\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
fb->fb.fix.smem_start = dma;
|
||||
fb->fb.fix.smem_len = 1024*1024;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
|
||||
{
|
||||
return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
|
||||
fb->fb.fix.smem_start, fb->fb.fix.smem_len);
|
||||
}
|
||||
|
||||
void netx_clcd_remove(struct clcd_fb *fb)
|
||||
{
|
||||
dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base,
|
||||
fb->fb.fix.smem_start);
|
||||
}
|
||||
|
||||
static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL);
|
||||
|
||||
int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
|
||||
{
|
||||
netx_panel = panel;
|
||||
fb_device.dev.platform_data = board;
|
||||
return amba_device_register(&fb_device, &iomem_resource);
|
||||
}
|
||||
@@ -1,12 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* arch/arm/mach-netx/fb.h
|
||||
*
|
||||
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*/
|
||||
|
||||
void netx_clcd_enable(struct clcd_fb *fb);
|
||||
int netx_clcd_setup(struct clcd_fb *fb);
|
||||
int netx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
|
||||
void netx_clcd_remove(struct clcd_fb *fb);
|
||||
int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel);
|
||||
@@ -1,182 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* arch/arm/mach-netx/generic.c
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/netx-regs.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
static struct map_desc netx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = NETX_IO_VIRT,
|
||||
.pfn = __phys_to_pfn(NETX_IO_PHYS),
|
||||
.length = NETX_IO_SIZE,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
void __init netx_map_io(void)
|
||||
{
|
||||
iotable_init(netx_io_desc, ARRAY_SIZE(netx_io_desc));
|
||||
}
|
||||
|
||||
static struct resource netx_rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x00101200,
|
||||
.end = 0x00101220,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device netx_rtc_device = {
|
||||
.name = "netx-rtc",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(netx_rtc_resources),
|
||||
.resource = netx_rtc_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&netx_rtc_device,
|
||||
};
|
||||
|
||||
#if 0
|
||||
#define DEBUG_IRQ(fmt...) printk(fmt)
|
||||
#else
|
||||
#define DEBUG_IRQ(fmt...) while (0) {}
|
||||
#endif
|
||||
|
||||
static void netx_hif_demux_handler(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
|
||||
unsigned int stat;
|
||||
|
||||
stat = ((readl(NETX_DPMAS_INT_EN) &
|
||||
readl(NETX_DPMAS_INT_STAT)) >> 24) & 0x1f;
|
||||
|
||||
while (stat) {
|
||||
if (stat & 1) {
|
||||
DEBUG_IRQ("handling irq %d\n", irq);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
irq++;
|
||||
stat >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
netx_hif_irq_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
unsigned int val, irq;
|
||||
|
||||
val = readl(NETX_DPMAS_IF_CONF1);
|
||||
|
||||
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_RISING) {
|
||||
DEBUG_IRQ("rising edges\n");
|
||||
val |= (1 << 26) << irq;
|
||||
}
|
||||
if (type & IRQ_TYPE_EDGE_FALLING) {
|
||||
DEBUG_IRQ("falling edges\n");
|
||||
val &= ~((1 << 26) << irq);
|
||||
}
|
||||
if (type & IRQ_TYPE_LEVEL_LOW) {
|
||||
DEBUG_IRQ("low level\n");
|
||||
val &= ~((1 << 26) << irq);
|
||||
}
|
||||
if (type & IRQ_TYPE_LEVEL_HIGH) {
|
||||
DEBUG_IRQ("high level\n");
|
||||
val |= (1 << 26) << irq;
|
||||
}
|
||||
|
||||
writel(val, NETX_DPMAS_IF_CONF1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
netx_hif_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, irq;
|
||||
|
||||
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
|
||||
writel((1 << 24) << irq, NETX_DPMAS_INT_STAT);
|
||||
|
||||
val = readl(NETX_DPMAS_INT_EN);
|
||||
val &= ~((1 << 24) << irq);
|
||||
writel(val, NETX_DPMAS_INT_EN);
|
||||
|
||||
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
|
||||
}
|
||||
|
||||
static void
|
||||
netx_hif_mask_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, irq;
|
||||
|
||||
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
|
||||
val = readl(NETX_DPMAS_INT_EN);
|
||||
val &= ~((1 << 24) << irq);
|
||||
writel(val, NETX_DPMAS_INT_EN);
|
||||
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
|
||||
}
|
||||
|
||||
static void
|
||||
netx_hif_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, irq;
|
||||
|
||||
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
|
||||
val = readl(NETX_DPMAS_INT_EN);
|
||||
val |= (1 << 24) << irq;
|
||||
writel(val, NETX_DPMAS_INT_EN);
|
||||
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
|
||||
}
|
||||
|
||||
static struct irq_chip netx_hif_chip = {
|
||||
.irq_ack = netx_hif_ack_irq,
|
||||
.irq_mask = netx_hif_mask_irq,
|
||||
.irq_unmask = netx_hif_unmask_irq,
|
||||
.irq_set_type = netx_hif_irq_type,
|
||||
};
|
||||
|
||||
void __init netx_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
vic_init(io_p2v(NETX_PA_VIC), NETX_IRQ_VIC_START, ~0, 0);
|
||||
|
||||
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
|
||||
irq_set_chip_and_handler(irq, &netx_hif_chip,
|
||||
handle_level_irq);
|
||||
irq_clear_status_flags(irq, IRQ_NOREQUEST);
|
||||
}
|
||||
|
||||
writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
|
||||
irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
|
||||
}
|
||||
|
||||
static int __init netx_init(void)
|
||||
{
|
||||
return platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
subsys_initcall(netx_init);
|
||||
|
||||
void netx_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
|
||||
NETX_SYSTEM_RES_CR);
|
||||
}
|
||||
@@ -1,14 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* arch/arm/mach-netx/generic.h
|
||||
*
|
||||
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*/
|
||||
|
||||
#include <linux/reboot.h>
|
||||
|
||||
extern void __init netx_map_io(void);
|
||||
extern void __init netx_init_irq(void);
|
||||
extern void netx_restart(enum reboot_mode, const char *);
|
||||
|
||||
extern void netx_timer_init(void);
|
||||
@@ -1,27 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* arch/arm/mach-netx/include/mach/hardware.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*/
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#define NETX_IO_PHYS 0x00100000
|
||||
#define NETX_IO_VIRT 0xe0000000
|
||||
#define NETX_IO_SIZE 0x00100000
|
||||
|
||||
#define SRAM_INTERNAL_PHYS_0 0x00000
|
||||
#define SRAM_INTERNAL_PHYS_1 0x08000
|
||||
#define SRAM_INTERNAL_PHYS_2 0x10000
|
||||
#define SRAM_INTERNAL_PHYS_3 0x18000
|
||||
#define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000)
|
||||
|
||||
#define XPEC_MEM_SIZE 0x4000
|
||||
#define XMAC_MEM_SIZE 0x1000
|
||||
#define SRAM_MEM_SIZE 0x8000
|
||||
|
||||
#define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
|
||||
#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
|
||||
|
||||
#endif
|
||||
@@ -1,58 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* arch/arm/mach-netx/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*/
|
||||
|
||||
#define NETX_IRQ_VIC_START 64
|
||||
#define NETX_IRQ_SOFTINT (NETX_IRQ_VIC_START + 0)
|
||||
#define NETX_IRQ_TIMER0 (NETX_IRQ_VIC_START + 1)
|
||||
#define NETX_IRQ_TIMER1 (NETX_IRQ_VIC_START + 2)
|
||||
#define NETX_IRQ_TIMER2 (NETX_IRQ_VIC_START + 3)
|
||||
#define NETX_IRQ_SYSTIME_NS (NETX_IRQ_VIC_START + 4)
|
||||
#define NETX_IRQ_SYSTIME_S (NETX_IRQ_VIC_START + 5)
|
||||
#define NETX_IRQ_GPIO_15 (NETX_IRQ_VIC_START + 6)
|
||||
#define NETX_IRQ_WATCHDOG (NETX_IRQ_VIC_START + 7)
|
||||
#define NETX_IRQ_UART0 (NETX_IRQ_VIC_START + 8)
|
||||
#define NETX_IRQ_UART1 (NETX_IRQ_VIC_START + 9)
|
||||
#define NETX_IRQ_UART2 (NETX_IRQ_VIC_START + 10)
|
||||
#define NETX_IRQ_USB (NETX_IRQ_VIC_START + 11)
|
||||
#define NETX_IRQ_SPI (NETX_IRQ_VIC_START + 12)
|
||||
#define NETX_IRQ_I2C (NETX_IRQ_VIC_START + 13)
|
||||
#define NETX_IRQ_LCD (NETX_IRQ_VIC_START + 14)
|
||||
#define NETX_IRQ_HIF (NETX_IRQ_VIC_START + 15)
|
||||
#define NETX_IRQ_GPIO_0_14 (NETX_IRQ_VIC_START + 16)
|
||||
#define NETX_IRQ_XPEC0 (NETX_IRQ_VIC_START + 17)
|
||||
#define NETX_IRQ_XPEC1 (NETX_IRQ_VIC_START + 18)
|
||||
#define NETX_IRQ_XPEC2 (NETX_IRQ_VIC_START + 19)
|
||||
#define NETX_IRQ_XPEC3 (NETX_IRQ_VIC_START + 20)
|
||||
#define NETX_IRQ_XPEC(no) (NETX_IRQ_VIC_START + 17 + (no))
|
||||
#define NETX_IRQ_MSYNC0 (NETX_IRQ_VIC_START + 21)
|
||||
#define NETX_IRQ_MSYNC1 (NETX_IRQ_VIC_START + 22)
|
||||
#define NETX_IRQ_MSYNC2 (NETX_IRQ_VIC_START + 23)
|
||||
#define NETX_IRQ_MSYNC3 (NETX_IRQ_VIC_START + 24)
|
||||
#define NETX_IRQ_IRQ_PHY (NETX_IRQ_VIC_START + 25)
|
||||
#define NETX_IRQ_ISO_AREA (NETX_IRQ_VIC_START + 26)
|
||||
/* int 27 is reserved */
|
||||
/* int 28 is reserved */
|
||||
#define NETX_IRQ_TIMER3 (NETX_IRQ_VIC_START + 29)
|
||||
#define NETX_IRQ_TIMER4 (NETX_IRQ_VIC_START + 30)
|
||||
/* int 31 is reserved */
|
||||
|
||||
#define NETX_IRQS (NETX_IRQ_VIC_START + 32)
|
||||
|
||||
/* for multiplexed irqs on gpio 0..14 */
|
||||
#define NETX_IRQ_GPIO(x) (NETX_IRQS + (x))
|
||||
#define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14)
|
||||
|
||||
/* Host interface interrupts */
|
||||
#define NETX_IRQ_HIF_CHAINED(x) (NETX_IRQ_GPIO_LAST + 1 + (x))
|
||||
#define NETX_IRQ_HIF_PIO35 NETX_IRQ_HIF_CHAINED(0)
|
||||
#define NETX_IRQ_HIF_PIO36 NETX_IRQ_HIF_CHAINED(1)
|
||||
#define NETX_IRQ_HIF_PIO40 NETX_IRQ_HIF_CHAINED(2)
|
||||
#define NETX_IRQ_HIF_PIO47 NETX_IRQ_HIF_CHAINED(3)
|
||||
#define NETX_IRQ_HIF_PIO72 NETX_IRQ_HIF_CHAINED(4)
|
||||
#define NETX_IRQ_HIF_LAST NETX_IRQ_HIF_CHAINED(4)
|
||||
|
||||
#define NR_IRQS (NETX_IRQ_HIF_LAST + 1)
|
||||
@@ -1,420 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* arch/arm/mach-netx/include/mach/netx-regs.h
|
||||
*
|
||||
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_NETX_REGS_H
|
||||
#define __ASM_ARCH_NETX_REGS_H
|
||||
|
||||
/* offsets relative to the beginning of the io space */
|
||||
#define NETX_OFS_SYSTEM 0x00000
|
||||
#define NETX_OFS_MEMCR 0x00100
|
||||
#define NETX_OFS_DPMAS 0x03000
|
||||
#define NETX_OFS_GPIO 0x00800
|
||||
#define NETX_OFS_PIO 0x00900
|
||||
#define NETX_OFS_UART0 0x00a00
|
||||
#define NETX_OFS_UART1 0x00a40
|
||||
#define NETX_OFS_UART2 0x00a80
|
||||
#define NETX_OF_MIIMU 0x00b00
|
||||
#define NETX_OFS_SPI 0x00c00
|
||||
#define NETX_OFS_I2C 0x00d00
|
||||
#define NETX_OFS_SYSTIME 0x01100
|
||||
#define NETX_OFS_RTC 0x01200
|
||||
#define NETX_OFS_EXTBUS 0x03600
|
||||
#define NETX_OFS_LCD 0x04000
|
||||
#define NETX_OFS_USB 0x20000
|
||||
#define NETX_OFS_XMAC0 0x60000
|
||||
#define NETX_OFS_XMAC1 0x61000
|
||||
#define NETX_OFS_XMAC2 0x62000
|
||||
#define NETX_OFS_XMAC3 0x63000
|
||||
#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000)
|
||||
#define NETX_OFS_PFIFO 0x64000
|
||||
#define NETX_OFS_XPEC0 0x70000
|
||||
#define NETX_OFS_XPEC1 0x74000
|
||||
#define NETX_OFS_XPEC2 0x78000
|
||||
#define NETX_OFS_XPEC3 0x7c000
|
||||
#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000)
|
||||
#define NETX_OFS_VIC 0xff000
|
||||
|
||||
/* physical addresses */
|
||||
#define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM)
|
||||
#define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR)
|
||||
#define NETX_PA_DPMAS (NETX_IO_PHYS + NETX_OFS_DPMAS)
|
||||
#define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO)
|
||||
#define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO)
|
||||
#define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0)
|
||||
#define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1)
|
||||
#define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2)
|
||||
#define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU)
|
||||
#define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI)
|
||||
#define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C)
|
||||
#define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME)
|
||||
#define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC)
|
||||
#define NETX_PA_EXTBUS (NETX_IO_PHYS + NETX_OFS_EXTBUS)
|
||||
#define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD)
|
||||
#define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB)
|
||||
#define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0)
|
||||
#define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1)
|
||||
#define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2)
|
||||
#define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3)
|
||||
#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no))
|
||||
#define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO)
|
||||
#define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0)
|
||||
#define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1)
|
||||
#define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2)
|
||||
#define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3)
|
||||
#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no))
|
||||
#define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC)
|
||||
|
||||
/* virtual addresses */
|
||||
#define NETX_VA_SYSTEM (NETX_IO_VIRT + NETX_OFS_SYSTEM)
|
||||
#define NETX_VA_MEMCR (NETX_IO_VIRT + NETX_OFS_MEMCR)
|
||||
#define NETX_VA_DPMAS (NETX_IO_VIRT + NETX_OFS_DPMAS)
|
||||
#define NETX_VA_GPIO (NETX_IO_VIRT + NETX_OFS_GPIO)
|
||||
#define NETX_VA_PIO (NETX_IO_VIRT + NETX_OFS_PIO)
|
||||
#define NETX_VA_UART0 (NETX_IO_VIRT + NETX_OFS_UART0)
|
||||
#define NETX_VA_UART1 (NETX_IO_VIRT + NETX_OFS_UART1)
|
||||
#define NETX_VA_UART2 (NETX_IO_VIRT + NETX_OFS_UART2)
|
||||
#define NETX_VA_MIIMU (NETX_IO_VIRT + NETX_OF_MIIMU)
|
||||
#define NETX_VA_SPI (NETX_IO_VIRT + NETX_OFS_SPI)
|
||||
#define NETX_VA_I2C (NETX_IO_VIRT + NETX_OFS_I2C)
|
||||
#define NETX_VA_SYSTIME (NETX_IO_VIRT + NETX_OFS_SYSTIME)
|
||||
#define NETX_VA_RTC (NETX_IO_VIRT + NETX_OFS_RTC)
|
||||
#define NETX_VA_EXTBUS (NETX_IO_VIRT + NETX_OFS_EXTBUS)
|
||||
#define NETX_VA_LCD (NETX_IO_VIRT + NETX_OFS_LCD)
|
||||
#define NETX_VA_USB (NETX_IO_VIRT + NETX_OFS_USB)
|
||||
#define NETX_VA_XMAC0 (NETX_IO_VIRT + NETX_OFS_XMAC0)
|
||||
#define NETX_VA_XMAC1 (NETX_IO_VIRT + NETX_OFS_XMAC1)
|
||||
#define NETX_VA_XMAC2 (NETX_IO_VIRT + NETX_OFS_XMAC2)
|
||||
#define NETX_VA_XMAC3 (NETX_IO_VIRT + NETX_OFS_XMAC3)
|
||||
#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no))
|
||||
#define NETX_VA_PFIFO (NETX_IO_VIRT + NETX_OFS_PFIFO)
|
||||
#define NETX_VA_XPEC0 (NETX_IO_VIRT + NETX_OFS_XPEC0)
|
||||
#define NETX_VA_XPEC1 (NETX_IO_VIRT + NETX_OFS_XPEC1)
|
||||
#define NETX_VA_XPEC2 (NETX_IO_VIRT + NETX_OFS_XPEC2)
|
||||
#define NETX_VA_XPEC3 (NETX_IO_VIRT + NETX_OFS_XPEC3)
|
||||
#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no))
|
||||
#define NETX_VA_VIC (NETX_IO_VIRT + NETX_OFS_VIC)
|
||||
|
||||
/*********************************
|
||||
* System functions *
|
||||
*********************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
|
||||
#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
|
||||
#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
|
||||
#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
|
||||
|
||||
/* FIXME: Docs are not consistent */
|
||||
/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */
|
||||
#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c)
|
||||
|
||||
#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10)
|
||||
#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34)
|
||||
#define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70)
|
||||
#define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200)
|
||||
#define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204)
|
||||
#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
|
||||
#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
|
||||
|
||||
/* Bits */
|
||||
#define NETX_SYSTEM_RES_CR_RSTIN (1<<0)
|
||||
#define NETX_SYSTEM_RES_CR_WDG_RES (1<<1)
|
||||
#define NETX_SYSTEM_RES_CR_HOST_RES (1<<2)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_RES (1<<3)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC0_RES (1<<4)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC1_RES (1<<5)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC2_RES (1<<6)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC3_RES (1<<7)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG0 (1<<20)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG1 (1<<21)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG2 (1<<22)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG3 (1<<23)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN (1<<24)
|
||||
#define NETX_SYSTEM_RES_CR_RSTOUT (1<<25)
|
||||
#define NETX_SYSTEM_RES_CR_EN_RSTOUT (1<<26)
|
||||
|
||||
#define PHY_CONTROL_RESET (1<<31)
|
||||
#define PHY_CONTROL_SIM_BYP (1<<30)
|
||||
#define PHY_CONTROL_CLK_XLATIN (1<<29)
|
||||
#define PHY_CONTROL_PHY1_EN (1<<21)
|
||||
#define PHY_CONTROL_PHY1_NP_MSG_CODE
|
||||
#define PHY_CONTROL_PHY1_AUTOMDIX (1<<17)
|
||||
#define PHY_CONTROL_PHY1_FIXMODE (1<<16)
|
||||
#define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13)
|
||||
#define PHY_CONTROL_PHY0_EN (1<<12)
|
||||
#define PHY_CONTROL_PHY0_NP_MSG_CODE
|
||||
#define PHY_CONTROL_PHY0_AUTOMDIX (1<<8)
|
||||
#define PHY_CONTROL_PHY0_FIXMODE (1<<7)
|
||||
#define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4)
|
||||
#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
|
||||
|
||||
#define PHY_MODE_10BASE_T_HALF 0
|
||||
#define PHY_MODE_10BASE_T_FULL 1
|
||||
#define PHY_MODE_100BASE_TX_FX_FULL 2
|
||||
#define PHY_MODE_100BASE_TX_FX_HALF 3
|
||||
#define PHY_MODE_100BASE_TX_HALF 4
|
||||
#define PHY_MODE_REPEATER 5
|
||||
#define PHY_MODE_POWER_DOWN 6
|
||||
#define PHY_MODE_ALL 7
|
||||
|
||||
/* Bits */
|
||||
#define VECT_CNTL_ENABLE (1 << 5)
|
||||
|
||||
/*******************************
|
||||
* GPIO and timer module *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
|
||||
#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
|
||||
#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
|
||||
#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
|
||||
#define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2))
|
||||
#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
|
||||
#define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc)
|
||||
#define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0)
|
||||
#define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4)
|
||||
#define NETX_GPIO_LINE NETX_GPIO_REG(0xc8)
|
||||
#define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0)
|
||||
|
||||
/* Bits */
|
||||
#define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0)
|
||||
#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1)
|
||||
#define NETX_GPIO_CFG_IOCFG_GP_UART (0x2)
|
||||
#define NETX_GPIO_CFG_INV (1<<2)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5)
|
||||
|
||||
#define NETX_GPIO_COUNTER_CTRL_RUN (1<<0)
|
||||
#define NETX_GPIO_COUNTER_CTRL_SYM (1<<1)
|
||||
#define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2)
|
||||
#define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3)
|
||||
#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4)
|
||||
#define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5)
|
||||
#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6)
|
||||
#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */
|
||||
|
||||
#define GPIO_BIT(gpio) (1<<(gpio))
|
||||
#define COUNTER_BIT(counter) ((1<<16)<<(counter))
|
||||
|
||||
/*******************************
|
||||
* PIO *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs))
|
||||
#define NETX_PIO_INPIO NETX_PIO_REG(0x0)
|
||||
#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
|
||||
#define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
|
||||
|
||||
/*******************************
|
||||
* MII Unit *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_MIIMU IOMEM(NETX_VA_MIIMU)
|
||||
|
||||
/* Bits */
|
||||
#define MIIMU_SNRDY (1<<0)
|
||||
#define MIIMU_PREAMBLE (1<<1)
|
||||
#define MIIMU_OPMODE_WRITE (1<<2)
|
||||
#define MIIMU_MDC_PERIOD (1<<3)
|
||||
#define MIIMU_PHY_NRES (1<<4)
|
||||
#define MIIMU_RTA (1<<5)
|
||||
#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)
|
||||
#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)
|
||||
#define MIIMU_DATA(data) (((data) & 0xffff) << 16)
|
||||
|
||||
/*******************************
|
||||
* xmac / xpec *
|
||||
*******************************/
|
||||
|
||||
/* XPEC register offsets relative to NETX_VA_XPEC(no) */
|
||||
#define NETX_XPEC_R0_OFS 0x00
|
||||
#define NETX_XPEC_R1_OFS 0x04
|
||||
#define NETX_XPEC_R2_OFS 0x08
|
||||
#define NETX_XPEC_R3_OFS 0x0c
|
||||
#define NETX_XPEC_R4_OFS 0x10
|
||||
#define NETX_XPEC_R5_OFS 0x14
|
||||
#define NETX_XPEC_R6_OFS 0x18
|
||||
#define NETX_XPEC_R7_OFS 0x1c
|
||||
#define NETX_XPEC_RANGE01_OFS 0x20
|
||||
#define NETX_XPEC_RANGE23_OFS 0x24
|
||||
#define NETX_XPEC_RANGE45_OFS 0x28
|
||||
#define NETX_XPEC_RANGE67_OFS 0x2c
|
||||
#define NETX_XPEC_PC_OFS 0x48
|
||||
#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))
|
||||
#define NETX_XPEC_IRQ_OFS 0x8c
|
||||
#define NETX_XPEC_SYSTIME_NS_OFS 0x90
|
||||
#define NETX_XPEC_FIFO_DATA_OFS 0x94
|
||||
#define NETX_XPEC_SYSTIME_S_OFS 0x98
|
||||
#define NETX_XPEC_ADC_OFS 0x9c
|
||||
#define NETX_XPEC_URX_COUNT_OFS 0x40
|
||||
#define NETX_XPEC_UTX_COUNT_OFS 0x44
|
||||
#define NETX_XPEC_PC_OFS 0x48
|
||||
#define NETX_XPEC_ZERO_OFS 0x4c
|
||||
#define NETX_XPEC_STATCFG_OFS 0x50
|
||||
#define NETX_XPEC_EC_MASKA_OFS 0x54
|
||||
#define NETX_XPEC_EC_MASKB_OFS 0x58
|
||||
#define NETX_XPEC_EC_MASK0_OFS 0x5c
|
||||
#define NETX_XPEC_EC_MASK8_OFS 0x7c
|
||||
#define NETX_XPEC_EC_MASK9_OFS 0x80
|
||||
#define NETX_XPEC_XPU_HOLD_PC_OFS 0x100
|
||||
#define NETX_XPEC_RAM_START_OFS 0x2000
|
||||
|
||||
/* Bits */
|
||||
#define XPU_HOLD_PC (1<<0)
|
||||
|
||||
/* XMAC register offsets relative to NETX_VA_XMAC(no) */
|
||||
#define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000
|
||||
#define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff
|
||||
#define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400
|
||||
#define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff
|
||||
#define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00
|
||||
#define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04
|
||||
#define NETX_XMAC_STATUS_SHARED0_OFS 0x840
|
||||
#define NETX_XMAC_CONFIG_SHARED0_OFS 0x844
|
||||
#define NETX_XMAC_STATUS_SHARED1_OFS 0x848
|
||||
#define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c
|
||||
#define NETX_XMAC_STATUS_SHARED2_OFS 0x850
|
||||
#define NETX_XMAC_CONFIG_SHARED2_OFS 0x854
|
||||
#define NETX_XMAC_STATUS_SHARED3_OFS 0x858
|
||||
#define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c
|
||||
|
||||
#define RPU_HOLD_PC (1<<15)
|
||||
#define TPU_HOLD_PC (1<<15)
|
||||
|
||||
/*******************************
|
||||
* Pointer FIFO *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs))
|
||||
#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
|
||||
#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
|
||||
#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
|
||||
#define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104)
|
||||
#define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108)
|
||||
#define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c)
|
||||
#define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110)
|
||||
#define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
|
||||
#define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2))
|
||||
|
||||
|
||||
/*******************************
|
||||
* Memory Controller *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs))
|
||||
#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
|
||||
#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
|
||||
#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
|
||||
#define NETX_MEMCR_SDRAM_MODE NETX_MEMCR_REG(0x48)
|
||||
#define NETX_MEMCR_SDRAM_EXT_MODE NETX_MEMCR_REG(0x4c)
|
||||
#define NETX_MEMCR_PRIO_TIMESLOT_CTRL NETX_MEMCR_REG(0x80)
|
||||
#define NETX_MEMCR_PRIO_ACCESS_CTRL NETX_MEMCR_REG(0x84)
|
||||
|
||||
/* Bits */
|
||||
#define NETX_MEMCR_SRAM_CTRL_WIDTHEXTMEM(x) (((x) & 0x3) << 24)
|
||||
#define NETX_MEMCR_SRAM_CTRL_WSPOSTPAUSEEXTMEM(x) (((x) & 0x3) << 16)
|
||||
#define NETX_MEMCR_SRAM_CTRL_WSPREPASEEXTMEM(x) (((x) & 0x3) << 8)
|
||||
#define NETX_MEMCR_SRAM_CTRL_WSEXTMEM(x) (((x) & 0x1f) << 0)
|
||||
|
||||
|
||||
/*******************************
|
||||
* Dual Port Memory *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs))
|
||||
#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
|
||||
#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
|
||||
#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
|
||||
#define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608)
|
||||
#define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c)
|
||||
#define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs))
|
||||
#define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */
|
||||
#define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624)
|
||||
#define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628)
|
||||
#define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */
|
||||
#define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634)
|
||||
#define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638)
|
||||
|
||||
/* Bits */
|
||||
#define NETX_DPMAS_INT_EN_GLB_EN (1<<31)
|
||||
#define NETX_DPMAS_INT_EN_MEM_LCK (1<<30)
|
||||
#define NETX_DPMAS_INT_EN_WDG (1<<29)
|
||||
#define NETX_DPMAS_INT_EN_PIO72 (1<<28)
|
||||
#define NETX_DPMAS_INT_EN_PIO47 (1<<27)
|
||||
#define NETX_DPMAS_INT_EN_PIO40 (1<<26)
|
||||
#define NETX_DPMAS_INT_EN_PIO36 (1<<25)
|
||||
#define NETX_DPMAS_INT_EN_PIO35 (1<<24)
|
||||
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS (1<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT (2<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_IO (4<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP (1<<14)
|
||||
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD (2<<14)
|
||||
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14)
|
||||
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30)
|
||||
|
||||
#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)
|
||||
#define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26)
|
||||
#define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23)
|
||||
#define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20)
|
||||
#define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17)
|
||||
#define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12)
|
||||
#define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7)
|
||||
#define NETX_EXT_CONFIG_WAIT_POL (1<<6)
|
||||
#define NETX_EXT_CONFIG_WAIT_EN (1<<5)
|
||||
#define NETX_EXT_CONFIG_NRD_MODE (1<<4)
|
||||
#define NETX_EXT_CONFIG_DS_MODE (1<<3)
|
||||
#define NETX_EXT_CONFIG_NWR_MODE (1<<2)
|
||||
#define NETX_EXT_CONFIG_16BIT (1<<1)
|
||||
#define NETX_EXT_CONFIG_CS_ENABLE (1<<0)
|
||||
|
||||
#define NETX_DPMAS_IO_MODE0_WRL (1<<13)
|
||||
#define NETX_DPMAS_IO_MODE0_WAIT (1<<14)
|
||||
#define NETX_DPMAS_IO_MODE0_READY (1<<15)
|
||||
#define NETX_DPMAS_IO_MODE0_CS0 (1<<19)
|
||||
#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20)
|
||||
|
||||
#define NETX_DPMAS_IO_MODE1_CS2 (1<<15)
|
||||
#define NETX_DPMAS_IO_MODE1_CS1 (1<<16)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36 (3<<30)
|
||||
|
||||
/*******************************
|
||||
* I2C *
|
||||
*******************************/
|
||||
#define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs))
|
||||
#define NETX_I2C_CTRL NETX_I2C_REG(0x0)
|
||||
#define NETX_I2C_DATA NETX_I2C_REG(0x4)
|
||||
|
||||
#endif /* __ASM_ARCH_NETX_REGS_H */
|
||||
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Reference in New Issue
Block a user