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Merge tag 'soc-fsl-next-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.7 DPAA2 DPIO driver performance optimization - Add and use QMAN multiple enqueue interface - Use function pointer indirection to replace checks in hotpath QUICC Engine drivers - Fix sparse warnings and exposed endian issues * tag 'soc-fsl-next-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: soc: fsl: qe: fix sparse warnings for ucc_slow.c soc: fsl: qe: ucc_slow: remove 0 assignment for kzalloc'ed structure soc: fsl: qe: fix sparse warnings for ucc_fast.c soc: fsl: qe: fix sparse warnings for qe_ic.c soc: fsl: qe: fix sparse warnings for ucc.c soc: fsl: qe: fix sparse warning for qe_common.c soc: fsl: qe: fix sparse warnings for qe.c soc: fsl: dpio: fix dereference of pointer p before null check soc: fsl: dpio: Replace QMAN array mode with ring mode enqueue soc: fsl: dpio: QMAN performance improvement with function pointer indirection soc: fsl: dpio: Adding QMAN multiple enqueue interface Link: https://lore.kernel.org/r/20200326001257.22696-1-leoyang.li@nxp.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -1,7 +1,7 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright 2014-2016 Freescale Semiconductor Inc.
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* Copyright 2016 NXP
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* Copyright 2016-2019 NXP
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*
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*/
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#include <linux/types.h>
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@@ -432,6 +432,69 @@ int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d,
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}
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EXPORT_SYMBOL(dpaa2_io_service_enqueue_fq);
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/**
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* dpaa2_io_service_enqueue_multiple_fq() - Enqueue multiple frames
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* to a frame queue using one fqid.
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* @d: the given DPIO service.
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* @fqid: the given frame queue id.
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* @fd: the frame descriptor which is enqueued.
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* @nb: number of frames to be enqueud
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*
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* Return 0 for successful enqueue, -EBUSY if the enqueue ring is not ready,
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* or -ENODEV if there is no dpio service.
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*/
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int dpaa2_io_service_enqueue_multiple_fq(struct dpaa2_io *d,
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u32 fqid,
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const struct dpaa2_fd *fd,
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int nb)
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{
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struct qbman_eq_desc ed;
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d = service_select(d);
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if (!d)
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return -ENODEV;
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qbman_eq_desc_clear(&ed);
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qbman_eq_desc_set_no_orp(&ed, 0);
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qbman_eq_desc_set_fq(&ed, fqid);
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return qbman_swp_enqueue_multiple(d->swp, &ed, fd, 0, nb);
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}
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EXPORT_SYMBOL(dpaa2_io_service_enqueue_multiple_fq);
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/**
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* dpaa2_io_service_enqueue_multiple_desc_fq() - Enqueue multiple frames
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* to different frame queue using a list of fqids.
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* @d: the given DPIO service.
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* @fqid: the given list of frame queue ids.
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* @fd: the frame descriptor which is enqueued.
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* @nb: number of frames to be enqueud
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*
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* Return 0 for successful enqueue, -EBUSY if the enqueue ring is not ready,
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* or -ENODEV if there is no dpio service.
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*/
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int dpaa2_io_service_enqueue_multiple_desc_fq(struct dpaa2_io *d,
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u32 *fqid,
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const struct dpaa2_fd *fd,
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int nb)
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{
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int i;
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struct qbman_eq_desc ed[32];
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d = service_select(d);
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if (!d)
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return -ENODEV;
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for (i = 0; i < nb; i++) {
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qbman_eq_desc_clear(&ed[i]);
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qbman_eq_desc_set_no_orp(&ed[i], 0);
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qbman_eq_desc_set_fq(&ed[i], fqid[i]);
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}
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return qbman_swp_enqueue_multiple_desc(d->swp, &ed[0], fd, nb);
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}
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EXPORT_SYMBOL(dpaa2_io_service_enqueue_multiple_desc_fq);
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/**
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* dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD.
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* @d: the given DPIO service.
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@@ -526,7 +589,7 @@ EXPORT_SYMBOL_GPL(dpaa2_io_service_acquire);
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/**
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* dpaa2_io_store_create() - Create the dma memory storage for dequeue result.
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* @max_frames: the maximum number of dequeued result for frames, must be <= 16.
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* @max_frames: the maximum number of dequeued result for frames, must be <= 32.
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* @dev: the device to allow mapping/unmapping the DMAable region.
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*
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* The size of the storage is "max_frames*sizeof(struct dpaa2_dq)".
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@@ -541,7 +604,7 @@ struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
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struct dpaa2_io_store *ret;
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size_t size;
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if (!max_frames || (max_frames > 16))
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if (!max_frames || (max_frames > 32))
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return NULL;
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ret = kmalloc(sizeof(*ret), GFP_KERNEL);
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File diff suppressed because it is too large
Load Diff
@@ -9,6 +9,13 @@
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#include <soc/fsl/dpaa2-fd.h>
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#define QMAN_REV_4000 0x04000000
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#define QMAN_REV_4100 0x04010000
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#define QMAN_REV_4101 0x04010001
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#define QMAN_REV_5000 0x05000000
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#define QMAN_REV_MASK 0xffff0000
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struct dpaa2_dq;
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struct qbman_swp;
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@@ -81,6 +88,10 @@ struct qbman_eq_desc {
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u8 wae;
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u8 rspid;
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__le64 rsp_addr;
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};
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struct qbman_eq_desc_with_fd {
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struct qbman_eq_desc desc;
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u8 fd[32];
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};
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@@ -132,8 +143,48 @@ struct qbman_swp {
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u8 dqrr_size;
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int reset_bug; /* indicates dqrr reset workaround is needed */
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} dqrr;
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struct {
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u32 pi;
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u32 pi_vb;
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u32 pi_ring_size;
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u32 pi_ci_mask;
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u32 ci;
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int available;
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u32 pend;
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u32 no_pfdr;
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} eqcr;
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spinlock_t access_spinlock;
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};
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/* Function pointers */
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extern
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int (*qbman_swp_enqueue_ptr)(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd);
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extern
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int (*qbman_swp_enqueue_multiple_ptr)(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd,
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uint32_t *flags,
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int num_frames);
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extern
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int (*qbman_swp_enqueue_multiple_desc_ptr)(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd,
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int num_frames);
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extern
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int (*qbman_swp_pull_ptr)(struct qbman_swp *s, struct qbman_pull_desc *d);
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extern
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const struct dpaa2_dq *(*qbman_swp_dqrr_next_ptr)(struct qbman_swp *s);
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extern
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int (*qbman_swp_release_ptr)(struct qbman_swp *s,
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const struct qbman_release_desc *d,
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const u64 *buffers,
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unsigned int num_buffers);
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/* Functions */
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struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
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void qbman_swp_finish(struct qbman_swp *p);
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u32 qbman_swp_interrupt_read_status(struct qbman_swp *p);
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@@ -158,9 +209,6 @@ void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
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void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
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enum qbman_pull_type_e dct);
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int qbman_swp_pull(struct qbman_swp *p, struct qbman_pull_desc *d);
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const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s);
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void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq);
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int qbman_result_has_new_result(struct qbman_swp *p, const struct dpaa2_dq *dq);
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@@ -172,15 +220,11 @@ void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
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void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
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u32 qd_bin, u32 qd_prio);
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int qbman_swp_enqueue(struct qbman_swp *p, const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd);
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void qbman_release_desc_clear(struct qbman_release_desc *d);
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void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid);
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void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
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int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
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const u64 *buffers, unsigned int num_buffers);
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int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
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unsigned int num_buffers);
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int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
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@@ -193,6 +237,61 @@ void *qbman_swp_mc_start(struct qbman_swp *p);
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void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb);
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void *qbman_swp_mc_result(struct qbman_swp *p);
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/**
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* qbman_swp_enqueue() - Issue an enqueue command
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* @s: the software portal used for enqueue
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* @d: the enqueue descriptor
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* @fd: the frame descriptor to be enqueued
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*
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* Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
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*/
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static inline int
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qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd)
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{
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return qbman_swp_enqueue_ptr(s, d, fd);
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}
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/**
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* qbman_swp_enqueue_multiple() - Issue a multi enqueue command
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* using one enqueue descriptor
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* @s: the software portal used for enqueue
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* @d: the enqueue descriptor
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* @fd: table pointer of frame descriptor table to be enqueued
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* @flags: table pointer of QBMAN_ENQUEUE_FLAG_DCA flags, not used if NULL
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* @num_frames: number of fd to be enqueued
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*
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* Return the number of fd enqueued, or a negative error number.
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*/
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static inline int
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qbman_swp_enqueue_multiple(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd,
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uint32_t *flags,
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int num_frames)
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{
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return qbman_swp_enqueue_multiple_ptr(s, d, fd, flags, num_frames);
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}
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/**
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* qbman_swp_enqueue_multiple_desc() - Issue a multi enqueue command
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* using multiple enqueue descriptor
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* @s: the software portal used for enqueue
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* @d: table of minimal enqueue descriptor
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* @fd: table pointer of frame descriptor table to be enqueued
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* @num_frames: number of fd to be enqueued
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*
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* Return the number of fd enqueued, or a negative error number.
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*/
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static inline int
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qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd,
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int num_frames)
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{
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return qbman_swp_enqueue_multiple_desc_ptr(s, d, fd, num_frames);
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}
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/**
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* qbman_result_is_DQ() - check if the dequeue result is a dequeue response
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* @dq: the dequeue result to be checked
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@@ -504,4 +603,49 @@ int qbman_bp_query(struct qbman_swp *s, u16 bpid,
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u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a);
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/**
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* qbman_swp_release() - Issue a buffer release command
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* @s: the software portal object
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* @d: the release descriptor
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* @buffers: a pointer pointing to the buffer address to be released
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* @num_buffers: number of buffers to be released, must be less than 8
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*
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* Return 0 for success, -EBUSY if the release command ring is not ready.
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*/
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static inline int qbman_swp_release(struct qbman_swp *s,
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const struct qbman_release_desc *d,
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const u64 *buffers,
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unsigned int num_buffers)
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{
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return qbman_swp_release_ptr(s, d, buffers, num_buffers);
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}
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/**
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* qbman_swp_pull() - Issue the pull dequeue command
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* @s: the software portal object
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* @d: the software portal descriptor which has been configured with
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* the set of qbman_pull_desc_set_*() calls
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*
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* Return 0 for success, and -EBUSY if the software portal is not ready
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* to do pull dequeue.
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*/
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static inline int qbman_swp_pull(struct qbman_swp *s,
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struct qbman_pull_desc *d)
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{
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return qbman_swp_pull_ptr(s, d);
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}
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/**
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* qbman_swp_dqrr_next() - Get an valid DQRR entry
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* @s: the software portal object
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*
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* Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry
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* only once, so repeated calls can return a sequence of DQRR entries, without
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* requiring they be consumed immediately or in any particular order.
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*/
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static inline const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
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{
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return qbman_swp_dqrr_next_ptr(s);
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}
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#endif /* __FSL_QBMAN_PORTAL_H */
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@@ -423,7 +423,7 @@ static void qe_upload_microcode(const void *base,
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qe_iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
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/* Set I-RAM Ready Register */
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qe_iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
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qe_iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
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}
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/*
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@@ -525,7 +525,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
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*/
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memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
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strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
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qe_firmware_info.extended_modes = firmware->extended_modes;
|
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qe_firmware_info.extended_modes = be64_to_cpu(firmware->extended_modes);
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memcpy(qe_firmware_info.vtraps, firmware->vtraps,
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sizeof(firmware->vtraps));
|
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@@ -46,7 +46,7 @@ int cpm_muram_init(void)
|
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{
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struct device_node *np;
|
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struct resource r;
|
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u32 zero[OF_MAX_ADDR_CELLS] = {};
|
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__be32 zero[OF_MAX_ADDR_CELLS] = {};
|
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resource_size_t max = 0;
|
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int i = 0;
|
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int ret = 0;
|
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|
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@@ -44,7 +44,7 @@
|
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struct qe_ic {
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/* Control registers offset */
|
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u32 __iomem *regs;
|
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__be32 __iomem *regs;
|
||||
|
||||
/* The remapper for this QEIC */
|
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struct irq_domain *irqhost;
|
||||
|
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@@ -632,7 +632,7 @@ int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock,
|
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{
|
||||
int source;
|
||||
u32 shift;
|
||||
struct qe_mux *qe_mux_reg;
|
||||
struct qe_mux __iomem *qe_mux_reg;
|
||||
|
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qe_mux_reg = &qe_immr->qmx;
|
||||
|
||||
|
||||
@@ -72,7 +72,7 @@ EXPORT_SYMBOL(ucc_slow_restart_tx);
|
||||
|
||||
void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
|
||||
{
|
||||
struct ucc_slow *us_regs;
|
||||
struct ucc_slow __iomem *us_regs;
|
||||
u32 gumr_l;
|
||||
|
||||
us_regs = uccs->us_regs;
|
||||
@@ -93,7 +93,7 @@ EXPORT_SYMBOL(ucc_slow_enable);
|
||||
|
||||
void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
|
||||
{
|
||||
struct ucc_slow *us_regs;
|
||||
struct ucc_slow __iomem *us_regs;
|
||||
u32 gumr_l;
|
||||
|
||||
us_regs = uccs->us_regs;
|
||||
@@ -122,7 +122,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
|
||||
u32 i;
|
||||
struct ucc_slow __iomem *us_regs;
|
||||
u32 gumr;
|
||||
struct qe_bd *bd;
|
||||
struct qe_bd __iomem *bd;
|
||||
u32 id;
|
||||
u32 command;
|
||||
int ret = 0;
|
||||
@@ -168,16 +168,9 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
uccs->saved_uccm = 0;
|
||||
uccs->p_rx_frame = 0;
|
||||
us_regs = uccs->us_regs;
|
||||
uccs->p_ucce = (u16 *) & (us_regs->ucce);
|
||||
uccs->p_uccm = (u16 *) & (us_regs->uccm);
|
||||
#ifdef STATISTICS
|
||||
uccs->rx_frames = 0;
|
||||
uccs->tx_frames = 0;
|
||||
uccs->rx_discarded = 0;
|
||||
#endif /* STATISTICS */
|
||||
uccs->p_ucce = &us_regs->ucce;
|
||||
uccs->p_uccm = &us_regs->uccm;
|
||||
|
||||
/* Get PRAM base */
|
||||
uccs->us_pram_offset =
|
||||
@@ -231,24 +224,24 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
|
||||
/* clear bd buffer */
|
||||
qe_iowrite32be(0, &bd->buf);
|
||||
/* set bd status and length */
|
||||
qe_iowrite32be(0, (u32 *)bd);
|
||||
qe_iowrite32be(0, (u32 __iomem *)bd);
|
||||
bd++;
|
||||
}
|
||||
/* for last BD set Wrap bit */
|
||||
qe_iowrite32be(0, &bd->buf);
|
||||
qe_iowrite32be(cpu_to_be32(T_W), (u32 *)bd);
|
||||
qe_iowrite32be(T_W, (u32 __iomem *)bd);
|
||||
|
||||
/* Init Rx bds */
|
||||
bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
|
||||
for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
|
||||
/* set bd status and length */
|
||||
qe_iowrite32be(0, (u32 *)bd);
|
||||
qe_iowrite32be(0, (u32 __iomem *)bd);
|
||||
/* clear bd buffer */
|
||||
qe_iowrite32be(0, &bd->buf);
|
||||
bd++;
|
||||
}
|
||||
/* for last BD set Wrap bit */
|
||||
qe_iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
|
||||
qe_iowrite32be(R_W, (u32 __iomem *)bd);
|
||||
qe_iowrite32be(0, &bd->buf);
|
||||
|
||||
/* Set GUMR (For more details see the hardware spec.). */
|
||||
@@ -273,8 +266,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
|
||||
qe_iowrite32be(gumr, &us_regs->gumr_h);
|
||||
|
||||
/* gumr_l */
|
||||
gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
|
||||
us_info->diag | us_info->mode;
|
||||
gumr = (u32)us_info->tdcr | (u32)us_info->rdcr | (u32)us_info->tenc |
|
||||
(u32)us_info->renc | (u32)us_info->diag | (u32)us_info->mode;
|
||||
if (us_info->tci)
|
||||
gumr |= UCC_SLOW_GUMR_L_TCI;
|
||||
if (us_info->rinv)
|
||||
@@ -289,8 +282,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
|
||||
|
||||
/* if the data is in cachable memory, the 'global' */
|
||||
/* in the function code should be set. */
|
||||
uccs->us_pram->tbmr = UCC_BMR_BO_BE;
|
||||
uccs->us_pram->rbmr = UCC_BMR_BO_BE;
|
||||
qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr);
|
||||
qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr);
|
||||
|
||||
/* rbase, tbase are offsets from MURAM base */
|
||||
qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright 2014-2016 Freescale Semiconductor Inc.
|
||||
* Copyright NXP
|
||||
* Copyright 2017-2019 NXP
|
||||
*
|
||||
*/
|
||||
#ifndef __FSL_DPAA2_IO_H
|
||||
@@ -109,6 +109,10 @@ int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
|
||||
|
||||
int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, u32 fqid,
|
||||
const struct dpaa2_fd *fd);
|
||||
int dpaa2_io_service_enqueue_multiple_fq(struct dpaa2_io *d, u32 fqid,
|
||||
const struct dpaa2_fd *fd, int number_of_frame);
|
||||
int dpaa2_io_service_enqueue_multiple_desc_fq(struct dpaa2_io *d, u32 *fqid,
|
||||
const struct dpaa2_fd *fd, int number_of_frame);
|
||||
int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
|
||||
u16 qdbin, const struct dpaa2_fd *fd);
|
||||
int dpaa2_io_service_release(struct dpaa2_io *d, u16 bpid,
|
||||
|
||||
@@ -178,10 +178,10 @@ struct ucc_fast_info {
|
||||
struct ucc_fast_private {
|
||||
struct ucc_fast_info *uf_info;
|
||||
struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
|
||||
u32 __iomem *p_ucce; /* a pointer to the event register in memory. */
|
||||
u32 __iomem *p_uccm; /* a pointer to the mask register in memory. */
|
||||
__be32 __iomem *p_ucce; /* a pointer to the event register in memory. */
|
||||
__be32 __iomem *p_uccm; /* a pointer to the mask register in memory. */
|
||||
#ifdef CONFIG_UGETH_TX_ON_DEMAND
|
||||
u16 __iomem *p_utodr; /* pointer to the transmit on demand register */
|
||||
__be16 __iomem *p_utodr;/* pointer to the transmit on demand register */
|
||||
#endif
|
||||
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
|
||||
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
|
||||
|
||||
@@ -184,7 +184,7 @@ struct ucc_slow_info {
|
||||
struct ucc_slow_private {
|
||||
struct ucc_slow_info *us_info;
|
||||
struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
|
||||
struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
|
||||
struct ucc_slow_pram __iomem *us_pram; /* a pointer to the parameter RAM */
|
||||
s32 us_pram_offset;
|
||||
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
|
||||
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
|
||||
@@ -196,13 +196,12 @@ struct ucc_slow_private {
|
||||
and length for first BD in a frame */
|
||||
s32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
|
||||
s32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
|
||||
struct qe_bd *confBd; /* next BD for confirm after Tx */
|
||||
struct qe_bd *tx_bd; /* next BD for new Tx request */
|
||||
struct qe_bd *rx_bd; /* next BD to collect after Rx */
|
||||
struct qe_bd __iomem *confBd; /* next BD for confirm after Tx */
|
||||
struct qe_bd __iomem *tx_bd; /* next BD for new Tx request */
|
||||
struct qe_bd __iomem *rx_bd; /* next BD to collect after Rx */
|
||||
void *p_rx_frame; /* accumulating receive frame */
|
||||
u16 *p_ucce; /* a pointer to the event register in memory.
|
||||
*/
|
||||
u16 *p_uccm; /* a pointer to the mask register in memory */
|
||||
__be16 __iomem *p_ucce; /* a pointer to the event register in memory */
|
||||
__be16 __iomem *p_uccm; /* a pointer to the mask register in memory */
|
||||
u16 saved_uccm; /* a saved mask for the RX Interrupt bits */
|
||||
#ifdef STATISTICS
|
||||
u32 tx_frames; /* Transmitted frames counters */
|
||||
|
||||
Reference in New Issue
Block a user