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Merge branch 'sparx5-ptp'
Horatiu Vultur says: ==================== net: sparx5: Add PTP Hardware Clock support Add support for PTP Hardware Clock (PHC) for sparx5. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
@@ -53,12 +53,14 @@ properties:
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items:
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- description: register based extraction
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- description: frame dma based extraction
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- description: ptp interrupt
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interrupt-names:
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minItems: 1
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items:
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- const: xtr
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- const: fdma
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- const: ptp
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resets:
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items:
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@@ -471,9 +471,10 @@
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<0x6 0x10004000 0x7fc000>,
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<0x6 0x11010000 0xaf0000>;
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reg-names = "cpu", "dev", "gcb";
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interrupt-names = "xtr", "fdma";
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interrupt-names = "xtr", "fdma", "ptp";
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&reset 0>;
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reset-names = "switch";
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};
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@@ -7,4 +7,5 @@ obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
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sparx5-switch-objs := sparx5_main.o sparx5_packet.o \
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sparx5_netdev.o sparx5_phylink.o sparx5_port.o sparx5_mactable.o sparx5_vlan.o \
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sparx5_switchdev.o sparx5_calendar.o sparx5_ethtool.o sparx5_fdma.o
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sparx5_switchdev.o sparx5_calendar.o sparx5_ethtool.o sparx5_fdma.o \
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sparx5_ptp.o
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@@ -1183,6 +1183,39 @@ static void sparx5_config_port_stats(struct sparx5 *sparx5, int portno)
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sparx5, ANA_AC_PORT_STAT_CFG(portno, SPX5_PORT_POLICER_DROPS));
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}
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static int sparx5_get_ts_info(struct net_device *dev,
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struct ethtool_ts_info *info)
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{
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struct sparx5_port *port = netdev_priv(dev);
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struct sparx5 *sparx5 = port->sparx5;
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struct sparx5_phc *phc;
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if (!sparx5->ptp)
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return ethtool_op_get_ts_info(dev, info);
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phc = &sparx5->phc[SPARX5_PHC_PORT];
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info->phc_index = phc->clock ? ptp_clock_index(phc->clock) : -1;
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if (info->phc_index == -1) {
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info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
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SOF_TIMESTAMPING_RX_SOFTWARE |
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SOF_TIMESTAMPING_SOFTWARE;
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return 0;
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}
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info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
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SOF_TIMESTAMPING_RX_SOFTWARE |
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SOF_TIMESTAMPING_SOFTWARE |
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SOF_TIMESTAMPING_TX_HARDWARE |
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SOF_TIMESTAMPING_RX_HARDWARE |
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SOF_TIMESTAMPING_RAW_HARDWARE;
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info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
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BIT(HWTSTAMP_TX_ONESTEP_SYNC);
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info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
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BIT(HWTSTAMP_FILTER_ALL);
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return 0;
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}
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const struct ethtool_ops sparx5_ethtool_ops = {
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.get_sset_count = sparx5_get_sset_count,
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.get_strings = sparx5_get_sset_strings,
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@@ -1194,6 +1227,7 @@ const struct ethtool_ops sparx5_ethtool_ops = {
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.get_eth_mac_stats = sparx5_get_eth_mac_stats,
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.get_eth_ctrl_stats = sparx5_get_eth_mac_ctrl_stats,
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.get_rmon_stats = sparx5_get_eth_rmon_stats,
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.get_ts_info = sparx5_get_ts_info,
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};
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int sparx_stats_init(struct sparx5 *sparx5)
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@@ -240,6 +240,8 @@ static bool sparx5_fdma_rx_get_frame(struct sparx5 *sparx5, struct sparx5_rx *rx
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skb_pull(skb, IFH_LEN * sizeof(u32));
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if (likely(!(skb->dev->features & NETIF_F_RXFCS)))
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skb_trim(skb, skb->len - ETH_FCS_LEN);
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sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp);
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skb->protocol = eth_type_trans(skb, skb->dev);
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/* Everything we see on an interface that is in the HW bridge
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* has already been forwarded
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@@ -190,6 +190,7 @@ static const struct sparx5_main_io_resource sparx5_main_iomap[] = {
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{ TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */
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{ TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */
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{ TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */
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{ TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */
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{ TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */
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{ TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */
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{ TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */
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@@ -692,6 +693,18 @@ static int sparx5_start(struct sparx5 *sparx5)
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} else {
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sparx5->xtr_irq = -ENXIO;
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}
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if (sparx5->ptp_irq >= 0) {
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err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq,
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NULL, sparx5_ptp_irq_handler,
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IRQF_ONESHOT, "sparx5-ptp",
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sparx5);
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if (err)
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sparx5->ptp_irq = -ENXIO;
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sparx5->ptp = 1;
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}
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return err;
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}
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@@ -808,6 +821,7 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
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sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma");
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sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr");
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sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp");
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/* Read chip ID to check CPU interface */
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sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID);
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@@ -846,6 +860,12 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
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dev_err(sparx5->dev, "Start failed\n");
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goto cleanup_ports;
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}
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err = sparx5_ptp_init(sparx5);
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if (err) {
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dev_err(sparx5->dev, "PTP failed\n");
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goto cleanup_ports;
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}
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goto cleanup_config;
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cleanup_ports:
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@@ -869,6 +889,7 @@ static int mchp_sparx5_remove(struct platform_device *pdev)
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disable_irq(sparx5->fdma_irq);
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sparx5->fdma_irq = -ENXIO;
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}
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sparx5_ptp_deinit(sparx5);
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sparx5_fdma_stop(sparx5);
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sparx5_cleanup_ports(sparx5);
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/* Unregister netdevs */
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@@ -14,6 +14,8 @@
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#include <linux/if_vlan.h>
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#include <linux/bitmap.h>
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#include <linux/phylink.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/hrtimer.h>
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#include "sparx5_main_regs.h"
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@@ -79,6 +81,18 @@ enum sparx5_vlan_port_type {
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#define FDMA_RX_DCB_MAX_DBS 15
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#define FDMA_TX_DCB_MAX_DBS 1
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#define SPARX5_PHC_COUNT 3
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#define SPARX5_PHC_PORT 0
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#define IFH_REW_OP_NOOP 0x0
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#define IFH_REW_OP_ONE_STEP_PTP 0x3
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#define IFH_REW_OP_TWO_STEP_PTP 0x4
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#define IFH_PDU_TYPE_NONE 0x0
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#define IFH_PDU_TYPE_PTP 0x5
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#define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6
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#define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7
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struct sparx5;
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struct sparx5_db_hw {
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@@ -167,9 +181,12 @@ struct sparx5_port {
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enum sparx5_port_max_tags max_vlan_tags;
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enum sparx5_vlan_port_type vlan_type;
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u32 custom_etype;
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u32 ifh[IFH_LEN];
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bool vlan_aware;
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struct hrtimer inj_timer;
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/* ptp */
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u8 ptp_cmd;
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u16 ts_id;
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struct sk_buff_head tx_skbs;
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};
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enum sparx5_core_clockfreq {
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@@ -179,6 +196,26 @@ enum sparx5_core_clockfreq {
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SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */
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};
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struct sparx5_phc {
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struct ptp_clock *clock;
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struct ptp_clock_info info;
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struct hwtstamp_config hwtstamp_config;
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struct sparx5 *sparx5;
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u8 index;
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};
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struct sparx5_skb_cb {
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u8 rew_op;
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u8 pdu_type;
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u8 pdu_w16_offset;
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u16 ts_id;
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unsigned long jiffies;
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};
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#define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10)
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#define SPARX5_SKB_CB(skb) \
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((struct sparx5_skb_cb *)((skb)->cb))
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struct sparx5 {
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struct platform_device *pdev;
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struct device *dev;
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@@ -226,6 +263,14 @@ struct sparx5 {
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int fdma_irq;
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struct sparx5_rx rx;
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struct sparx5_tx tx;
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/* PTP */
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bool ptp;
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struct sparx5_phc phc[SPARX5_PHC_COUNT];
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spinlock_t ptp_clock_lock; /* lock for phc */
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spinlock_t ptp_ts_id_lock; /* lock for ts_id */
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struct mutex ptp_lock; /* lock for ptp interface state */
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u16 ptp_skbs;
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int ptp_irq;
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};
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/* sparx5_switchdev.c */
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@@ -235,6 +280,7 @@ void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);
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/* sparx5_packet.c */
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struct frame_info {
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int src_port;
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u32 timestamp;
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};
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void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp);
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@@ -288,12 +334,30 @@ void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats
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int sparx_stats_init(struct sparx5 *sparx5);
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/* sparx5_netdev.c */
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void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp);
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void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op);
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void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type);
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void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset);
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void sparx5_set_port_ifh(void *ifh_hdr, u16 portno);
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bool sparx5_netdevice_check(const struct net_device *dev);
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struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno);
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int sparx5_register_netdevs(struct sparx5 *sparx5);
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void sparx5_destroy_netdevs(struct sparx5 *sparx5);
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void sparx5_unregister_netdevs(struct sparx5 *sparx5);
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/* sparx5_ptp.c */
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int sparx5_ptp_init(struct sparx5 *sparx5);
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void sparx5_ptp_deinit(struct sparx5 *sparx5);
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int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr);
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int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr);
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void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb,
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u64 timestamp);
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int sparx5_ptp_txtstamp_request(struct sparx5_port *port,
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struct sk_buff *skb);
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void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
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struct sk_buff *skb);
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irqreturn_t sparx5_ptp_irq_handler(int irq, void *args);
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/* Clock period in picoseconds */
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static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
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{
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@@ -4,8 +4,8 @@
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* Copyright (c) 2021 Microchip Technology Inc.
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*/
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/* This file is autogenerated by cml-utils 2021-05-06 13:06:37 +0200.
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* Commit ID: 9ae4ec441e25e4b9003f4e514df5cb12a36b84d3
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/* This file is autogenerated by cml-utils 2022-02-26 14:15:01 +0100.
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* Commit ID: 98bdd3d171cc2a1afd30d241d41a4281d471a48c (dirty)
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*/
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#ifndef _SPARX5_MAIN_REGS_H_
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@@ -40,6 +40,7 @@ enum sparx5_target {
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TARGET_PCS25G_BR = 144,
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TARGET_PCS5G_BR = 160,
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TARGET_PORT_CONF = 173,
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TARGET_PTP = 174,
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TARGET_QFWD = 175,
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TARGET_QRES = 176,
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TARGET_QS = 177,
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@@ -4156,6 +4157,249 @@ enum sparx5_target {
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#define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\
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FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
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/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */
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#define PTP_PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 0, 0, 1, 4)
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#define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0)
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#define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\
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FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x)
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#define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\
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FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x)
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/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */
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#define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 4, 0, 1, 4)
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#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0)
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#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\
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FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
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#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\
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FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
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/* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */
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#define PTP_PTP_INTR_IDENT __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 8, 0, 1, 4)
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#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0)
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#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\
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FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
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#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\
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FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
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/* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */
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#define PTP_PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 12, 0, 1, 4)
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|
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#define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9)
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#define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\
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FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
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#define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\
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FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
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#define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6)
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#define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\
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FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x)
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#define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\
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FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x)
|
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|
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#define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3)
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#define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\
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FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
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#define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\
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FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
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|
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#define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0)
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#define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\
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FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
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#define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\
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FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
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/* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */
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#define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 0, r, 2, 4)
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/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */
|
||||
#define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 8, 0, 1, 4)
|
||||
|
||||
#define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0)
|
||||
#define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
|
||||
#define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\
|
||||
FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */
|
||||
#define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 12, 0, 1, 4)
|
||||
|
||||
#define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0)
|
||||
#define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
|
||||
#define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\
|
||||
FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */
|
||||
#define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 16, 0, 1, 4)
|
||||
|
||||
/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */
|
||||
#define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 20, 0, 1, 4)
|
||||
|
||||
#define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0)
|
||||
#define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
|
||||
#define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\
|
||||
FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */
|
||||
#define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 24, 0, 1, 4)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */
|
||||
#define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 0, 0, 1, 4)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18)
|
||||
#define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK BIT(13)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
|
||||
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
|
||||
#define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\
|
||||
FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */
|
||||
#define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 4, 0, 1, 4)
|
||||
|
||||
#define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0)
|
||||
#define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
|
||||
#define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\
|
||||
FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */
|
||||
#define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 8, 0, 1, 4)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */
|
||||
#define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 12, 0, 1, 4)
|
||||
|
||||
#define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0)
|
||||
#define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
|
||||
#define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\
|
||||
FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */
|
||||
#define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 16, 0, 1, 4)
|
||||
|
||||
#define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0)
|
||||
#define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\
|
||||
FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
|
||||
#define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\
|
||||
FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:NTP_NSEC */
|
||||
#define PTP_NTP_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 20, 0, 1, 4)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */
|
||||
#define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 24, 0, 1, 4)
|
||||
|
||||
#define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0)
|
||||
#define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\
|
||||
FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
|
||||
#define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\
|
||||
FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */
|
||||
#define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 28, 0, 1, 4)
|
||||
|
||||
#define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0)
|
||||
#define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\
|
||||
FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
|
||||
#define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\
|
||||
FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
|
||||
|
||||
/* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */
|
||||
#define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 32, 0, 1, 4)
|
||||
|
||||
#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3)
|
||||
#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\
|
||||
FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
|
||||
#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\
|
||||
FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
|
||||
|
||||
#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0)
|
||||
#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\
|
||||
FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
|
||||
#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\
|
||||
FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
|
||||
|
||||
/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */
|
||||
#define PTP_PHAD_CTRL(g) __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 0, 0, 1, 4)
|
||||
|
||||
#define PTP_PHAD_CTRL_PHAD_ENA BIT(7)
|
||||
#define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\
|
||||
FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x)
|
||||
#define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\
|
||||
FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x)
|
||||
|
||||
#define PTP_PHAD_CTRL_PHAD_FAILED BIT(6)
|
||||
#define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\
|
||||
FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x)
|
||||
#define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\
|
||||
FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x)
|
||||
|
||||
#define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3)
|
||||
#define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\
|
||||
FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x)
|
||||
#define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\
|
||||
FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x)
|
||||
|
||||
#define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0)
|
||||
#define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\
|
||||
FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x)
|
||||
#define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\
|
||||
FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x)
|
||||
|
||||
/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */
|
||||
#define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 4, 0, 1, 4)
|
||||
|
||||
/* QFWD:SYSTEM:SWITCH_PORT_MODE */
|
||||
#define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, 70, 4)
|
||||
|
||||
@@ -4528,6 +4772,93 @@ enum sparx5_target {
|
||||
#define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\
|
||||
FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
|
||||
|
||||
/* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */
|
||||
#define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
|
||||
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
|
||||
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
|
||||
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
|
||||
|
||||
#define REW_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9)
|
||||
#define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
|
||||
#define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
|
||||
|
||||
#define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
|
||||
#define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
|
||||
#define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
|
||||
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
|
||||
#define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
|
||||
|
||||
/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */
|
||||
#define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
|
||||
|
||||
#define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0)
|
||||
#define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
|
||||
#define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
|
||||
|
||||
/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */
|
||||
#define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
|
||||
|
||||
#define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0)
|
||||
#define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\
|
||||
FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
|
||||
#define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\
|
||||
FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
|
||||
|
||||
/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */
|
||||
#define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
|
||||
|
||||
/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */
|
||||
#define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
|
||||
|
||||
/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */
|
||||
#define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
|
||||
|
||||
#define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0)
|
||||
#define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\
|
||||
FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
|
||||
#define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\
|
||||
FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
|
||||
|
||||
/* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */
|
||||
#define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
|
||||
|
||||
#define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2)
|
||||
#define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\
|
||||
FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
|
||||
#define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\
|
||||
FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
|
||||
|
||||
#define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0)
|
||||
#define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\
|
||||
FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
|
||||
#define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\
|
||||
FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
|
||||
|
||||
/* REW:RAM_CTRL:RAM_INIT */
|
||||
#define REW_RAM_INIT __REG(TARGET_REW, 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4)
|
||||
|
||||
|
||||
@@ -54,7 +54,7 @@ static void __ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
|
||||
ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40);
|
||||
}
|
||||
|
||||
static void sparx5_set_port_ifh(void *ifh_hdr, u16 portno)
|
||||
void sparx5_set_port_ifh(void *ifh_hdr, u16 portno)
|
||||
{
|
||||
/* VSTAX.RSV = 1. MSBit must be 1 */
|
||||
ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1);
|
||||
@@ -74,6 +74,26 @@ static void sparx5_set_port_ifh(void *ifh_hdr, u16 portno)
|
||||
ifh_encode_bitfield(ifh_hdr, 1, 67, 1);
|
||||
}
|
||||
|
||||
void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op)
|
||||
{
|
||||
ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32, 10);
|
||||
}
|
||||
|
||||
void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type)
|
||||
{
|
||||
ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4);
|
||||
}
|
||||
|
||||
void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset)
|
||||
{
|
||||
ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6);
|
||||
}
|
||||
|
||||
void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp)
|
||||
{
|
||||
ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40);
|
||||
}
|
||||
|
||||
static int sparx5_port_open(struct net_device *ndev)
|
||||
{
|
||||
struct sparx5_port *port = netdev_priv(ndev);
|
||||
@@ -179,6 +199,24 @@ static int sparx5_get_port_parent_id(struct net_device *dev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sparx5_port_ioctl(struct net_device *dev, struct ifreq *ifr,
|
||||
int cmd)
|
||||
{
|
||||
struct sparx5_port *sparx5_port = netdev_priv(dev);
|
||||
struct sparx5 *sparx5 = sparx5_port->sparx5;
|
||||
|
||||
if (!phy_has_hwtstamp(dev->phydev) && sparx5->ptp) {
|
||||
switch (cmd) {
|
||||
case SIOCSHWTSTAMP:
|
||||
return sparx5_ptp_hwtstamp_set(sparx5_port, ifr);
|
||||
case SIOCGHWTSTAMP:
|
||||
return sparx5_ptp_hwtstamp_get(sparx5_port, ifr);
|
||||
}
|
||||
}
|
||||
|
||||
return phy_mii_ioctl(dev->phydev, ifr, cmd);
|
||||
}
|
||||
|
||||
static const struct net_device_ops sparx5_port_netdev_ops = {
|
||||
.ndo_open = sparx5_port_open,
|
||||
.ndo_stop = sparx5_port_stop,
|
||||
@@ -189,6 +227,7 @@ static const struct net_device_ops sparx5_port_netdev_ops = {
|
||||
.ndo_validate_addr = eth_validate_addr,
|
||||
.ndo_get_stats64 = sparx5_get_stats64,
|
||||
.ndo_get_port_parent_id = sparx5_get_port_parent_id,
|
||||
.ndo_eth_ioctl = sparx5_port_ioctl,
|
||||
};
|
||||
|
||||
bool sparx5_netdevice_check(const struct net_device *dev)
|
||||
@@ -210,7 +249,6 @@ struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno)
|
||||
spx5_port->ndev = ndev;
|
||||
spx5_port->sparx5 = sparx5;
|
||||
spx5_port->portno = portno;
|
||||
sparx5_set_port_ifh(spx5_port->ifh, portno);
|
||||
|
||||
ndev->netdev_ops = &sparx5_port_netdev_ops;
|
||||
ndev->ethtool_ops = &sparx5_ethtool_ops;
|
||||
|
||||
@@ -44,6 +44,12 @@ void sparx5_ifh_parse(u32 *ifh, struct frame_info *info)
|
||||
((u32)xtr_hdr[30] << 0);
|
||||
fwd = (fwd >> 5);
|
||||
info->src_port = FIELD_GET(GENMASK(7, 1), fwd);
|
||||
|
||||
info->timestamp =
|
||||
((u64)xtr_hdr[2] << 24) |
|
||||
((u64)xtr_hdr[3] << 16) |
|
||||
((u64)xtr_hdr[4] << 8) |
|
||||
((u64)xtr_hdr[5] << 0);
|
||||
}
|
||||
|
||||
static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap)
|
||||
@@ -144,6 +150,7 @@ static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap)
|
||||
/* Finish up skb */
|
||||
skb_put(skb, byte_cnt - ETH_FCS_LEN);
|
||||
eth_skb_pad(skb);
|
||||
sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp);
|
||||
skb->protocol = eth_type_trans(skb, netdev);
|
||||
netdev->stats.rx_bytes += skb->len;
|
||||
netdev->stats.rx_packets++;
|
||||
@@ -218,20 +225,44 @@ int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev)
|
||||
struct net_device_stats *stats = &dev->stats;
|
||||
struct sparx5_port *port = netdev_priv(dev);
|
||||
struct sparx5 *sparx5 = port->sparx5;
|
||||
u32 ifh[IFH_LEN];
|
||||
int ret;
|
||||
|
||||
memset(ifh, 0, IFH_LEN * 4);
|
||||
sparx5_set_port_ifh(ifh, port->portno);
|
||||
|
||||
if (sparx5->ptp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
|
||||
ret = sparx5_ptp_txtstamp_request(port, skb);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
sparx5_set_port_ifh_rew_op(ifh, SPARX5_SKB_CB(skb)->rew_op);
|
||||
sparx5_set_port_ifh_pdu_type(ifh, SPARX5_SKB_CB(skb)->pdu_type);
|
||||
sparx5_set_port_ifh_pdu_w16_offset(ifh, SPARX5_SKB_CB(skb)->pdu_w16_offset);
|
||||
sparx5_set_port_ifh_timestamp(ifh, SPARX5_SKB_CB(skb)->ts_id);
|
||||
}
|
||||
|
||||
skb_tx_timestamp(skb);
|
||||
if (sparx5->fdma_irq > 0)
|
||||
ret = sparx5_fdma_xmit(sparx5, port->ifh, skb);
|
||||
ret = sparx5_fdma_xmit(sparx5, ifh, skb);
|
||||
else
|
||||
ret = sparx5_inject(sparx5, port->ifh, skb, dev);
|
||||
ret = sparx5_inject(sparx5, ifh, skb, dev);
|
||||
|
||||
if (ret == NETDEV_TX_OK) {
|
||||
stats->tx_bytes += skb->len;
|
||||
stats->tx_packets++;
|
||||
skb_tx_timestamp(skb);
|
||||
|
||||
if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
|
||||
SPARX5_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP)
|
||||
return ret;
|
||||
|
||||
dev_kfree_skb_any(skb);
|
||||
} else {
|
||||
stats->tx_dropped++;
|
||||
|
||||
if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
|
||||
SPARX5_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP)
|
||||
sparx5_ptp_txtstamp_release(port, skb);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user