mirror of
https://github.com/ukui/kernel.git
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Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next
- Qualcomm QCS404 CDSP clk support - Qualcomm QCS404 Turing clk support - Mediatek MT8183 clock support - Mediatek MT8516 clock support - Milbeaut M10V clk controller support * clk-renesas: clk: renesas: rcar-gen3: Remove unused variable clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value clk: renesas: r8a77980: Fix RPC-IF module clock's parent clk: renesas: rcar-gen3: Rename DRIF clocks clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC clk: renesas: rcar-gen3: Correct parent clock of HS-USB clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI clk: renesas: r8a774c0: Add Z2 clock clk: renesas: r8a77990: Add Z2 clock clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents math64: New DIV64_U64_ROUND_CLOSEST helper clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r9a06g032: Add missing PCI USB clock clk: renesas: r7s9210: Always use readl() clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() * clk-qcom: clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 clk: qcom: Add QCS404 TuringCC clk: qcom: branch: Add AON clock ops dt-bindings: clock: Introduce Qualcomm Turing Clock controller clk: qcom: gcc-qcs404: Add CDSP related clocks and resets * clk-mtk: clk: mediatek: add clock driver for MT8516 dt-bindings: mediatek: apmixedsys: add support for MT8516 dt-bindings: mediatek: infracfg: add support for MT8516 dt-bindings: mediatek: topckgen: add support for MT8516 clk: mediatek: Allow changing PLL rate when it is off clk: mediatek: Add MT8183 clock support clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add dt-bindings for MT8183 clocks dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data clk: mediatek: Add new clkmux register API clk: mediatek: Disable tuner_en before change PLL rate * clk-milbeaut: clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: clock: milbeaut: add Milbeaut clock description * clk-imx: clk: imx: correct pfdv2 gate_bit/vld_bit operations clk: imx: clk-pllv3: mark expected switch fall-throughs clk: imx8mq: Add dsi_ipg_div clk: imx: pllv4: add fractional-N pll support clk: imx: keep uart clock on during system boot clk: imx: correct i.MX7D AV PLL num/denom offset clk: imx6sll: Fix mispelling uart4_serial as serail clk: imx: pll14xx: drop unused variable clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers clk: imx: Remove unused imx_get_clk_hw_fixed dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock
This commit is contained in:
Stephen Boyd
@@ -14,6 +14,8 @@ Required Properties:
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- "mediatek,mt7629-apmixedsys"
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- "mediatek,mt8135-apmixedsys"
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- "mediatek,mt8173-apmixedsys"
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- "mediatek,mt8183-apmixedsys", "syscon"
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- "mediatek,mt8516-apmixedsys"
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- #clock-cells: Must be 1
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The apmixedsys controller uses the common clk binding from
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@@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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- #clock-cells: Must be 1
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The AUDSYS controller uses the common clk binding from
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@@ -0,0 +1,22 @@
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MediaTek CAMSYS controller
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============================
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The MediaTek camsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt8183-camsys", "syscon"
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- #clock-cells: Must be 1
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The camsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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camsys: camsys@1a000000 {
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compatible = "mediatek,mt8183-camsys", "syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -11,6 +11,7 @@ Required Properties:
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- "mediatek,mt8183-imgsys", "syscon"
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- #clock-cells: Must be 1
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The imgsys controller uses the common clk binding from
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@@ -15,6 +15,8 @@ Required Properties:
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- "mediatek,mt7629-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- "mediatek,mt8183-infracfg", "syscon"
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- "mediatek,mt8516-infracfg", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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@@ -0,0 +1,43 @@
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Mediatek IPU controller
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============================
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The Mediatek ipu controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt8183-ipu_conn", "syscon"
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- "mediatek,mt8183-ipu_adl", "syscon"
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- "mediatek,mt8183-ipu_core0", "syscon"
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- "mediatek,mt8183-ipu_core1", "syscon"
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- #clock-cells: Must be 1
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The ipu controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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ipu_conn: syscon@19000000 {
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compatible = "mediatek,mt8183-ipu_conn", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_adl: syscon@19010000 {
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compatible = "mediatek,mt8183-ipu_adl", "syscon";
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reg = <0 0x19010000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_core0: syscon@19180000 {
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compatible = "mediatek,mt8183-ipu_core0", "syscon";
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reg = <0 0x19180000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_core1: syscon@19280000 {
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compatible = "mediatek,mt8183-ipu_core1", "syscon";
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reg = <0 0x19280000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-mcucfg", "syscon"
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- "mediatek,mt8183-mcucfg", "syscon"
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- #clock-cells: Must be 1
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The mcucfg controller uses the common clk binding from
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-mfgcfg", "syscon"
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- "mediatek,mt8183-mfgcfg", "syscon"
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- #clock-cells: Must be 1
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The mfgcfg controller uses the common clk binding from
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@@ -11,6 +11,7 @@ Required Properties:
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- "mediatek,mt6797-mmsys", "syscon"
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- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt8173-mmsys", "syscon"
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- "mediatek,mt8183-mmsys", "syscon"
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- #clock-cells: Must be 1
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The mmsys controller uses the common clk binding from
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@@ -14,6 +14,8 @@ Required Properties:
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- "mediatek,mt7629-topckgen"
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- "mediatek,mt8135-topckgen"
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- "mediatek,mt8173-topckgen"
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- "mediatek,mt8183-topckgen", "syscon"
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- "mediatek,mt8516-topckgen"
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- #clock-cells: Must be 1
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The topckgen controller uses the common clk binding from
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@@ -11,6 +11,7 @@ Required Properties:
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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- "mediatek,mt8183-vdecsys", "syscon"
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- #clock-cells: Must be 1
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The vdecsys controller uses the common clk binding from
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@@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2712-vencsys", "syscon"
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- "mediatek,mt6797-vencsys", "syscon"
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- "mediatek,mt8173-vencsys", "syscon"
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- "mediatek,mt8183-vencsys", "syscon"
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- #clock-cells: Must be 1
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The vencsys controller uses the common clk binding from
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@@ -0,0 +1,73 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Milbeaut SoCs Clock Controller Binding
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maintainers:
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- Taichi Sugaya <sugaya.taichi@socionext.com>
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description: |
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Milbeaut SoCs Clock controller is an integrated clock controller, which
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generates and supplies to all modules.
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This binding uses common clock bindings
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- socionext,milbeaut-m10v-ccu
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clocks:
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maxItems: 1
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description: external clock
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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examples:
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# Clock controller node:
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- |
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m10v-clk-ctrl@1d021000 {
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compatible = "socionext,milbeaut-m10v-clk-ccu";
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reg = <0x1d021000 0x4000>;
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#clock-cells = <1>;
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clocks = <&clki40mhz>;
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};
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# Required an external clock for Clock controller node:
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- |
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clocks {
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clki40mhz: clki40mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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};
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/* other clocks */
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};
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# The clock consumer shall specify the desired clock-output of the clock
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# controller as below by specifying output-id in its "clk" phandle cell.
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# 2: uart
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# 4: 32-bit timer
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# 7: UHS-I/II
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- |
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serial@1e700010 {
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compatible = "socionext,milbeaut-usio-uart";
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reg = <0x1e700010 0x10>;
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interrupts = <0 141 0x4>, <0 149 0x4>;
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interrupt-names = "rx", "tx";
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clocks = <&clk 2>;
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};
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...
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@@ -0,0 +1,19 @@
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Qualcomm Turing Clock & Reset Controller Binding
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------------------------------------------------
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Required properties :
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- compatible: shall contain "qcom,qcs404-turingcc".
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- reg: shall contain base register location and length.
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- clocks: ahb clock for the TuringCC
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- #clock-cells: from common clock binding, shall contain 1.
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- #reset-cells: from common reset binding, shall contain 1.
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Example:
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turingcc: clock-controller@800000 {
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compatible = "qcom,qcs404-turingcc";
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reg = <0x00800000 0x30000>;
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clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@@ -34,6 +34,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
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obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
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obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
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obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
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obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
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obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
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obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
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File diff suppressed because it is too large
Load Diff
@@ -35,7 +35,7 @@ obj-$(CONFIG_SOC_IMX25) += clk-imx25.o
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obj-$(CONFIG_SOC_IMX27) += clk-imx27.o
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obj-$(CONFIG_SOC_IMX31) += clk-imx31.o
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obj-$(CONFIG_SOC_IMX35) += clk-imx35.o
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obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o
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obj-$(CONFIG_SOC_IMX5) += clk-imx5.o
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obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o
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obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
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obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
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@@ -164,10 +164,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
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clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
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clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
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periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
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clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
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main_bus_sel, ARRAY_SIZE(main_bus_sel));
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clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
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per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
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clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
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@@ -191,16 +187,10 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
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clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
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clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
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clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
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clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
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clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
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clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
|
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clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
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clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
|
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clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
|
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clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
|
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emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
|
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@@ -311,10 +301,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
|
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clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
|
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clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
|
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|
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/* Set SDHC parents to be PLL2 */
|
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clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
|
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clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
|
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|
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/* move usb phy clk to 24MHz */
|
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clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
|
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}
|
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@@ -342,8 +328,21 @@ static void __init mx50_clocks_init(struct device_node *np)
|
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|
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mx5_clocks_common_init(ccm_base);
|
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|
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/*
|
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* This clock is called periph_clk in the i.MX50 Reference Manual, but
|
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* it comes closest in scope to the main_bus_clk of i.MX51 and i.MX53
|
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*/
|
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clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 2,
|
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
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|
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clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
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lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
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clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 21, 2,
|
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
|
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
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clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
|
||||
clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
|
||||
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
|
||||
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
|
||||
@@ -372,6 +371,10 @@ static void __init mx50_clocks_init(struct device_node *np)
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
/* Set SDHC parents to be PLL2 */
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
@@ -410,6 +413,10 @@ static void __init mx51_clocks_init(struct device_node *np)
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
|
||||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
|
||||
main_bus_sel, ARRAY_SIZE(main_bus_sel));
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
|
||||
@@ -422,6 +429,12 @@ static void __init mx51_clocks_init(struct device_node *np)
|
||||
mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
|
||||
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
|
||||
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
|
||||
clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
|
||||
clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
|
||||
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
|
||||
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
|
||||
@@ -452,6 +465,10 @@ static void __init mx51_clocks_init(struct device_node *np)
|
||||
/* set the usboh3 parent to pll2_sw */
|
||||
clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
/* Set SDHC parents to be PLL2 */
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
/* set SDHC root clock to 166.25MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
|
||||
@@ -506,6 +523,10 @@ static void __init mx53_clocks_init(struct device_node *np)
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
|
||||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
|
||||
main_bus_sel, ARRAY_SIZE(main_bus_sel));
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
@@ -527,6 +548,12 @@ static void __init mx53_clocks_init(struct device_node *np)
|
||||
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
|
||||
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
|
||||
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
|
||||
clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
|
||||
clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
|
||||
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
|
||||
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
|
||||
@@ -589,6 +616,10 @@ static void __init mx53_clocks_init(struct device_node *np)
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
/* Set SDHC parents to be PLL2 */
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
@@ -76,6 +76,20 @@ static u32 share_count_ssi1;
|
||||
static u32 share_count_ssi2;
|
||||
static u32 share_count_ssi3;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clks[IMX6SLL_CLK_UART1_IPG],
|
||||
&clks[IMX6SLL_CLK_UART1_SERIAL],
|
||||
&clks[IMX6SLL_CLK_UART2_IPG],
|
||||
&clks[IMX6SLL_CLK_UART2_SERIAL],
|
||||
&clks[IMX6SLL_CLK_UART3_IPG],
|
||||
&clks[IMX6SLL_CLK_UART3_SERIAL],
|
||||
&clks[IMX6SLL_CLK_UART4_IPG],
|
||||
&clks[IMX6SLL_CLK_UART4_SERIAL],
|
||||
&clks[IMX6SLL_CLK_UART5_IPG],
|
||||
&clks[IMX6SLL_CLK_UART5_SERIAL],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
@@ -268,7 +282,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6SLL_CLK_GPT_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
|
||||
clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
|
||||
clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
|
||||
clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
|
||||
clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
|
||||
clks[IMX6SLL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
|
||||
clks[IMX6SLL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
|
||||
|
||||
@@ -334,6 +348,8 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
/* Lower the AHB clock rate before changing the clock source. */
|
||||
clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
|
||||
|
||||
|
||||
@@ -417,8 +417,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f);
|
||||
clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);
|
||||
clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0);
|
||||
clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f);
|
||||
clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f);
|
||||
clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f);
|
||||
clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f);
|
||||
|
||||
clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT);
|
||||
clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user