mirror of
https://github.com/ukui/kernel.git
synced 2026-03-09 10:07:04 -07:00
Merge branch 'spi-5.7' into spi-next
This commit is contained in:
Mark Brown
@@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-or-later)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fsi/ibm,fsi2spi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: IBM FSI-attached SPI controllers
|
||||
|
||||
maintainers:
|
||||
- Eddie James <eajames@linux.ibm.com>
|
||||
|
||||
description: |
|
||||
This binding describes an FSI CFAM engine called the FSI2SPI. Therefore this
|
||||
node will always be a child of an FSI CFAM node; see fsi.txt for details on
|
||||
FSI slave and CFAM nodes. This FSI2SPI engine provides access to a number of
|
||||
SPI controllers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ibm,fsi2spi
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: FSI slave address
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
fsi2spi@1c00 {
|
||||
compatible = "ibm,fsi2spi";
|
||||
reg = <0x1c00 0x400>;
|
||||
};
|
||||
@@ -61,6 +61,7 @@ Regulator nodes are identified by their compatible:
|
||||
"qcom,rpm-pm8901-regulators"
|
||||
"qcom,rpm-pm8921-regulators"
|
||||
"qcom,rpm-pm8018-regulators"
|
||||
"qcom,rpm-smb208-regulators"
|
||||
|
||||
- vdd_l0_l1_lvs-supply:
|
||||
- vdd_l2_l11_l12-supply:
|
||||
@@ -171,6 +172,9 @@ pm8018:
|
||||
s1, s2, s3, s4, s5, , l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
|
||||
l12, l14, lvs1
|
||||
|
||||
smb208:
|
||||
s1a, s1b, s2a, s2b
|
||||
|
||||
The content of each sub-node is defined by the standard binding for regulators -
|
||||
see regulator.txt - with additional custom properties described below:
|
||||
|
||||
|
||||
@@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/mps,mp5416.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Monolithic Power System MP5416 PMIC
|
||||
|
||||
maintainers:
|
||||
- Saravanan Sekar <sravanhome@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^pmic@[0-9a-f]{1,2}$"
|
||||
compatible:
|
||||
enum:
|
||||
- mps,mp5416
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
description: |
|
||||
list of regulators provided by this controller, must be named
|
||||
after their hardware counterparts BUCK[1-4] and LDO[1-4]
|
||||
|
||||
patternProperties:
|
||||
"^buck[1-4]$":
|
||||
allOf:
|
||||
- $ref: "regulator.yaml#"
|
||||
type: object
|
||||
|
||||
"^ldo[1-4]$":
|
||||
allOf:
|
||||
- $ref: "regulator.yaml#"
|
||||
type: object
|
||||
|
||||
additionalProperties: false
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- regulators
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmic@69 {
|
||||
compatible = "mps,mp5416";
|
||||
reg = <0x69>;
|
||||
|
||||
regulators {
|
||||
|
||||
buck1 {
|
||||
regulator-name = "buck1";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-min-microamp = <3800000>;
|
||||
regulator-max-microamp = <6800000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3975000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -22,6 +22,7 @@ properties:
|
||||
enum:
|
||||
- amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs
|
||||
- amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs
|
||||
- amlogic,meson-g12a-spicc # SPICC controller on Amlogic G12A and compatible SoCs
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
@@ -40,6 +41,27 @@ properties:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- amlogic,meson-g12a-spicc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
contains:
|
||||
items:
|
||||
- description: controller register bus clock
|
||||
- description: baud rate generator and delay control clock
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: core
|
||||
- const: pclk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -10,7 +10,10 @@ Required properties:
|
||||
- "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
|
||||
- "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
|
||||
- "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
|
||||
- "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M
|
||||
- "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8MQ
|
||||
- "fsl,imx8mm-ecspi" for SPI compatible with the one integrated on i.MX8MM
|
||||
- "fsl,imx8mn-ecspi" for SPI compatible with the one integrated on i.MX8MN
|
||||
- "fsl,imx8mp-ecspi" for SPI compatible with the one integrated on i.MX8MP
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : Should contain CSPI/eCSPI interrupt
|
||||
- clocks : Clock specifiers for both ipg and per clocks.
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/spi/qca,ar934x-spi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Atheros AR934x/QCA95xx SoC SPI controller
|
||||
|
||||
maintainers:
|
||||
- Chuanhong Guo <gch981213@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: spi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qca,ar934x-spi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/ath79-clk.h>
|
||||
spi: spi@1f000000 {
|
||||
compatible = "qca,ar934x-spi";
|
||||
reg = <0x1f000000 0x1c>;
|
||||
clocks = <&pll ATH79_CLK_AHB>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
@@ -52,6 +52,12 @@ properties:
|
||||
description:
|
||||
The SPI controller acts as a slave, instead of a master.
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
- "#address-cells"
|
||||
- required:
|
||||
- spi-slave
|
||||
|
||||
patternProperties:
|
||||
"^slave$":
|
||||
type: object
|
||||
@@ -114,7 +120,7 @@ patternProperties:
|
||||
- enum: [ 1, 2, 4, 8 ]
|
||||
- default: 1
|
||||
description:
|
||||
Bus width to the SPI bus used for MISO.
|
||||
Bus width to the SPI bus used for read transfers.
|
||||
|
||||
spi-rx-delay-us:
|
||||
description:
|
||||
@@ -126,7 +132,7 @@ patternProperties:
|
||||
- enum: [ 1, 2, 4, 8 ]
|
||||
- default: 1
|
||||
description:
|
||||
Bus width to the SPI bus used for MOSI.
|
||||
Bus width to the SPI bus used for write transfers.
|
||||
|
||||
spi-tx-delay-us:
|
||||
description:
|
||||
|
||||
@@ -1,12 +1,17 @@
|
||||
ARM Freescale DSPI controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
|
||||
"fsl,ls2085a-dspi"
|
||||
or
|
||||
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
|
||||
"fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
|
||||
"fsl,ls1088a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
|
||||
- compatible : must be one of:
|
||||
"fsl,vf610-dspi",
|
||||
"fsl,ls1021a-v1.0-dspi",
|
||||
"fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
|
||||
"fsl,ls1028a-dspi",
|
||||
"fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
|
||||
"fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
|
||||
"fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
|
||||
"fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
|
||||
"fsl,ls2085a-dspi",
|
||||
"fsl,lx2160a-dspi",
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : Should contain SPI controller interrupt
|
||||
- clocks: from common clock binding: handle to dspi clock.
|
||||
@@ -14,11 +19,11 @@ Required properties:
|
||||
- pinctrl-0: pin control group to be used for this controller.
|
||||
- pinctrl-names: must contain a "default" entry.
|
||||
- spi-num-chipselects : the number of the chipselect signals.
|
||||
- bus-num : the slave chip chipselect signal number.
|
||||
|
||||
Optional property:
|
||||
- big-endian: If present the dspi device's registers are implemented
|
||||
in big endian mode.
|
||||
- bus-num : the slave chip chipselect signal number.
|
||||
|
||||
Optional SPI slave node properties:
|
||||
- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
|
||||
|
||||
+6
-9
@@ -1,4 +1,4 @@
|
||||
* Serial NOR flash controller for MediaTek SoCs
|
||||
* Serial NOR flash controller for MediaTek ARM SoCs
|
||||
|
||||
Required properties:
|
||||
- compatible: For mt8173, compatible should be "mediatek,mt8173-nor",
|
||||
@@ -13,6 +13,7 @@ Required properties:
|
||||
"mediatek,mt7629-nor", "mediatek,mt8173-nor"
|
||||
"mediatek,mt8173-nor"
|
||||
- reg: physical base address and length of the controller's register
|
||||
- interrupts: Interrupt number used by the controller.
|
||||
- clocks: the phandle of the clocks needed by the nor controller
|
||||
- clock-names: the names of the clocks
|
||||
the clocks should be named "spi" and "sf". "spi" is used for spi bus,
|
||||
@@ -22,20 +23,16 @@ Required properties:
|
||||
- #address-cells: should be <1>
|
||||
- #size-cells: should be <0>
|
||||
|
||||
The SPI flash must be a child of the nor_flash node and must have a
|
||||
compatible property. Also see jedec,spi-nor.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible: May include a device-specific string consisting of the manufacturer
|
||||
and name of the chip. Must also include "jedec,spi-nor" for any
|
||||
SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F).
|
||||
- reg : Chip-Select number
|
||||
There should be only one spi slave device following generic spi bindings.
|
||||
It's not recommended to use this controller for devices other than SPI NOR
|
||||
flash due to limited transfer capability of this controller.
|
||||
|
||||
Example:
|
||||
|
||||
nor_flash: spi@1100d000 {
|
||||
compatible = "mediatek,mt8173-nor";
|
||||
reg = <0 0x1100d000 0 0xe0>;
|
||||
interrupts = <&spi_flash_irq>;
|
||||
clocks = <&pericfg CLK_PERI_SPI>,
|
||||
<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
|
||||
clock-names = "spi", "sf";
|
||||
@@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/spi/spi-mux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Generic SPI Multiplexer
|
||||
|
||||
description: |
|
||||
This binding describes a SPI bus multiplexer to route the SPI chip select
|
||||
signals. This can be used when you need more devices than the SPI controller
|
||||
has chip selects available. An example setup is shown in ASCII art; the actual
|
||||
setting of the multiplexer to a channel needs to be done by a specific SPI mux
|
||||
driver.
|
||||
|
||||
MOSI /--------------------------------+--------+--------+--------\
|
||||
MISO |/------------------------------+|-------+|-------+|-------\|
|
||||
SCL ||/----------------------------+||------+||------+||------\||
|
||||
||| ||| ||| ||| |||
|
||||
+------------+ ||| ||| ||| |||
|
||||
| SoC ||| | +-+++-+ +-+++-+ +-+++-+ +-+++-+
|
||||
| ||| | | dev | | dev | | dev | | dev |
|
||||
| +--+++-+ | CS-X +------+\ +--+--+ +--+--+ +--+--+ +--+--+
|
||||
| | SPI +-|-------+ Mux |\\ CS-0 | | | |
|
||||
| +------+ | +--+---+\\\-------/ CS-1 | | |
|
||||
| | | \\\----------------/ CS-2 | |
|
||||
| +------+ | | \\-------------------------/ CS-3 |
|
||||
| | ? +-|----------/ \----------------------------------/
|
||||
| +------+ |
|
||||
+------------+
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/spi/spi-controller.yaml#"
|
||||
|
||||
maintainers:
|
||||
- Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spi-mux
|
||||
|
||||
mux-controls:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-max-frequency
|
||||
- mux-controls
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
spi@0 {
|
||||
compatible = "spi-mux";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
mux-controls = <&mux>;
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
|
||||
spi-device@1 {
|
||||
compatible = "lineartechnology,ltc2488";
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -2,6 +2,9 @@
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "nxp,lx2160a-fspi"
|
||||
"nxp,imx8qxp-fspi"
|
||||
"nxp,imx8mm-fspi"
|
||||
|
||||
- reg : First contains the register location and length,
|
||||
Second contains the memory mapping address and length
|
||||
- reg-names : Should contain the resource reg names:
|
||||
|
||||
@@ -1,58 +0,0 @@
|
||||
* Rockchip SPI Controller
|
||||
|
||||
The Rockchip SPI controller is used to interface with various devices such as flash
|
||||
and display controllers using the SPI communication interface.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
"rockchip,rv1108-spi" for rv1108 SoCs.
|
||||
"rockchip,px30-spi", "rockchip,rk3066-spi" for px30 SoCs.
|
||||
"rockchip,rk3036-spi" for rk3036 SoCS.
|
||||
"rockchip,rk3066-spi" for rk3066 SoCs.
|
||||
"rockchip,rk3188-spi" for rk3188 SoCs.
|
||||
"rockchip,rk3228-spi" for rk3228 SoCS.
|
||||
"rockchip,rk3288-spi" for rk3288 SoCs.
|
||||
"rockchip,rk3368-spi" for rk3368 SoCs.
|
||||
"rockchip,rk3399-spi" for rk3399 SoCs.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: The interrupt number to the cpu. The interrupt specifier format
|
||||
depends on the interrupt controller.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
- clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for
|
||||
the peripheral clock.
|
||||
- #address-cells: should be 1.
|
||||
- #size-cells: should be 0.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names: DMA request names should include "tx" and "rx" if present.
|
||||
- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
|
||||
Rx data (may need to be fine tuned for high capacitance lines).
|
||||
No delay (0) by default.
|
||||
- pinctrl-names: Names for the pin configuration(s); may be "default" or
|
||||
"sleep", where the "sleep" configuration may describe the state
|
||||
the pins should be in during system suspend. See also
|
||||
pinctrl/pinctrl-bindings.txt.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
spi0: spi@ff110000 {
|
||||
compatible = "rockchip,rk3066-spi";
|
||||
reg = <0xff110000 0x1000>;
|
||||
dmas = <&pdma1 11>, <&pdma1 12>;
|
||||
dma-names = "tx", "rx";
|
||||
rx-sample-delay-ns = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-1 = <&spi1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
};
|
||||
@@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip SPI Controller
|
||||
|
||||
description:
|
||||
The Rockchip SPI controller is used to interface with various devices such
|
||||
as flash and display controllers using the SPI communication interface.
|
||||
|
||||
allOf:
|
||||
- $ref: "spi-controller.yaml#"
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
# Everything else is described in the common file
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: rockchip,rk3036-spi
|
||||
- const: rockchip,rk3066-spi
|
||||
- const: rockchip,rk3228-spi
|
||||
- const: rockchip,rv1108-spi
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,px30-spi
|
||||
- rockchip,rk3188-spi
|
||||
- rockchip,rk3288-spi
|
||||
- rockchip,rk3308-spi
|
||||
- rockchip,rk3328-spi
|
||||
- rockchip,rk3368-spi
|
||||
- rockchip,rk3399-spi
|
||||
- const: rockchip,rk3066-spi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: transfer-clock
|
||||
- description: peripheral clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: spiclk
|
||||
- const: apb_pclk
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: TX DMA Channel
|
||||
- description: RX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
rx-sample-delay-ns:
|
||||
default: 0
|
||||
description:
|
||||
Nano seconds to delay after the SCLK edge before sampling Rx data
|
||||
(may need to be fine tuned for high capacitance lines).
|
||||
If not specified 0 will be used.
|
||||
|
||||
pinctrl-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: default
|
||||
- const: sleep
|
||||
description:
|
||||
Names for the pin configuration(s); may be "default" or "sleep",
|
||||
where the "sleep" configuration may describe the state
|
||||
the pins should be in during system suspend.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3188-cru-common.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi0: spi@ff110000 {
|
||||
compatible = "rockchip,rk3066-spi";
|
||||
reg = <0xff110000 0x1000>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
dmas = <&pdma1 11>, <&pdma1 12>;
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-1 = <&spi1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
rx-sample-delay-ns = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
+10
-1
@@ -2276,6 +2276,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
|
||||
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
|
||||
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
|
||||
F: arch/arm/boot/dts/rk3*
|
||||
F: arch/arm/boot/dts/rv1108*
|
||||
F: arch/arm/mach-rockchip/
|
||||
@@ -6858,6 +6859,13 @@ S: Maintained
|
||||
F: drivers/i2c/busses/i2c-fsi.c
|
||||
F: Documentation/devicetree/bindings/i2c/i2c-fsi.txt
|
||||
|
||||
FSI-ATTACHED SPI DRIVER
|
||||
M: Eddie James <eajames@linux.ibm.com>
|
||||
L: linux-spi@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/spi/spi-fsi.c
|
||||
F: Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml
|
||||
|
||||
FSNOTIFY: FILESYSTEM NOTIFICATION INFRASTRUCTURE
|
||||
M: Jan Kara <jack@suse.cz>
|
||||
R: Amir Goldstein <amir73il@gmail.com>
|
||||
@@ -11256,7 +11264,8 @@ F: drivers/tty/mxser.*
|
||||
MONOLITHIC POWER SYSTEM PMIC DRIVER
|
||||
M: Saravanan Sekar <sravanhome@gmail.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/regulator/mpq7920.yaml
|
||||
F: Documentation/devicetree/bindings/regulator/mps,mp*.yaml
|
||||
F: drivers/regulator/mp5416.c
|
||||
F: drivers/regulator/mpq7920.c
|
||||
F: drivers/regulator/mpq7920.h
|
||||
|
||||
|
||||
@@ -52,14 +52,6 @@ config SPI_HISI_SFC
|
||||
help
|
||||
This enables support for HiSilicon FMC SPI-NOR flash controller.
|
||||
|
||||
config SPI_MTK_QUADSPI
|
||||
tristate "MediaTek Quad SPI controller"
|
||||
depends on HAS_IOMEM
|
||||
help
|
||||
This enables support for the Quad SPI controller in master mode.
|
||||
This controller does not support generic SPI. It only supports
|
||||
SPI NOR.
|
||||
|
||||
config SPI_NXP_SPIFI
|
||||
tristate "NXP SPI Flash Interface (SPIFI)"
|
||||
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
|
||||
|
||||
@@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
|
||||
obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
|
||||
obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
|
||||
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
|
||||
obj-$(CONFIG_SPI_MTK_QUADSPI) += mtk-quadspi.o
|
||||
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
|
||||
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
|
||||
obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -107,6 +107,7 @@ config REGULATOR_AD5398
|
||||
|
||||
config REGULATOR_ANATOP
|
||||
tristate "Freescale i.MX on-chip ANATOP LDO regulators"
|
||||
depends on ARCH_MXC || COMPILE_TEST
|
||||
depends on MFD_SYSCON
|
||||
help
|
||||
Say y here to support Freescale i.MX on-chip ANATOP LDOs
|
||||
@@ -613,6 +614,16 @@ config REGULATOR_MCP16502
|
||||
through the regulator interface. In addition it enables
|
||||
suspend-to-ram/standby transition.
|
||||
|
||||
config REGULATOR_MP5416
|
||||
tristate "Monolithic MP5416 PMIC"
|
||||
depends on I2C && OF
|
||||
select REGMAP_I2C
|
||||
help
|
||||
Say y here to support the MP5416 PMIC. This will enable supports
|
||||
the software controllable 4 buck and 4 LDO regulators.
|
||||
Say M here if you want to include support for the regulator as a
|
||||
module.
|
||||
|
||||
config REGULATOR_MP8859
|
||||
tristate "MPS MP8859 regulator driver"
|
||||
depends on I2C
|
||||
|
||||
@@ -78,6 +78,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
|
||||
obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
|
||||
obj-$(CONFIG_REGULATOR_MCP16502) += mcp16502.o
|
||||
obj-$(CONFIG_REGULATOR_MP5416) += mp5416.o
|
||||
obj-$(CONFIG_REGULATOR_MP8859) += mp8859.o
|
||||
obj-$(CONFIG_REGULATOR_MPQ7920) += mpq7920.o
|
||||
obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
|
||||
|
||||
@@ -305,9 +305,13 @@ static int anatop_regulator_probe(struct platform_device *pdev)
|
||||
/* register regulator */
|
||||
rdev = devm_regulator_register(dev, rdesc, &config);
|
||||
if (IS_ERR(rdev)) {
|
||||
dev_err(dev, "failed to register %s\n",
|
||||
rdesc->name);
|
||||
return PTR_ERR(rdev);
|
||||
ret = PTR_ERR(rdev);
|
||||
if (ret == -EPROBE_DEFER)
|
||||
dev_dbg(dev, "failed to register %s, deferring...\n",
|
||||
rdesc->name);
|
||||
else
|
||||
dev_err(dev, "failed to register %s\n", rdesc->name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, rdev);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user