mirror of
https://github.com/usetrmnl/bb_epaper.git
synced 2026-04-29 13:43:26 -07:00
Added CH32V003 demo
This commit is contained in:
Larry Bank
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/*
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* ch32v_io.inl
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*
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* Created on: Jan 12, 2023
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* Author: larry
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*/
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// GPIO pin states
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enum {
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OUTPUT = 0,
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INPUT,
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INPUT_PULLUP,
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INPUT_PULLDOWN
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};
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#define LOW 0
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#define HIGH 1
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#define PROGMEM
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#define memcpy_P memcpy
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#define pgm_read_byte(s) *(uint8_t *)s
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#define pgm_read_word(s) *(uint16_t *)s
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#define pgm_read_dword(s) *(uint32_t *)s
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void delay(int i)
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{
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Delay_Ms(i);
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}
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// Arduino-like API defines and function wrappers for WCH MCUs
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void pinMode(uint8_t u8Pin, int iMode)
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{
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GPIO_InitTypeDef GPIO_InitStructure = {0};
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if (u8Pin < 0xa0 || u8Pin > 0xdf) return; // invalid pin number
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 << (u8Pin & 0xf);
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if (iMode == OUTPUT)
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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else if (iMode == INPUT)
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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else if (iMode == INPUT_PULLUP)
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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else if (iMode == INPUT_PULLDOWN)
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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switch (u8Pin & 0xf0) {
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case 0xa0:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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break;
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case 0xc0:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
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GPIO_Init(GPIOC, &GPIO_InitStructure);
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break;
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case 0xd0:
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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break;
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}
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} /* pinMode() */
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uint8_t digitalRead(uint8_t u8Pin)
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{
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uint8_t u8GPIO = GPIO_Pin_0 << (u8Pin & 0xf);
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uint8_t u8Value = 0;
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switch (u8Pin & 0xf0) {
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case 0xa0:
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u8Value = GPIO_ReadInputDataBit(GPIOA, u8GPIO);
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break;
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case 0xc0:
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u8Value = GPIO_ReadInputDataBit(GPIOC, u8GPIO);
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break;
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case 0xd0:
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u8Value = GPIO_ReadInputDataBit(GPIOD, u8GPIO);
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break;
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}
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return u8Value;
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} /* digitalRead() */
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void digitalWrite(uint8_t u8Pin, uint8_t u8Value)
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{
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uint8_t u8GPIO = GPIO_Pin_0 << (u8Pin & 0xf);
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u8Value = (u8Value) ? Bit_SET : Bit_RESET;
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switch (u8Pin & 0xf0) {
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case 0xa0:
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GPIO_WriteBit(GPIOA, u8GPIO, u8Value);
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break;
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case 0xc0:
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GPIO_WriteBit(GPIOC, u8GPIO, u8Value);
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break;
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case 0xd0:
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GPIO_WriteBit(GPIOD, u8GPIO, u8Value);
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break;
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}
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} /* digitalWrite() */
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void I2CInit(int iSpeed)
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{
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GPIO_InitTypeDef GPIO_InitStructure={0};
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I2C_InitTypeDef I2C_InitTSturcture={0};
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// Fixed to pins C1/C2 for now
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RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE );
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RCC_APB1PeriphClockCmd( RCC_APB1Periph_I2C1, ENABLE );
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init( GPIOC, &GPIO_InitStructure );
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init( GPIOC, &GPIO_InitStructure );
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I2C_InitTSturcture.I2C_ClockSpeed = iSpeed;
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I2C_InitTSturcture.I2C_Mode = I2C_Mode_I2C;
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I2C_InitTSturcture.I2C_DutyCycle = I2C_DutyCycle_16_9;
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I2C_InitTSturcture.I2C_OwnAddress1 = 0x02; //address; sender's unimportant address
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I2C_InitTSturcture.I2C_Ack = I2C_Ack_Enable;
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I2C_InitTSturcture.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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I2C_Init( I2C1, &I2C_InitTSturcture );
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I2C_Cmd( I2C1, ENABLE );
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I2C_AcknowledgeConfig( I2C1, ENABLE );
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while( I2C_GetFlagStatus( I2C1, I2C_FLAG_BUSY ) != RESET );
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} /* I2CInit() */
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void I2CRead(uint8_t u8Addr, uint8_t *pData, int iLen)
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{
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I2C_GenerateSTART( I2C1, ENABLE );
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while( !I2C_CheckEvent( I2C1, I2C_EVENT_MASTER_MODE_SELECT ) );
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I2C_Send7bitAddress( I2C1, u8Addr<<1, I2C_Direction_Receiver );
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while( !I2C_CheckEvent( I2C1, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) );
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while(iLen)
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{
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if( I2C_GetFlagStatus( I2C1, I2C_FLAG_RXNE ) != RESET )
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{
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pData[0] = I2C_ReceiveData( I2C1 );
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pData++;
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iLen--;
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}
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}
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I2C_GenerateSTOP( I2C1, ENABLE );
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} /* I2CRead() */
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void I2CWrite(uint8_t u8Addr, uint8_t *pData, int iLen)
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{
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I2C_GenerateSTART( I2C1, ENABLE );
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while( !I2C_CheckEvent( I2C1, I2C_EVENT_MASTER_MODE_SELECT ) );
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I2C_Send7bitAddress( I2C1, u8Addr<<1, I2C_Direction_Transmitter );
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while( !I2C_CheckEvent( I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ) );
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while(iLen)
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{
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if( I2C_GetFlagStatus( I2C1, I2C_FLAG_TXE ) != RESET )
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{
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I2C_SendData( I2C1, pData[0] );
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pData++;
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iLen--;
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}
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}
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while( !I2C_CheckEvent( I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
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I2C_GenerateSTOP( I2C1, ENABLE );
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} /* I2CWrite() */
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int I2CTest(uint8_t u8Addr)
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{
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I2C_GenerateSTART( I2C1, ENABLE );
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while( !I2C_CheckEvent( I2C1, I2C_EVENT_MASTER_MODE_SELECT ) );
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I2C_Send7bitAddress( I2C1, u8Addr<<1, I2C_Direction_Transmitter );
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while( !I2C_CheckEvent( I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ) );
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I2C_GenerateSTOP( I2C1, ENABLE );
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return (I2C_GetFlagStatus(I2C1, I2C_FLAG_TXE) != RESET); // 0 = fail, 1 = succeed
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} /* I2CTest() */
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// Put CPU into standby mode for a multiple of 82ms tick increments
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// max ticks value is 63
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void Standby82ms(uint8_t iTicks)
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{
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EXTI_InitTypeDef EXTI_InitStructure = {0};
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GPIO_InitTypeDef GPIO_InitStructure = {0};
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// init external interrupts
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
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EXTI_InitStructure.EXTI_Line = EXTI_Line9;
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EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Event;
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EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
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EXTI_InitStructure.EXTI_LineCmd = ENABLE;
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EXTI_Init(&EXTI_InitStructure);
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// Init GPIOs
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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GPIO_Init(GPIOC, &GPIO_InitStructure);
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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// init wake up timer and enter standby mode
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RCC_LSICmd(ENABLE);
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while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET);
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PWR_AWU_SetPrescaler(PWR_AWU_Prescaler_10240);
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PWR_AWU_SetWindowValue(iTicks);
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PWR_AutoWakeUpCmd(ENABLE);
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PWR_EnterSTANDBYMode(PWR_STANDBYEntry_WFE);
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GPIO_DeInit(GPIOA);
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GPIO_DeInit(GPIOC);
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GPIO_DeInit(GPIOD);
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} /* Standby82ms() */
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//
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// Ramp an LED brightness with PWM from 0 to 50%
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// The period represents the total up+down time in milliseconds
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//
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void breatheLED(uint8_t u8Pin, int iPeriod)
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{
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int i, j, iStep, iCount, iOnTime;
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pinMode(u8Pin, OUTPUT);
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// Use a pwm freq of 1000hz and 50 steps up then 50 steps down
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iStep = 10000/iPeriod; // us per step
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iCount = iPeriod / 20;
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// ramp up
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iOnTime = 0;
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for (i=0; i<iCount; i++) {
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for (j=0; j<20; j++) { // 20ms per step
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digitalWrite(u8Pin, 1); // on period
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Delay_Us(iOnTime);
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digitalWrite(u8Pin, 0); // off period
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Delay_Us(1000 - iOnTime);
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} // for j
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iOnTime += iStep;
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} // for i
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// ramp down
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iOnTime = 500;
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for (i=0; i<iCount; i++) {
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for (j=0; j<20; j++) { // 20ms per step
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digitalWrite(u8Pin, 1); // on period
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Delay_Us(iOnTime);
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digitalWrite(u8Pin, 0); // off period
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Delay_Us(1000 - iOnTime);
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} // for j
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iOnTime -= iStep;
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} // for i
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} /* breatheLED() */
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void SPI_begin(int iSpeed, int iMode)
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{
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GPIO_InitTypeDef GPIO_InitStructure={0};
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SPI_InitTypeDef SPI_InitStructure={0};
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RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOC | RCC_APB2Periph_SPI1, ENABLE );
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init( GPIOC, &GPIO_InitStructure );
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init( GPIOC, &GPIO_InitStructure );
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SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
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SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
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SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
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SPI_InitStructure.SPI_CPOL = (iMode & 2) ? SPI_CPOL_High : SPI_CPOL_Low;
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SPI_InitStructure.SPI_CPHA = (iMode & 1) ? SPI_CPHA_2Edge : SPI_CPHA_1Edge;
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SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
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if (iSpeed >= (SystemCoreClock/2))
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
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else if (iSpeed >= (SystemCoreClock/4))
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
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else if (iSpeed >= (SystemCoreClock/8))
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
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else if (iSpeed >= (SystemCoreClock/16))
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
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else if (iSpeed >= (SystemCoreClock/32))
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;
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else if (iSpeed >= (SystemCoreClock/64))
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
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else if (iSpeed >= (SystemCoreClock/128))
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_128;
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else
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
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SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
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SPI_InitStructure.SPI_CRCPolynomial = 7;
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SPI_Init( SPI1, &SPI_InitStructure );
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SPI_Cmd( SPI1, ENABLE );
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} /* SPI_begin() */
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// polling write
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void SPI_write(uint8_t *pData, int iLen)
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{
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int i = 0;
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while (i < iLen)
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{
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if ( SPI_I2S_GetFlagStatus( SPI1, SPI_I2S_FLAG_TXE ) != RESET )
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SPI_I2S_SendData( SPI1, pData[i++] );
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}
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// wait until transmit empty flag is true
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while (SPI_I2S_GetFlagStatus( SPI1, SPI_I2S_FLAG_TXE ) == RESET)
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{};
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while (SPI_I2S_GetFlagStatus( SPI1, SPI_I2S_FLAG_BSY ) == SET)
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{}; // wait until it's not busy
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} /* SPI_write() */
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// foreward references
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void bbepWakeUp(BBEPDISP *pBBEP);
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//
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// Initialize the GPIO pins and SPI for use by bb_eink
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//
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void bbepInitIO(BBEPDISP *pBBEP, uint8_t u8DC, uint8_t u8RST, uint8_t u8BUSY, uint8_t u8CS, uint8_t u8MOSI, uint8_t u8SCK, uint32_t u32Speed)
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{
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pBBEP->iDCPin = u8DC;
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pBBEP->iCSPin = u8CS;
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pBBEP->iMOSIPin = u8MOSI;
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pBBEP->iCLKPin = u8SCK;
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pBBEP->iRSTPin = u8RST;
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pBBEP->iBUSYPin = u8BUSY;
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pinMode(pBBEP->iDCPin, OUTPUT);
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pinMode(pBBEP->iRSTPin, OUTPUT);
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digitalWrite(pBBEP->iRSTPin, LOW);
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delay(100);
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digitalWrite(pBBEP->iRSTPin, HIGH);
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delay(100);
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if (pBBEP->iBUSYPin != 0xff) {
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pinMode(pBBEP->iBUSYPin, INPUT);
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}
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pBBEP->iSpeed = u32Speed;
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pinMode(pBBEP->iCSPin, OUTPUT);
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digitalWrite(pBBEP->iCSPin, HIGH); // we have to manually control the CS pin
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SPI_begin(u32Speed, 0);
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} /* bbepInitIO() */
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//
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// Convenience function to write a command byte along with a data
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// byte (it's single parameter)
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//
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void bbepCMD2(BBEPDISP *pBBEP, uint8_t cmd1, uint8_t cmd2)
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{
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if (!pBBEP->is_awake) {
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// if it's asleep, it can't receive commands
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bbepWakeUp(pBBEP);
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pBBEP->is_awake = 1;
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}
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digitalWrite(pBBEP->iDCPin, LOW);
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digitalWrite(pBBEP->iCSPin, LOW);
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SPI_write(&cmd1, 1);
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digitalWrite(pBBEP->iDCPin, HIGH);
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SPI_write(&cmd2, 1); // second byte is data
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digitalWrite(pBBEP->iCSPin, HIGH);
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} /* bbepCMD2() */
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//
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// Write a single byte as a COMMAND (D/C set low)
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//
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void bbepWriteCmd(BBEPDISP *pBBEP, uint8_t cmd)
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{
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if (!pBBEP->is_awake) {
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// if it's asleep, it can't receive commands
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bbepWakeUp(pBBEP);
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pBBEP->is_awake = 1;
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}
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digitalWrite(pBBEP->iDCPin, LOW);
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digitalWrite(pBBEP->iCSPin, LOW);
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SPI_write(&cmd, 1);
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digitalWrite(pBBEP->iCSPin, HIGH);
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digitalWrite(pBBEP->iDCPin, HIGH); // leave data mode as the default
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} /* bbepWriteCmd() */
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//
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// Write 1 or more bytes as DATA (D/C set high)
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//
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void bbepWriteData(BBEPDISP *pBBEP, uint8_t *pData, int iLen)
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{
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digitalWrite(pBBEP->iCSPin, LOW);
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SPI_write(pData, iLen);
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digitalWrite(pBBEP->iCSPin, HIGH);
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} /* bbepWriteData() */
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@@ -0,0 +1,276 @@
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/********************************** (C) COPYRIGHT *******************************
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||||
* File Name : core_riscv.c
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||||
* Author : WCH
|
||||
* Version : V1.0.1
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||||
* Date : 2023/11/11
|
||||
* Description : RISC-V V2 Core Peripheral Access Layer Source File for CH32V003
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/* define compiler specific symbols */
|
||||
#if defined(__CC_ARM)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
|
||||
#elif defined(__TASKING__)
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSTATUS
|
||||
*
|
||||
* @brief Return the Machine Status Register
|
||||
*
|
||||
* @return mstatus value
|
||||
*/
|
||||
uint32_t __get_MSTATUS(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mstatus": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSTATUS
|
||||
*
|
||||
* @brief Set the Machine Status Register
|
||||
*
|
||||
* @param value - set mstatus value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSTATUS(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mstatus, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MISA
|
||||
*
|
||||
* @brief Return the Machine ISA Register
|
||||
*
|
||||
* @return misa value
|
||||
*/
|
||||
uint32_t __get_MISA(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""misa" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MISA
|
||||
*
|
||||
* @brief Set the Machine ISA Register
|
||||
*
|
||||
* @param value - set misa value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MISA(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw misa, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MTVEC
|
||||
*
|
||||
* @brief Return the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @return mtvec value
|
||||
*/
|
||||
uint32_t __get_MTVEC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mtvec": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MTVEC
|
||||
*
|
||||
* @brief Set the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @param value - set mtvec value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MTVEC(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mtvec, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSCRATCH
|
||||
*
|
||||
* @brief Return the Machine Seratch Register
|
||||
*
|
||||
* @return mscratch value
|
||||
*/
|
||||
uint32_t __get_MSCRATCH(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mscratch" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSCRATCH
|
||||
*
|
||||
* @brief Set the Machine Seratch Register
|
||||
*
|
||||
* @param value - set mscratch value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSCRATCH(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mscratch, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MEPC
|
||||
*
|
||||
* @brief Return the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
uint32_t __get_MEPC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mepc" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
void __set_MEPC(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mepc, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MCAUSE
|
||||
*
|
||||
* @brief Return the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
uint32_t __get_MCAUSE(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mcause": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
void __set_MCAUSE(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mcause, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MVENDORID
|
||||
*
|
||||
* @brief Return Vendor ID Register
|
||||
*
|
||||
* @return mvendorid value
|
||||
*/
|
||||
uint32_t __get_MVENDORID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mvendorid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MARCHID
|
||||
*
|
||||
* @brief Return Machine Architecture ID Register
|
||||
*
|
||||
* @return marchid value
|
||||
*/
|
||||
uint32_t __get_MARCHID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""marchid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MIMPID
|
||||
*
|
||||
* @brief Return Machine Implementation ID Register
|
||||
*
|
||||
* @return mimpid value
|
||||
*/
|
||||
uint32_t __get_MIMPID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mimpid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MHARTID
|
||||
*
|
||||
* @brief Return Hart ID Register
|
||||
*
|
||||
* @return mhartid value
|
||||
*/
|
||||
uint32_t __get_MHARTID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mhartid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_SP
|
||||
*
|
||||
* @brief Return SP Register
|
||||
*
|
||||
* @return SP value
|
||||
*/
|
||||
uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("mv %0,""sp": "=r"(result):);
|
||||
return (result);
|
||||
}
|
||||
@@ -0,0 +1,401 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2023/12/21
|
||||
* Description : RISC-V V2 Core Peripheral Access Layer Header File for CH32V003
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CORE_RISCV_H__
|
||||
#define __CORE_RISCV_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* IO definitions */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /* defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /* defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /* defines 'write only' permissions */
|
||||
#define __IO volatile /* defines 'read / write' permissions */
|
||||
|
||||
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||
typedef __I uint32_t vuc32; /* Read Only */
|
||||
typedef __I uint16_t vuc16; /* Read Only */
|
||||
typedef __I uint8_t vuc8; /* Read Only */
|
||||
|
||||
typedef const uint32_t uc32; /* Read Only */
|
||||
typedef const uint16_t uc16; /* Read Only */
|
||||
typedef const uint8_t uc8; /* Read Only */
|
||||
|
||||
typedef __I int32_t vsc32; /* Read Only */
|
||||
typedef __I int16_t vsc16; /* Read Only */
|
||||
typedef __I int8_t vsc8; /* Read Only */
|
||||
|
||||
typedef const int32_t sc32; /* Read Only */
|
||||
typedef const int16_t sc16; /* Read Only */
|
||||
typedef const int8_t sc8; /* Read Only */
|
||||
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
|
||||
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
#define RV_STATIC_INLINE static inline
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
__IO uint32_t RESERVED;
|
||||
__IO uint32_t CFGR;
|
||||
__I uint32_t GISR;
|
||||
__IO uint8_t VTFIDR[4];
|
||||
uint8_t RESERVED0[12];
|
||||
__IO uint32_t VTFADDR[4];
|
||||
uint8_t RESERVED1[0x90];
|
||||
__O uint32_t IENR[8];
|
||||
uint8_t RESERVED2[0x60];
|
||||
__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
|
||||
__IO uint32_t SCTLR;
|
||||
}PFIC_Type;
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTLR;
|
||||
__IO uint32_t SR;
|
||||
__IO uint32_t CNT;
|
||||
uint32_t RESERVED0;
|
||||
__IO uint32_t CMP;
|
||||
uint32_t RESERVED1;
|
||||
}SysTick_Type;
|
||||
|
||||
|
||||
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
|
||||
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __enable_irq
|
||||
* This function is only used for Machine mode.
|
||||
*
|
||||
* @brief Enable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
|
||||
{
|
||||
__asm volatile ("csrs mstatus, %0" : : "r" (0x88) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __disable_irq
|
||||
* This function is only used for Machine mode.
|
||||
*
|
||||
* @brief Disable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
|
||||
{
|
||||
__asm volatile ("csrc mstatus, %0" : : "r" (0x88) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __NOP
|
||||
*
|
||||
* @brief nop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
|
||||
{
|
||||
__asm volatile ("nop");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_EnableIRQ
|
||||
*
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_DisableIRQ
|
||||
*
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetStatusIRQ
|
||||
*
|
||||
* @brief Get Interrupt Enable State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetPendingIRQ
|
||||
*
|
||||
* @brief Get Interrupt Pending State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPendingIRQ
|
||||
*
|
||||
* @brief Set Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_ClearPendingIRQ
|
||||
*
|
||||
* @brief Clear Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetActive
|
||||
*
|
||||
* @brief Get Interrupt Active State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Active
|
||||
* 0 - Interrupt No Active
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPriority
|
||||
*
|
||||
* @brief Set Interrupt Priority
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
* interrupt nesting enable(CSR-0x804 bit1 = 1)
|
||||
* priority - bit[7] - Preemption Priority
|
||||
* bit[6] - Sub priority
|
||||
* bit[5:0] - Reserve
|
||||
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||
* priority - bit[7:6] - Sub priority
|
||||
* bit[5:0] - Reserve
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFI
|
||||
*
|
||||
* @brief Wait for Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _SEV
|
||||
*
|
||||
* @brief Set Event
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->SCTLR;
|
||||
NVIC->SCTLR |= (1<<3)|(1<<5);
|
||||
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
|
||||
{
|
||||
NVIC->SCTLR |= (1<<3);
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
_SEV();
|
||||
_WFE();
|
||||
_WFE();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetVTFIRQ
|
||||
*
|
||||
* @brief Set VTF Interrupt
|
||||
*
|
||||
* @param addr - VTF interrupt service function base address.
|
||||
* IRQn - Interrupt Numbers
|
||||
* num - VTF Interrupt Numbers
|
||||
* NewState - DISABLE or ENABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
|
||||
{
|
||||
if(num > 1) return ;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SystemReset
|
||||
*
|
||||
* @brief Initiate a system reset request
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||
}
|
||||
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif/* __CORE_RISCV_H__ */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,242 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : debug.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for UART
|
||||
* Printf , Delay functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include <debug.h>
|
||||
|
||||
static uint8_t p_us = 0;
|
||||
static uint16_t p_ms = 0;
|
||||
|
||||
#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE00000F4)
|
||||
#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE00000F8)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Init
|
||||
*
|
||||
* @brief Initializes Delay Funcation.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void Delay_Init(void)
|
||||
{
|
||||
p_us = SystemCoreClock / 8000000;
|
||||
p_ms = (uint16_t)p_us * 1000;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Us
|
||||
*
|
||||
* @brief Microsecond Delay Time.
|
||||
*
|
||||
* @param n - Microsecond number.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Delay_Us(uint32_t n)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
SysTick->SR &= ~(1 << 0);
|
||||
i = (uint32_t)n * p_us;
|
||||
|
||||
SysTick->CMP = i;
|
||||
SysTick->CNT = 0;
|
||||
SysTick->CTLR |=(1 << 0);
|
||||
|
||||
while((SysTick->SR & (1 << 0)) != (1 << 0));
|
||||
SysTick->CTLR &= ~(1 << 0);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Ms
|
||||
*
|
||||
* @brief Millisecond Delay Time.
|
||||
*
|
||||
* @param n - Millisecond number.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Delay_Ms(uint32_t n)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
SysTick->SR &= ~(1 << 0);
|
||||
i = (uint32_t)n * p_ms;
|
||||
|
||||
SysTick->CMP = i;
|
||||
SysTick->CNT = 0;
|
||||
SysTick->CTLR |=(1 << 0);
|
||||
|
||||
while((SysTick->SR & (1 << 0)) != (1 << 0));
|
||||
SysTick->CTLR &= ~(1 << 0);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Printf_Init
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral.
|
||||
*
|
||||
* @param baudrate - USART communication baud rate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void USART_Printf_Init(uint32_t baudrate)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
#if (DEBUG == DEBUG_UART1_NoRemap)
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
|
||||
#elif (DEBUG == DEBUG_UART1_Remap1)
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap1_USART1, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
|
||||
#elif (DEBUG == DEBUG_UART1_Remap2)
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap2_USART1, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
|
||||
#elif (DEBUG == DEBUG_UART1_Remap3)
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
|
||||
GPIO_PinRemapConfig(GPIO_FullRemap_USART1, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_30MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
|
||||
#endif
|
||||
|
||||
USART_InitStructure.USART_BaudRate = baudrate;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Tx;
|
||||
|
||||
USART_Init(USART1, &USART_InitStructure);
|
||||
USART_Cmd(USART1, ENABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SDI_Printf_Enable
|
||||
*
|
||||
* @brief Initializes the SDI printf Function.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void SDI_Printf_Enable(void)
|
||||
{
|
||||
*(DEBUG_DATA0_ADDRESS) = 0;
|
||||
Delay_Init();
|
||||
Delay_Ms(1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _write
|
||||
*
|
||||
* @brief Support Printf Function
|
||||
*
|
||||
* @param *buf - UART send Data.
|
||||
* size - Data length.
|
||||
*
|
||||
* @return size - Data length
|
||||
*/
|
||||
__attribute__((used))
|
||||
int _write(int fd, char *buf, int size)
|
||||
{
|
||||
int i = 0;
|
||||
int writeSize = size;
|
||||
#if (SDI_PRINT == SDI_PR_OPEN)
|
||||
do
|
||||
{
|
||||
|
||||
/**
|
||||
* data0 data1 8 bytes
|
||||
* data0 The lowest byte storage length, the maximum is 7
|
||||
*
|
||||
*/
|
||||
|
||||
while( (*(DEBUG_DATA0_ADDRESS) != 0u))
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
if(writeSize>7)
|
||||
{
|
||||
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||
|
||||
i += 7;
|
||||
writeSize -= 7;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||
|
||||
writeSize = 0;
|
||||
}
|
||||
|
||||
} while (writeSize);
|
||||
|
||||
#else
|
||||
|
||||
for(i = 0; i < size; i++){
|
||||
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
|
||||
USART_SendData(USART1, *buf++);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
return writeSize;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _sbrk
|
||||
*
|
||||
* @brief Change the spatial position of data segment.
|
||||
*
|
||||
* @return size: Data length
|
||||
*/
|
||||
__attribute__((used))
|
||||
void *_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
extern char _end[];
|
||||
extern char _heap_end[];
|
||||
static char *curbrk = _end;
|
||||
|
||||
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
|
||||
return NULL - 1;
|
||||
|
||||
curbrk += incr;
|
||||
return curbrk - incr;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : debug.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for UART
|
||||
* Printf , Delay functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __DEBUG_H
|
||||
#define __DEBUG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
#include <stdio.h>
|
||||
|
||||
/* UART Printf Definition */
|
||||
#define DEBUG_UART1_NoRemap 1 //Tx-PD5
|
||||
#define DEBUG_UART1_Remap1 2 //Tx-PD0
|
||||
#define DEBUG_UART1_Remap2 3 //Tx-PD6
|
||||
#define DEBUG_UART1_Remap3 4 //Tx-PC0
|
||||
|
||||
/* DEBUG UATR Definition */
|
||||
#ifndef DEBUG
|
||||
#define DEBUG DEBUG_UART1_NoRemap
|
||||
#endif
|
||||
|
||||
/* SDI Printf Definition */
|
||||
#define SDI_PR_CLOSE 0
|
||||
#define SDI_PR_OPEN 1
|
||||
|
||||
#ifndef SDI_PRINT
|
||||
#define SDI_PRINT SDI_PR_CLOSE
|
||||
#endif
|
||||
|
||||
void Delay_Init(void);
|
||||
void Delay_Us(uint32_t n);
|
||||
void Delay_Ms(uint32_t n);
|
||||
void USART_Printf_Init(uint32_t baudrate);
|
||||
void SDI_Printf_Enable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DEBUG_H */
|
||||
@@ -0,0 +1,159 @@
|
||||
ENTRY( _start )
|
||||
|
||||
__stack_size = 256;
|
||||
|
||||
PROVIDE( _stack_size = __stack_size );
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.init :
|
||||
{
|
||||
_sinit = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(SORT_NONE(.init)))
|
||||
. = ALIGN(4);
|
||||
_einit = .;
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP(*(SORT_NONE(.fini)))
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
PROVIDE( _etext = . );
|
||||
PROVIDE( _eitcm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_vma = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.dlalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_lma = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.sdata2*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _sbss = .);
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ebss = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
PROVIDE( _end = _ebss);
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_susrstack = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _eusrstack = .);
|
||||
} >RAM
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_adc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/20
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* ADC firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_ADC_H
|
||||
#define __CH32V00x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* ADC Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
|
||||
dual mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
|
||||
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
|
||||
Scan (multichannels) or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
|
||||
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
|
||||
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
} ADC_InitTypeDef;
|
||||
|
||||
/* ADC_mode */
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||
|
||||
/* ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000)
|
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000)
|
||||
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000)
|
||||
#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000)
|
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000)
|
||||
#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
|
||||
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
|
||||
|
||||
/* ADC_data_align */
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
|
||||
/* ADC_channels */
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
|
||||
#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
|
||||
|
||||
/* ADC_sampling_time */
|
||||
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_15Cycles ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_30Cycles ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_43Cycles ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_57Cycles ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_73Cycles ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_241Cycles ((uint8_t)0x07)
|
||||
|
||||
/* ADC_external_trigger_sources_for_injected_channels_conversion */
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000)
|
||||
#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
|
||||
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
|
||||
|
||||
/* ADC_injected_channel_selection */
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||
|
||||
/* ADC_analog_watchdog_selection */
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
|
||||
/* ADC_interrupts_definition */
|
||||
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||
|
||||
/* ADC_flags_definition */
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||
|
||||
/* ADC_calibration_voltage_definition */
|
||||
#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000)
|
||||
#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000)
|
||||
|
||||
/* ADC_external_trigger_sources_delay_channels_definition */
|
||||
#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00000200)
|
||||
|
||||
void ADC_DeInit(ADC_TypeDef *ADCx);
|
||||
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
void ADC_ResetCalibration(ADC_TypeDef *ADCx);
|
||||
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
|
||||
void ADC_StartCalibration(ADC_TypeDef *ADCx);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
|
||||
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
|
||||
void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL);
|
||||
void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V00x_ADC_H */
|
||||
@@ -0,0 +1,38 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_dbgmcu.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* DBGMCU firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_DBGMCU_H
|
||||
#define __CH32V00x_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* CFGR0 Register */
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020)
|
||||
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
uint32_t __get_DEBUG_CR(void);
|
||||
void __set_DEBUG_CR(uint32_t value);
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
uint32_t DBGMCU_GetCHIPID( void );
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_DBGMCU_H */
|
||||
@@ -0,0 +1,177 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_dma.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* DMA firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_DMA_H
|
||||
#define __CH32V00x_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* DMA Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/* DMA_data_transfer_direction */
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_peripheral_incremented_mode */
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_memory_incremented_mode */
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_peripheral_data_size */
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||
|
||||
/* DMA_memory_data_size */
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
|
||||
/* DMA_circular_normal_mode */
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_priority_level */
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_memory_to_memory */
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_interrupts_definition */
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
/* DMA_flags_definition */
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
|
||||
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V00x_DMA_H */
|
||||
@@ -0,0 +1,78 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_exti.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* EXTI firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_EXTI_H
|
||||
#define __CH32V00x_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* EXTI mode enumeration */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
} EXTIMode_TypeDef;
|
||||
|
||||
/* EXTI Trigger enumeration */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
} EXTITrigger_TypeDef;
|
||||
|
||||
/* EXTI Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} EXTI_InitTypeDef;
|
||||
|
||||
/* EXTI_Lines */
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */
|
||||
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_EXTI_H */
|
||||
@@ -0,0 +1,138 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_flash.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/12/25
|
||||
* Description : This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_FLASH_H
|
||||
#define __CH32V00x_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* FLASH Status */
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PG,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT,
|
||||
FLASH_OP_RANGE_ERROR = 0xFD,
|
||||
FLASH_ALIGN_ERROR = 0xFE,
|
||||
FLASH_ADR_RANGE_ERROR = 0xFF,
|
||||
} FLASH_Status;
|
||||
|
||||
/* Flash_Latency */
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
|
||||
|
||||
/* Values to be used with CH32V00x devices (1page = 64Byte) */
|
||||
#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
|
||||
#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
|
||||
#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */
|
||||
#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */
|
||||
#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */
|
||||
#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */
|
||||
#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */
|
||||
#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */
|
||||
#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */
|
||||
#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */
|
||||
#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */
|
||||
#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */
|
||||
#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */
|
||||
#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */
|
||||
#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */
|
||||
#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */
|
||||
|
||||
#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
|
||||
|
||||
/* Option_Bytes_IWatchdog */
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
|
||||
|
||||
/* Option_Bytes_nRST_STOP */
|
||||
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
|
||||
|
||||
/* Option_Bytes_nRST_STDBY */
|
||||
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
|
||||
|
||||
/* Option_Bytes_RST_ENandDT */
|
||||
#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/
|
||||
#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */
|
||||
#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */
|
||||
#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128us */
|
||||
|
||||
/* Option_Bytes_Power_ON_Start_Mode */
|
||||
#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */
|
||||
#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */
|
||||
|
||||
/* FLASH_Interrupts */
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
/* FLASH_Flags */
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
|
||||
|
||||
/* System_Reset_Start_Mode */
|
||||
#define Start_Mode_USER ((uint32_t)0x00000000)
|
||||
#define Start_Mode_BOOT ((uint32_t)0x00004000)
|
||||
|
||||
|
||||
/*Functions used for all CH32V00x devices*/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
|
||||
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
|
||||
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode);
|
||||
uint32_t FLASH_GetUserOptionByte(void);
|
||||
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
void FLASH_Unlock_Fast(void);
|
||||
void FLASH_Lock_Fast(void);
|
||||
void FLASH_BufReset(void);
|
||||
void FLASH_BufLoad(uint32_t Address, uint32_t Data0);
|
||||
void FLASH_ErasePage_Fast(uint32_t Page_Address);
|
||||
void FLASH_ProgramPage_Fast(uint32_t Page_Address);
|
||||
void SystemReset_StartMode(uint32_t Mode);
|
||||
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
|
||||
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_FLASH_H */
|
||||
@@ -0,0 +1,132 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_gpio.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/02/27
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* GPIO firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_GPIO_H
|
||||
#define __CH32V00x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* Output Maximum frequency selection */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_10MHz = 1,
|
||||
GPIO_Speed_2MHz,
|
||||
GPIO_Speed_30MHz
|
||||
} GPIOSpeed_TypeDef;
|
||||
|
||||
#define GPIO_Speed_50MHz GPIO_Speed_30MHz
|
||||
|
||||
/* Configuration Mode enumeration */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_AIN = 0x0,
|
||||
GPIO_Mode_IN_FLOATING = 0x04,
|
||||
GPIO_Mode_IPD = 0x28,
|
||||
GPIO_Mode_IPU = 0x48,
|
||||
GPIO_Mode_Out_OD = 0x14,
|
||||
GPIO_Mode_Out_PP = 0x10,
|
||||
GPIO_Mode_AF_OD = 0x1C,
|
||||
GPIO_Mode_AF_PP = 0x18
|
||||
} GPIOMode_TypeDef;
|
||||
|
||||
/* GPIO Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/* Bit_SET and Bit_RESET enumeration */
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
} BitAction;
|
||||
|
||||
/* GPIO_pins_define */
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
/* GPIO_Remap_define */
|
||||
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
|
||||
#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */
|
||||
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */
|
||||
#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */
|
||||
|
||||
/* GPIO_Port_Sources */
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||
|
||||
/* GPIO_Pin_sources */
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef *GPIOx);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_GPIO_H */
|
||||
@@ -0,0 +1,415 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_i2c.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* I2C firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_I2C_H
|
||||
#define __CH32V00x_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* I2C Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t I2C_Mode; /* Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/* I2C_mode */
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||
|
||||
/* I2C_duty_cycle_in_fast_mode */
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
|
||||
|
||||
/* I2C_acknowledgement */
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* I2C_transfer_direction */
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||
|
||||
/* I2C_acknowledged_address */
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||
|
||||
/* I2C_registers */
|
||||
#define I2C_Register_CTLR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CTLR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OADDR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_DATAR ((uint8_t)0x10)
|
||||
#define I2C_Register_STAR1 ((uint8_t)0x14)
|
||||
#define I2C_Register_STAR2 ((uint8_t)0x18)
|
||||
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
|
||||
|
||||
/* I2C_PEC_position */
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C_NACK_position */
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C_interrupts_definition */
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||
|
||||
/* I2C_interrupts_definition */
|
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||
|
||||
/* SR2 register flags */
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||
|
||||
/* SR1 register flags */
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||
|
||||
/****************I2C Master Events (Events grouped in order of communication)********************/
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Start communicate
|
||||
*
|
||||
* After master use I2C_GenerateSTART() function sending the START condition,the master
|
||||
* has to wait for event 5(the Start condition has been correctly
|
||||
* released on the I2C bus ).
|
||||
*
|
||||
*/
|
||||
/* EVT5 */
|
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* When start condition correctly released on the bus(check EVT5), the
|
||||
* master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
|
||||
* it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will be set:
|
||||
*
|
||||
*
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||
* event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||
* is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (after generating the START
|
||||
* and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
|
||||
* Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
|
||||
* on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
|
||||
* of the 10-bit address (LSB) . Then master should wait for event 6.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
/* EVT6 */
|
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
/*EVT9 */
|
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Communication events
|
||||
*
|
||||
* If START condition has generated and slave address
|
||||
* been acknowledged. then the master has to check one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use
|
||||
* I2C_ReceiveData() function to read the data received from the slave .
|
||||
*
|
||||
* 2) Master Transmitter mode: The master use I2C_SendData() function to send data
|
||||
* then to wait on event EVT8 or EVT8_2.
|
||||
* These two events are similar:
|
||||
* - EVT8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EVT8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EVT8 is sufficient for the application.
|
||||
* Using EVT8_2 will leads to a slower communication speed but will more reliable .
|
||||
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
|
||||
*
|
||||
*
|
||||
* Note:
|
||||
* In case the user software does not guarantee that this event EVT7 is managed before
|
||||
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
|
||||
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
/* Master Receive mode */
|
||||
/* EVT7 */
|
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master Transmitter mode*/
|
||||
/* EVT8 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
/* EVT8_2 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
/******************I2C Slave Events (Events grouped in order of communication)******************/
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Start Communicate events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a start condition of master device generate on the bus.
|
||||
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
|
||||
*
|
||||
*
|
||||
*
|
||||
* a) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* b) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* c) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* EVT1 */
|
||||
/* a) Case of One Single Address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* b) Case of Dual address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* c) Case of General Call enabled for the slave */
|
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EVT1 has already been checked :
|
||||
*
|
||||
* - Slave Receiver mode:
|
||||
* - EVT2--The device is expecting to receive a data byte .
|
||||
* - EVT4--The device is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
|
||||
* the EVT3 is managed before the current byte end of transfer The second one can optionally
|
||||
* be used.
|
||||
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission
|
||||
* shall end . The slave device has to stop sending
|
||||
* data bytes and wait a Stop condition from bus.
|
||||
*
|
||||
* Note:
|
||||
* If the user software does not guarantee that the event 2 is
|
||||
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
|
||||
* and I2C_FLAG_BTF flag at the same time .
|
||||
* In this case the communication will be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Slave Receiver mode*/
|
||||
/* EVT2 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
/* EVT4 */
|
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||
|
||||
/* Slave Transmitter mode -----------------------*/
|
||||
/* EVT3 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
/*EVT3_2 */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
|
||||
void I2C_DeInit(I2C_TypeDef *I2Cx);
|
||||
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
|
||||
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
|
||||
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
|
||||
|
||||
|
||||
/*****************************************************************************************
|
||||
*
|
||||
* I2C State Monitoring Functions
|
||||
*
|
||||
****************************************************************************************
|
||||
* This I2C driver provides three different ways for I2C state monitoring
|
||||
* profit the application requirements and constraints:
|
||||
*
|
||||
*
|
||||
* a) First way:
|
||||
* Using I2C_CheckEvent() function:
|
||||
* It compares the status registers (STARR1 and STAR2) content to a given event
|
||||
* (can be the combination of more flags).
|
||||
* If the current status registers includes the given flags will return SUCCESS.
|
||||
* and if the current status registers miss flags will returns ERROR.
|
||||
* - When to use:
|
||||
* - This function is suitable for most applications as well as for startup
|
||||
* activity since the events are fully described in the product reference manual
|
||||
* (CH32V03RM).
|
||||
* - It is also suitable for users who need to define their own events.
|
||||
* - Limitations:
|
||||
* - If an error occurs besides to the monitored error,
|
||||
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||
* in corrupted state. it is suggeted to use error interrupts to monitor the error
|
||||
* events and handle them in IRQ handler.
|
||||
*
|
||||
*
|
||||
* Note:
|
||||
* The following functions are recommended for error management: :
|
||||
* - I2C_ITConfig() main function of configure and enable the error interrupts.
|
||||
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
|
||||
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
|
||||
* to determine which error occurred.
|
||||
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
|
||||
* \ I2C_GenerateStop() will be use to clear the error flag and source,
|
||||
* and return to correct communication status.
|
||||
*
|
||||
*
|
||||
* b) Second way:
|
||||
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
|
||||
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
|
||||
* - When to use:
|
||||
*
|
||||
* - This function is suitable for the same applications above but it
|
||||
* don't have the limitations of I2C_GetFlagStatus() function .
|
||||
* The returned value could be compared to events already defined in the
|
||||
* library (CH32V00x_i2c.h) or to custom values defined by user.
|
||||
* - This function can be used to monitor the status of multiple flags simultaneously.
|
||||
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to
|
||||
* accept the event according to the user's needs (when all event flags are set and
|
||||
* no other flags are set, or only when the required flags are set)
|
||||
*
|
||||
* - Limitations:
|
||||
* - User may need to define his own events.
|
||||
* - Same remark concerning the error management is applicable for this
|
||||
* function if user decides to check only regular communication flags (and
|
||||
* ignores error flags).
|
||||
*
|
||||
*
|
||||
* c) Third way:
|
||||
* Using the function I2C_GetFlagStatus() get the status of
|
||||
* one single flag .
|
||||
* - When to use:
|
||||
* - This function could be used for specific applications or in debug phase.
|
||||
* - It is suitable when only one flag checking is needed .
|
||||
*
|
||||
* - Limitations:
|
||||
* - Call this function to access the status register. Some flag bits may be cleared.
|
||||
* - Function may need to be called twice or more in order to monitor one single event.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*********************************************************
|
||||
*
|
||||
* a) Basic state monitoring(First way)
|
||||
********************************************************
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||
/*********************************************************
|
||||
*
|
||||
* b) Advanced state monitoring(Second way:)
|
||||
********************************************************
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||
/*********************************************************
|
||||
*
|
||||
* c) Flag-based state monitoring(Third way)
|
||||
*********************************************************
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
|
||||
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V00x_I2C_H */
|
||||
@@ -0,0 +1,50 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_iwdg.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* IWDG firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_IWDG_H
|
||||
#define __CH32V00x_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* IWDG_WriteAccess */
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* IWDG_prescaler */
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
|
||||
/* IWDG_Flag */
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_Enable(void);
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_IWDG_H */
|
||||
@@ -0,0 +1,74 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_misc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/12/26
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* miscellaneous firmware library functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00X_MISC_H
|
||||
#define __CH32V00X_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* CSR_INTSYSCR_INEST_definition */
|
||||
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
|
||||
#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
|
||||
|
||||
/* Check the configuration of CSR(0x804) in the startup file(.S)
|
||||
* interrupt nesting enable(CSR-0x804 bit1 = 1)
|
||||
* priority - bit[7] - Preemption Priority
|
||||
* bit[6] - Sub priority
|
||||
* bit[5:0] - Reserve
|
||||
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||
* priority - bit[7:6] - Sub priority
|
||||
* bit[5:0] - Reserve
|
||||
*/
|
||||
|
||||
#ifndef INTSYSCR_INEST
|
||||
#define INTSYSCR_INEST INTSYSCR_INEST_EN
|
||||
#endif
|
||||
|
||||
/* NVIC Init Structure definition
|
||||
* interrupt nesting enable(CSR-0x804 bit1 = 1)
|
||||
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 1.
|
||||
*
|
||||
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 3.
|
||||
*
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel;
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority;
|
||||
uint8_t NVIC_IRQChannelSubPriority;
|
||||
FunctionalState NVIC_IRQChannelCmd;
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/* Preemption_Priority_Group */
|
||||
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
|
||||
#else
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
|
||||
#endif
|
||||
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_MISC_H */
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_opa.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* OPA firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_OPA_H
|
||||
#define __CH32V00x_OPA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32v00x.h"
|
||||
|
||||
/* OPA PSEL enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CHP0 = 0,
|
||||
CHP1
|
||||
} OPA_PSEL_TypeDef;
|
||||
|
||||
/* OPA NSEL enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CHN0 = 0,
|
||||
CHN1
|
||||
} OPA_NSEL_TypeDef;
|
||||
|
||||
|
||||
/* OPA Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
|
||||
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
|
||||
} OPA_InitTypeDef;
|
||||
|
||||
void OPA_DeInit(void);
|
||||
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct);
|
||||
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct);
|
||||
void OPA_Cmd(FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,78 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_pwr.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file contains all the functions prototypes for the PWR
|
||||
* firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_PWR_H
|
||||
#define __CH32V00x_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* PVD_detection_level */
|
||||
#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060)
|
||||
#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080)
|
||||
#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0)
|
||||
#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0)
|
||||
#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0)
|
||||
|
||||
#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE0
|
||||
#define PWR_PVDLevel_3V1 PWR_PVDLevel_MODE1
|
||||
#define PWR_PVDLevel_3V3 PWR_PVDLevel_MODE2
|
||||
#define PWR_PVDLevel_3V5 PWR_PVDLevel_MODE3
|
||||
#define PWR_PVDLevel_3V7 PWR_PVDLevel_MODE4
|
||||
#define PWR_PVDLevel_3V9 PWR_PVDLevel_MODE5
|
||||
#define PWR_PVDLevel_4V1 PWR_PVDLevel_MODE6
|
||||
#define PWR_PVDLevel_4V4 PWR_PVDLevel_MODE7
|
||||
|
||||
/* PWR_AWU_Prescaler */
|
||||
#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002)
|
||||
#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003)
|
||||
#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004)
|
||||
#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005)
|
||||
#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006)
|
||||
#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007)
|
||||
#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008)
|
||||
#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009)
|
||||
#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A)
|
||||
#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B)
|
||||
#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C)
|
||||
#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D)
|
||||
#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E)
|
||||
#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F)
|
||||
|
||||
/* STOP_mode_entry */
|
||||
#define PWR_STANDBYEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STANDBYEntry_WFE ((uint8_t)0x02)
|
||||
|
||||
/* PWR_Flag */
|
||||
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||
|
||||
void PWR_DeInit(void);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_AutoWakeUpCmd(FunctionalState NewState);
|
||||
void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler);
|
||||
void PWR_AWU_SetWindowValue(uint8_t WindowValue);
|
||||
void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry);
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_PWR_H */
|
||||
@@ -0,0 +1,154 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_rcc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/08
|
||||
* Description : This file provides all the RCC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_RCC_H
|
||||
#define __CH32V00x_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* RCC_Exported_Types */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
|
||||
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
|
||||
} RCC_ClocksTypeDef;
|
||||
|
||||
/* HSE_configuration */
|
||||
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||
|
||||
/* PLL_entry_clock_source */
|
||||
#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00010000)
|
||||
|
||||
/* System_clock_source */
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
|
||||
/* AHB_clock_source */
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
|
||||
#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030)
|
||||
#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040)
|
||||
#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050)
|
||||
#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
|
||||
|
||||
/* RCC_Interrupt_source */
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
/* ADC_clock_source */
|
||||
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
|
||||
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
|
||||
#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000)
|
||||
#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000)
|
||||
#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800)
|
||||
#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800)
|
||||
#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000)
|
||||
#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000)
|
||||
#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
|
||||
#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
|
||||
|
||||
/* AHB_peripheral */
|
||||
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||
|
||||
/* APB2_peripheral */
|
||||
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||
|
||||
/* APB1_peripheral */
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
|
||||
/* Clock_source_to_output_on_MCO_pin */
|
||||
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCO_PLLCLK ((uint8_t)0x07)
|
||||
|
||||
/* RCC_Flag */
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
/* SysTick_clock_source */
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
|
||||
void RCC_DeInit(void);
|
||||
void RCC_HSEConfig(uint32_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V00x_RCC_H */
|
||||
@@ -0,0 +1,156 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v00x_spi.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/06/01
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* SPI firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V00x_SPI_H
|
||||
#define __CH32V00x_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <ch32v00x.h>
|
||||
|
||||
/* SPI Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /* Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity
|
||||
When using SPI slave mode to send data, the CPOL bit should be set to 1 */
|
||||
|
||||
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
|
||||
} SPI_InitTypeDef;
|
||||
|
||||
/* SPI_data_direction */
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
|
||||
/* SPI_mode */
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
|
||||
/* SPI_data_size */
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||
|
||||
/* SPI_Clock_Polarity */
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)//When using SPI slave mode to send data, the CPOL bit should be set to 1.
|
||||
|
||||
/* SPI_Clock_Phase */
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
|
||||
/* SPI_Slave_Select_management */
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
|
||||
/* SPI_BaudRate_Prescaler */
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
|
||||
/* SPI_MSB_LSB transmission */
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode
|
||||
|
||||
/* SPI_I2S_DMA_transfer_requests */
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
|
||||
/* SPI_NSS_internal_software_management */
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
|
||||
/* SPI_CRC_Transmit_Receive */
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
|
||||
/* SPI_direction_transmit_receive */
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
|
||||
/* SPI_I2S_interrupts_definition */
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
|
||||
/* SPI_I2S_flags_definition */
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
|
||||
void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
|
||||
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
|
||||
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_TransmitCRC(SPI_TypeDef *SPIx);
|
||||
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V00x_SPI_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user