mirror of
https://github.com/t2linux/kernel.git
synced 2026-04-30 13:48:59 -07:00
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "The diff is dominated by the Allwinner A10/A20 SoCs getting converted to the sunxi-ng framework. Otherwise, the heavy hitters are various drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are some other new clk drivers in here too but overall this is just a bunch of clk drivers for various different pieces of hardware and a collection of non-critical fixes for clk drivers. New Drivers: - Allwinner R40 SoCs - Renesas R-Car Gen3 USB 2.0 clock selector PHY - Atmel AT91 audio PLL - Uniphier PXs3 SoCs - ARC HSDK Board PLLs - AXS10X Board PLLs - STMicroelectronics STM32H743 SoCs Removed Drivers: - Non-compiling mb86s7x support Updates: - Allwinner A10/A20 SoCs converted to sunxi-ng framework - Allwinner H3 CPU clk fixes - Renesas R-Car D3 SoC - Renesas V2H and M3-W modules - Samsung Exynos5420/5422/5800 audio fixes - Rockchip fractional clk approximation fixes - Rockchip rk3126 SoC support within the rk3128 driver - Amlogic gxbb CEC32 and sd_emmc clks - Amlogic meson8b reset controller support - IDT VersaClock 5P49V5925/5P49V6901 support - Qualcomm MSM8996 SMMU clks - Various 'const' applications for struct clk_ops - si5351 PLL reset bugfix - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2 - Assorted Tegra clk driver fixes" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits) clk: si5351: fix PLL reset ASoC: atmel-classd: remove aclk clock ASoC: atmel-classd: remove aclk clock from DT binding clk: at91: clk-generated: make gclk determine audio_pll rate clk: at91: clk-generated: create function to find best_diff clk: at91: add audio pll clock drivers dt-bindings: clk: at91: add audio plls to the compatible list clk: at91: clk-generated: remove useless divisor loop clk: mb86s7x: Drop non-building driver clk: ti: check for null return in strrchr to avoid null dereferencing clk: Don't write error code into divider register clk: uniphier: add video input subsystem clock clk: uniphier: add audio system clock clk: stm32h7: Add stm32h743 clock driver clk: gate: expose clk_gate_ops::is_enabled clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled() clk: uniphier: add PXs3 clock data clk: hi6220: change watchdog clock source clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808 clk: cs2000: Add cs2000_set_saved_rate ...
This commit is contained in:
Linus Torvalds
@@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
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Required Properties:
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- compatible: should be "amlogic,gxbb-aoclkc"
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
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- GXM (S912) : "amlogic,meson-gxm-aoclkc"
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followed by the common "amlogic,meson-gx-aoclkc"
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- #clock-cells: should be 1.
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@@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
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preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
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- reg: base address and size of the AO system control register space.
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Example: AO Clock controller node:
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clkc_AO: clock-controller@040 {
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compatible = "amlogic,gxbb-aoclkc";
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reg = <0x0 0x040 0x0 0x4>;
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ao_sysctrl: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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Example: UART controller node that consumes the clock and reset generated
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by the clock controller:
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@@ -81,6 +81,16 @@ Required properties:
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"atmel,sama5d2-clk-generated":
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at91 generated clock
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"atmel,sama5d2-clk-audio-pll-frac":
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at91 audio fractional pll
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"atmel,sama5d2-clk-audio-pll-pad":
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at91 audio pll CLK_AUDIO output pin
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"atmel,sama5d2-clk-audio-pll-pmc"
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at91 audio pll output on AUDIOPLLCLK that feeds the PMC
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and can be used by peripheral clock or generic clock
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Required properties for SCKC node:
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- reg : defines the IO memory reserved for the SCKC.
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- #size-cells : shall be 0 (reg is used to encode clk id).
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@@ -1,24 +1,32 @@
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Binding for IDT VersaClock5 programmable i2c clock generator.
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Binding for IDT VersaClock 5,6 programmable i2c clock generators.
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The IDT VersaClock5 are programmable i2c clock generators providing
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from 3 to 12 output clocks.
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The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
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generators providing from 3 to 12 output clocks.
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==I2C device node==
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Required properties:
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- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
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"idt,5p49v5935".
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- compatible: shall be one of
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"idt,5p49v5923"
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"idt,5p49v5925"
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"idt,5p49v5933"
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"idt,5p49v5935"
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"idt,5p49v6901"
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- reg: i2c device address, shall be 0x68 or 0x6a.
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- #clock-cells: from common clock binding; shall be set to 1.
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- clocks: from common clock binding; list of parent clock handles,
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- 5p49v5923: (required) either or both of XTAL or CLKIN
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- 5p49v5923 and
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5p49v5925 and
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5p49v6901: (required) either or both of XTAL or CLKIN
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reference clock.
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- 5p49v5933 and
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- 5p49v5935: (optional) property not present (internal
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Xtal used) or CLKIN reference
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clock.
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- clock-names: from common clock binding; clock input names, can be
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- 5p49v5923: (required) either or both of "xin", "clkin".
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- 5p49v5923 and
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5p49v5925 and
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5p49v6901: (required) either or both of "xin", "clkin".
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- 5p49v5933 and
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- 5p49v5935: (optional) property not present or "clkin".
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@@ -37,6 +45,7 @@ clock specifier, the following mapping applies:
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1 -- OUT1
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2 -- OUT4
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5P49V5925 and
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5P49V5935:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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@@ -44,6 +53,13 @@ clock specifier, the following mapping applies:
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3 -- OUT3
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4 -- OUT4
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5P49V6901:
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0 -- OUT0_SEL_I2CB
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1 -- OUT1
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2 -- OUT2
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3 -- OUT3
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4 -- OUT4
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==Example==
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/* 25MHz reference crystal */
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@@ -22,6 +22,7 @@ Required Properties:
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- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
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- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
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- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
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- reg: Base address and length of the memory resource used by the CPG/MSSR
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block
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@@ -30,7 +31,7 @@ Required Properties:
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
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r8a7795, r8a7796)
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r8a7795, r8a7796, r8a77995)
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- "extalr" (r8a7795, r8a7796)
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- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
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@@ -0,0 +1,55 @@
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* Renesas R-Car USB 2.0 clock selector
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This file provides information on what the device node for the R-Car USB 2.0
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clock selector.
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If you connect an external clock to the USB_EXTAL pin only, you should set
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the clock rate to "usb_extal" node only.
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If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
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is not needed because this is default setting. (Of course, you can set the
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clock rates to both "usb_extal" and "usb_xtal" nodes.
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Case 1: An external clock connects to R-Car SoC
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+----------+ +--- R-Car ---------------------+
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|External |---|USB_EXTAL ---> all usb channels|
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|clock | |USB_XTAL |
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+----------+ +-------------------------------+
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In this case, we need this driver with "usb_extal" clock.
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Case 2: An oscillator connects to R-Car SoC
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+----------+ +--- R-Car ---------------------+
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|Oscillator|---|USB_EXTAL -+-> all usb channels|
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| |---|USB_XTAL --+ |
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+----------+ +-------------------------------+
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In this case, we don't need this selector.
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Required properties:
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- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
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an R8A7795 SoC.
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"renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
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an R8A7796 SoC.
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"renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
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compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: offset and length of the USB 2.0 clock selector register block.
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- clocks: A list of phandles and specifier pairs.
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- clock-names: Name of the clocks.
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- The functional clock must be "ehci_ohci"
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- The USB_EXTAL clock pin must be "usb_extal"
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- The USB_XTAL clock pin must be "usb_xtal"
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- #clock-cells: Must be 0
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Example (R-Car H3):
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usb2_clksel: clock-controller@e6590630 {
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compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
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"renesas,rcar-gen3-usb2-clock-sel";
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reg = <0 0xe6590630 0 0x02>;
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clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
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clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
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#clock-cells = <0>;
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};
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@@ -1,12 +1,14 @@
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* Rockchip RK3128 Clock and Reset Unit
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* Rockchip RK3126/RK3128 Clock and Reset Unit
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The RK3128 clock controller generates and supplies clock to various
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The RK3126/RK3128 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3128-cru"
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- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
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"rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
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"rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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@@ -0,0 +1,28 @@
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Binding for the HSDK Generic PLL clock
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible: should be "snps,hsdk-<name>-pll-clock"
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"snps,hsdk-core-pll-clock"
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"snps,hsdk-gp-pll-clock"
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"snps,hsdk-hdmi-pll-clock"
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- reg : should contain base register location and length.
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- clocks: shall be the input parent clock phandle for the PLL.
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- #clock-cells: from common clock binding; Should always be set to 0.
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Example:
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input_clk: input-clk {
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clock-frequency = <33333333>;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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cpu_clk: cpu-clk@0 {
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compatible = "snps,hsdk-core-pll-clock";
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reg = <0x00 0x10>;
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#clock-cells = <0>;
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clocks = <&input_clk>;
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};
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@@ -0,0 +1,28 @@
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Binding for the AXS10X Generic PLL clock
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible: should be "snps,axs10x-<name>-pll-clock"
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"snps,axs10x-arc-pll-clock"
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"snps,axs10x-pgu-pll-clock"
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- reg: should always contain 2 pairs address - length: first for PLL config
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registers and second for corresponding LOCK CGU register.
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- clocks: shall be the input parent clock phandle for the PLL.
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- #clock-cells: from common clock binding; Should always be set to 0.
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Example:
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input-clk: input-clk {
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clock-frequency = <33333333>;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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core-clk: core-clk@80 {
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compatible = "snps,axs10x-arc-pll-clock";
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reg = <0x80 0x10>, <0x100 0x10>;
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#clock-cells = <0>;
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clocks = <&input-clk>;
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};
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@@ -0,0 +1,71 @@
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STMicroelectronics STM32H7 Reset and Clock Controller
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=====================================================
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The RCC IP is both a reset and a clock controller.
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Please refer to clock-bindings.txt for common clock controller binding usage.
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Please also refer to reset.txt for common reset controller binding usage.
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Required properties:
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- compatible: Should be:
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"st,stm32h743-rcc"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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- #clock-cells : from common clock binding; shall be set to 1
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- clocks: External oscillator clock phandle
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- high speed external clock signal (HSE)
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- low speed external clock signal (LSE)
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- external I2S clock (I2S_CKIN)
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Optional properties:
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- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
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write protection (RTC clock).
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Example:
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rcc: reset-clock-controller@58024400 {
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compatible = "st,stm32h743-rcc", "st,stm32-rcc";
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reg = <0x58024400 0x400>;
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#reset-cells = <1>;
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#clock-cells = <2>;
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clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
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st,syscfg = <&pwrcfg>;
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};
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The peripheral clock consumer should specify the desired clock by
|
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having the clock ID in its "clocks" phandle cell.
|
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|
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Example:
|
||||
|
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc TIM5_CK>;
|
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};
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|
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Specifying softreset control of devices
|
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=======================================
|
||||
|
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Device nodes should specify the reset channel required in their "resets"
|
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property, containing a phandle to the reset device node and an index specifying
|
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which channel to use.
|
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The index is the bit number within the RCC registers bank, starting from RCC
|
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base address.
|
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It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
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Where bit_offset is the bit offset within the register.
|
||||
|
||||
For example, for CRC reset:
|
||||
crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
|
||||
|
||||
Example:
|
||||
|
||||
timer2 {
|
||||
resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
|
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};
|
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@@ -3,18 +3,24 @@ Allwinner Clock Control Unit Binding
|
||||
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatibles:
|
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- "allwinner,sun4i-a10-ccu"
|
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- "allwinner,sun5i-a10s-ccu"
|
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- "allwinner,sun5i-a13-ccu"
|
||||
- "allwinner,sun6i-a31-ccu"
|
||||
- "allwinner,sun7i-a20-ccu"
|
||||
- "allwinner,sun8i-a23-ccu"
|
||||
- "allwinner,sun8i-a33-ccu"
|
||||
- "allwinner,sun8i-a83t-ccu"
|
||||
- "allwinner,sun8i-a83t-r-ccu"
|
||||
- "allwinner,sun8i-h3-ccu"
|
||||
- "allwinner,sun8i-h3-r-ccu"
|
||||
+ - "allwinner,sun8i-r40-ccu"
|
||||
- "allwinner,sun8i-v3s-ccu"
|
||||
- "allwinner,sun9i-a80-ccu"
|
||||
- "allwinner,sun50i-a64-ccu"
|
||||
- "allwinner,sun50i-a64-r-ccu"
|
||||
- "allwinner,sun50i-h5-ccu"
|
||||
- "nextthing,gr8-ccu"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
|
||||
|
||||
@@ -6,7 +6,6 @@ System clock
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
|
||||
@@ -14,6 +13,7 @@ Required properties:
|
||||
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-clock" - for LD20 SoC.
|
||||
"socionext,uniphier-pxs3-clock" - for PXs3 SoC
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
@@ -48,7 +48,6 @@ Media I/O (MIO) clock, SD clock
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
|
||||
@@ -56,6 +55,7 @@ Required properties:
|
||||
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
|
||||
"socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
@@ -82,11 +82,9 @@ Provided clocks:
|
||||
8: USB2 ch0 host
|
||||
9: USB2 ch1 host
|
||||
10: USB2 ch2 host
|
||||
11: USB2 ch3 host
|
||||
12: USB2 ch0 PHY
|
||||
13: USB2 ch1 PHY
|
||||
14: USB2 ch2 PHY
|
||||
15: USB2 ch3 PHY
|
||||
|
||||
|
||||
Peripheral clock
|
||||
@@ -94,7 +92,6 @@ Peripheral clock
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following:
|
||||
"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
|
||||
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
|
||||
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
|
||||
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
|
||||
@@ -102,6 +99,7 @@ Required properties:
|
||||
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
|
||||
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
|
||||
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
|
||||
"socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
@@ -13,13 +13,11 @@ Required properties:
|
||||
Must be "tx".
|
||||
- clock-names
|
||||
Tuple listing input clock names.
|
||||
Required elements: "pclk", "gclk" and "aclk".
|
||||
Required elements: "pclk" and "gclk".
|
||||
- clocks
|
||||
Please refer to clock-bindings.txt.
|
||||
- assigned-clocks
|
||||
Should be <&classd_gclk>.
|
||||
- assigned-clock-parents
|
||||
Should be <&audio_pll_pmc>.
|
||||
|
||||
Optional properties:
|
||||
- pinctrl-names, pinctrl-0
|
||||
@@ -45,10 +43,9 @@ classd: classd@fc048000 {
|
||||
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
|
||||
| AT91_XDMAC_DT_PERID(47))>;
|
||||
dma-names = "tx";
|
||||
clocks = <&classd_clk>, <&classd_gclk>, <&audio_pll_pmc>;
|
||||
clock-names = "pclk", "gclk", "aclk";
|
||||
clocks = <&classd_clk>, <&classd_gclk>;
|
||||
clock-names = "pclk", "gclk";
|
||||
assigned-clocks = <&classd_gclk>;
|
||||
assigned-clock-parents = <&audio_pll_pmc>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_classd_default>;
|
||||
|
||||
+12
@@ -12842,6 +12842,18 @@ F: drivers/clocksource/arc_timer.c
|
||||
F: drivers/tty/serial/arc_uart.c
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git
|
||||
|
||||
SYNOPSYS ARC HSDK SDP pll clock driver
|
||||
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
|
||||
S: Supported
|
||||
F: drivers/clk/clk-hsdk-pll.c
|
||||
F: Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt
|
||||
|
||||
SYNOPSYS ARC SDP clock driver
|
||||
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
|
||||
S: Supported
|
||||
F: drivers/clk/axs10x/*
|
||||
F: Documentation/devicetree/bindings/clock/snps,pll-clock.txt
|
||||
|
||||
SYNOPSYS ARC SDP platform support
|
||||
M: Alexey Brodkin <abrodkin@synopsys.com>
|
||||
S: Supported
|
||||
|
||||
@@ -26,6 +26,7 @@ config SOC_SAMA5D2
|
||||
select HAVE_AT91_USB_CLK
|
||||
select HAVE_AT91_H32MX
|
||||
select HAVE_AT91_GENERATED_CLK
|
||||
select HAVE_AT91_AUDIO_PLL
|
||||
select PINCTRL_AT91PIO4
|
||||
help
|
||||
Select this if ou are using one of Atmel's SAMA5D2 family SoC.
|
||||
@@ -125,6 +126,9 @@ config HAVE_AT91_H32MX
|
||||
config HAVE_AT91_GENERATED_CLK
|
||||
bool
|
||||
|
||||
config HAVE_AT91_AUDIO_PLL
|
||||
bool
|
||||
|
||||
config SOC_SAM_V4_V5
|
||||
bool
|
||||
|
||||
|
||||
+12
-5
@@ -31,6 +31,13 @@ config COMMON_CLK_WM831X
|
||||
|
||||
source "drivers/clk/versatile/Kconfig"
|
||||
|
||||
config CLK_HSDK
|
||||
bool "PLL Driver for HSDK platform"
|
||||
depends on OF || COMPILE_TEST
|
||||
---help---
|
||||
This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
|
||||
control.
|
||||
|
||||
config COMMON_CLK_MAX77686
|
||||
tristate "Clock driver for Maxim 77620/77686/77802 MFD"
|
||||
depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
|
||||
@@ -39,10 +46,10 @@ config COMMON_CLK_MAX77686
|
||||
clock.
|
||||
|
||||
config COMMON_CLK_RK808
|
||||
tristate "Clock driver for RK808/RK818"
|
||||
tristate "Clock driver for RK805/RK808/RK818"
|
||||
depends on MFD_RK808
|
||||
---help---
|
||||
This driver supports RK808 and RK818 crystal oscillator clock. These
|
||||
This driver supports RK805, RK808 and RK818 crystal oscillator clock. These
|
||||
multi-function devices have two fixed-rate oscillators,
|
||||
clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
|
||||
by control register.
|
||||
@@ -210,14 +217,14 @@ config COMMON_CLK_OXNAS
|
||||
Support for the OXNAS SoC Family clocks.
|
||||
|
||||
config COMMON_CLK_VC5
|
||||
tristate "Clock driver for IDT VersaClock5 devices"
|
||||
tristate "Clock driver for IDT VersaClock 5,6 devices"
|
||||
depends on I2C
|
||||
depends on OF
|
||||
select REGMAP_I2C
|
||||
help
|
||||
---help---
|
||||
This driver supports the IDT VersaClock5 programmable clock
|
||||
generator.
|
||||
This driver supports the IDT VersaClock 5 and VersaClock 6
|
||||
programmable clock generators.
|
||||
|
||||
source "drivers/clk/bcm/Kconfig"
|
||||
source "drivers/clk/hisilicon/Kconfig"
|
||||
|
||||
@@ -27,8 +27,8 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
|
||||
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
|
||||
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
|
||||
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
|
||||
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
|
||||
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
|
||||
obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
|
||||
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
|
||||
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
|
||||
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
|
||||
@@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
|
||||
obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
|
||||
obj-$(CONFIG_ARCH_STM32) += clk-stm32h7.o
|
||||
obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
|
||||
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
|
||||
obj-$(CONFIG_ARCH_U300) += clk-u300.o
|
||||
|
||||
@@ -6,6 +6,7 @@ obj-y += pmc.o sckc.o
|
||||
obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
|
||||
obj-y += clk-system.o clk-peripheral.o clk-programmable.o
|
||||
|
||||
obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o
|
||||
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
|
||||
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
|
||||
obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -26,6 +26,13 @@
|
||||
#define GENERATED_SOURCE_MAX 6
|
||||
#define GENERATED_MAX_DIV 255
|
||||
|
||||
#define GCK_ID_SSC0 43
|
||||
#define GCK_ID_SSC1 44
|
||||
#define GCK_ID_I2S0 54
|
||||
#define GCK_ID_I2S1 55
|
||||
#define GCK_ID_CLASSD 59
|
||||
#define GCK_INDEX_DT_AUDIO_PLL 5
|
||||
|
||||
struct clk_generated {
|
||||
struct clk_hw hw;
|
||||
struct regmap *regmap;
|
||||
@@ -34,6 +41,7 @@ struct clk_generated {
|
||||
u32 id;
|
||||
u32 gckdiv;
|
||||
u8 parent_id;
|
||||
bool audio_pll_allowed;
|
||||
};
|
||||
|
||||
#define to_clk_generated(hw) \
|
||||
@@ -99,21 +107,41 @@ clk_generated_recalc_rate(struct clk_hw *hw,
|
||||
return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
|
||||
}
|
||||
|
||||
static void clk_generated_best_diff(struct clk_rate_request *req,
|
||||
struct clk_hw *parent,
|
||||
unsigned long parent_rate, u32 div,
|
||||
int *best_diff, long *best_rate)
|
||||
{
|
||||
unsigned long tmp_rate;
|
||||
int tmp_diff;
|
||||
|
||||
if (!div)
|
||||
tmp_rate = parent_rate;
|
||||
else
|
||||
tmp_rate = parent_rate / div;
|
||||
tmp_diff = abs(req->rate - tmp_rate);
|
||||
|
||||
if (*best_diff < 0 || *best_diff > tmp_diff) {
|
||||
*best_rate = tmp_rate;
|
||||
*best_diff = tmp_diff;
|
||||
req->best_parent_rate = parent_rate;
|
||||
req->best_parent_hw = parent;
|
||||
}
|
||||
}
|
||||
|
||||
static int clk_generated_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct clk_generated *gck = to_clk_generated(hw);
|
||||
struct clk_hw *parent = NULL;
|
||||
struct clk_rate_request req_parent = *req;
|
||||
long best_rate = -EINVAL;
|
||||
unsigned long tmp_rate, min_rate;
|
||||
unsigned long min_rate, parent_rate;
|
||||
int best_diff = -1;
|
||||
int tmp_diff;
|
||||
int i;
|
||||
u32 div;
|
||||
|
||||
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
|
||||
u32 div;
|
||||
unsigned long parent_rate;
|
||||
|
||||
for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
|
||||
parent = clk_hw_get_parent_by_index(hw, i);
|
||||
if (!parent)
|
||||
continue;
|
||||
@@ -124,25 +152,43 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
|
||||
(gck->range.max && min_rate > gck->range.max))
|
||||
continue;
|
||||
|
||||
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
|
||||
tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
|
||||
tmp_diff = abs(req->rate - tmp_rate);
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
|
||||
|
||||
if (best_diff < 0 || best_diff > tmp_diff) {
|
||||
best_rate = tmp_rate;
|
||||
best_diff = tmp_diff;
|
||||
req->best_parent_rate = parent_rate;
|
||||
req->best_parent_hw = parent;
|
||||
}
|
||||
|
||||
if (!best_diff || tmp_rate < req->rate)
|
||||
break;
|
||||
}
|
||||
clk_generated_best_diff(req, parent, parent_rate, div,
|
||||
&best_diff, &best_rate);
|
||||
|
||||
if (!best_diff)
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* The audio_pll rate can be modified, unlike the five others clocks
|
||||
* that should never be altered.
|
||||
* The audio_pll can technically be used by multiple consumers. However,
|
||||
* with the rate locking, the first consumer to enable to clock will be
|
||||
* the one definitely setting the rate of the clock.
|
||||
* Since audio IPs are most likely to request the same rate, we enforce
|
||||
* that the only clks able to modify gck rate are those of audio IPs.
|
||||
*/
|
||||
|
||||
if (!gck->audio_pll_allowed)
|
||||
goto end;
|
||||
|
||||
parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
|
||||
if (!parent)
|
||||
goto end;
|
||||
|
||||
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
|
||||
req_parent.rate = req->rate * div;
|
||||
__clk_determine_rate(parent, &req_parent);
|
||||
clk_generated_best_diff(req, parent, req_parent.rate, div,
|
||||
&best_diff, &best_rate);
|
||||
|
||||
if (!best_diff)
|
||||
break;
|
||||
}
|
||||
|
||||
end:
|
||||
pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
|
||||
__func__, best_rate,
|
||||
__clk_get_name((req->best_parent_hw)->clk),
|
||||
@@ -252,7 +298,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
|
||||
init.ops = &generated_ops;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
||||
CLK_SET_RATE_PARENT;
|
||||
|
||||
gck->id = id;
|
||||
gck->hw.init = &init;
|
||||
@@ -284,6 +331,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
|
||||
struct device_node *gcknp;
|
||||
struct clk_range range = CLK_RANGE(0, 0);
|
||||
struct regmap *regmap;
|
||||
struct clk_generated *gck;
|
||||
|
||||
num_parents = of_clk_get_parent_count(np);
|
||||
if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
|
||||
@@ -315,6 +363,21 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
|
||||
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
|
||||
parent_names, num_parents,
|
||||
id, &range);
|
||||
|
||||
gck = to_clk_generated(hw);
|
||||
|
||||
if (of_device_is_compatible(np,
|
||||
"atmel,sama5d2-clk-generated")) {
|
||||
if (gck->id == GCK_ID_SSC0 || gck->id == GCK_ID_SSC1 ||
|
||||
gck->id == GCK_ID_I2S0 || gck->id == GCK_ID_I2S1 ||
|
||||
gck->id == GCK_ID_CLASSD)
|
||||
gck->audio_pll_allowed = true;
|
||||
else
|
||||
gck->audio_pll_allowed = false;
|
||||
} else {
|
||||
gck->audio_pll_allowed = false;
|
||||
}
|
||||
|
||||
if (IS_ERR(hw))
|
||||
continue;
|
||||
|
||||
|
||||
@@ -1 +1,2 @@
|
||||
obj-y += i2s_pll_clock.o
|
||||
obj-y += pll_clock.o
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user