mirror of
https://github.com/t2linux/kernel.git
synced 2026-04-30 13:48:59 -07:00
Merge tag 'powerpc-4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
"Notable changes:
- Support for split PMD page table lock on 64-bit Book3S (Power8/9).
- Add support for HAVE_RELIABLE_STACKTRACE, so we properly support
live patching again.
- Add support for patching barrier_nospec in copy_from_user() and
syscall entry.
- A couple of fixes for our data breakpoints on Book3S.
- A series from Nick optimising TLB/mm handling with the Radix MMU.
- Numerous small cleanups to squash sparse/gcc warnings from Mathieu
Malaterre.
- Several series optimising various parts of the 32-bit code from
Christophe Leroy.
- Removal of support for two old machines, "SBC834xE" and "C2K"
("GEFanuc,C2K"), which is why the diffstat has so many deletions.
And many other small improvements & fixes.
There's a few out-of-area changes. Some minor ftrace changes OK'ed by
Steve, and a fix to our powernv cpuidle driver. Then there's a series
touching mm, x86 and fs/proc/task_mmu.c, which cleans up some details
around pkey support. It was ack'ed/reviewed by Ingo & Dave and has
been in next for several weeks.
Thanks to: Akshay Adiga, Alastair D'Silva, Alexey Kardashevskiy, Al
Viro, Andrew Donnellan, Aneesh Kumar K.V, Anju T Sudhakar, Arnd
Bergmann, Balbir Singh, Cédric Le Goater, Christophe Leroy, Christophe
Lombard, Colin Ian King, Dave Hansen, Fabio Estevam, Finn Thain,
Frederic Barrat, Gautham R. Shenoy, Haren Myneni, Hari Bathini, Ingo
Molnar, Jonathan Neuschäfer, Josh Poimboeuf, Kamalesh Babulal,
Madhavan Srinivasan, Mahesh Salgaonkar, Mark Greer, Mathieu Malaterre,
Matthew Wilcox, Michael Neuling, Michal Suchanek, Naveen N. Rao,
Nicholas Piggin, Nicolai Stange, Olof Johansson, Paul Gortmaker, Paul
Mackerras, Peter Rosin, Pridhiviraj Paidipeddi, Ram Pai, Rashmica
Gupta, Ravi Bangoria, Russell Currey, Sam Bobroff, Samuel
Mendoza-Jonas, Segher Boessenkool, Shilpasri G Bhat, Simon Guo,
Souptick Joarder, Stewart Smith, Thiago Jung Bauermann, Torsten Duwe,
Vaibhav Jain, Wei Yongjun, Wolfram Sang, Yisheng Xie, YueHaibing"
* tag 'powerpc-4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (251 commits)
powerpc/64s/radix: Fix missing ptesync in flush_cache_vmap
cpuidle: powernv: Fix promotion from snooze if next state disabled
powerpc: fix build failure by disabling attribute-alias warning in pci_32
ocxl: Fix missing unlock on error in afu_ioctl_enable_p9_wait()
powerpc-opal: fix spelling mistake "Uniterrupted" -> "Uninterrupted"
powerpc: fix spelling mistake: "Usupported" -> "Unsupported"
powerpc/pkeys: Detach execute_only key on !PROT_EXEC
powerpc/powernv: copy/paste - Mask SO bit in CR
powerpc: Remove core support for Marvell mv64x60 hostbridges
powerpc/boot: Remove core support for Marvell mv64x60 hostbridges
powerpc/boot: Remove support for Marvell mv64x60 i2c controller
powerpc/boot: Remove support for Marvell MPSC serial controller
powerpc/embedded6xx: Remove C2K board support
powerpc/lib: optimise PPC32 memcmp
powerpc/lib: optimise 32 bits __clear_user()
powerpc/time: inline arch_vtime_task_switch()
powerpc/Makefile: set -mcpu=860 flag for the 8xx
powerpc: Implement csum_ipv6_magic in assembly
powerpc/32: Optimise __csum_partial()
powerpc/lib: Adjust .balign inside string functions for PPC32
...
This commit is contained in:
Linus Torvalds
@@ -69,7 +69,9 @@ Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
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Description: read/write
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Set the mode for prefaulting in segments into the segment table
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when performing the START_WORK ioctl. Possible values:
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when performing the START_WORK ioctl. Only applicable when
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running under hashed page table mmu.
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Possible values:
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none: No prefaulting (default)
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work_element_descriptor: Treat the work element
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||||
descriptor as an effective address and
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@@ -157,6 +157,17 @@ OCXL_IOCTL_GET_METADATA:
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Obtains configuration information from the card, such at the size of
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MMIO areas, the AFU version, and the PASID for the current context.
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OCXL_IOCTL_ENABLE_P9_WAIT:
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Allows the AFU to wake a userspace thread executing 'wait'. Returns
|
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information to userspace to allow it to configure the AFU. Note that
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this is only available on POWER9.
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OCXL_IOCTL_GET_FEATURES:
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Reports on which CPU features that affect OpenCAPI are usable from
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userspace.
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mmap
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----
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File diff suppressed because it is too large
Load Diff
@@ -156,6 +156,7 @@ config PPC
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select BUILDTIME_EXTABLE_SORT
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select CLONE_BACKWARDS
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select DCACHE_WORD_ACCESS if PPC64 && CPU_LITTLE_ENDIAN
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select DYNAMIC_FTRACE if FUNCTION_TRACER
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select EDAC_ATOMIC_SCRUB
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select EDAC_SUPPORT
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select GENERIC_ATOMIC64 if PPC32
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@@ -214,6 +215,7 @@ config PPC
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select HAVE_PERF_USER_STACK_DUMP
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select HAVE_RCU_TABLE_FREE if SMP
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_RELIABLE_STACKTRACE if PPC64 && CPU_LITTLE_ENDIAN
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select HAVE_SYSCALL_TRACEPOINTS
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select HAVE_VIRT_CPU_ACCOUNTING
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select HAVE_IRQ_TIME_ACCOUNTING
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@@ -228,6 +230,7 @@ config PPC
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select OF_RESERVED_MEM
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select OLD_SIGACTION if PPC32
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select OLD_SIGSUSPEND
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select RTC_LIB
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select SPARSE_IRQ
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select SYSCTL_EXCEPTION_TRACE
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select VIRT_TO_BUS if !PPC64
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+18
-14
@@ -17,17 +17,18 @@ HAS_BIARCH := $(call cc-option-yn, -m32)
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# Set default 32 bits cross compilers for vdso and boot wrapper
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CROSS32_COMPILE ?=
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CROSS32CC := $(CROSS32_COMPILE)gcc
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CROSS32AR := $(CROSS32_COMPILE)ar
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ifeq ($(HAS_BIARCH),y)
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ifeq ($(CROSS32_COMPILE),)
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CROSS32CC := $(CC) -m32
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KBUILD_ARFLAGS += --target=elf32-powerpc
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ifdef CONFIG_PPC32
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# These options will be overridden by any -mcpu option that the CPU
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# or platform code sets later on the command line, but they are needed
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# to set a sane 32-bit cpu target for the 64-bit cross compiler which
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# may default to the wrong ISA.
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KBUILD_CFLAGS += -mcpu=powerpc
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KBUILD_AFLAGS += -mcpu=powerpc
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endif
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endif
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endif
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export CROSS32CC CROSS32AR
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ifeq ($(CROSS_COMPILE),)
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KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
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@@ -74,13 +75,15 @@ endif
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endif
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ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
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override LD += -EL
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KBUILD_CFLAGS += -mlittle-endian
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LDFLAGS += -EL
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LDEMULATION := lppc
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GNUTARGET := powerpcle
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MULTIPLEWORD := -mno-multiple
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KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-save-toc-indirect)
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else
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override LD += -EB
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KBUILD_CFLAGS += $(call cc-option,-mbig-endian)
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LDFLAGS += -EB
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LDEMULATION := ppc
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GNUTARGET := powerpc
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MULTIPLEWORD := -mmultiple
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@@ -93,19 +96,19 @@ aflags-$(CONFIG_CPU_BIG_ENDIAN) += $(call cc-option,-mabi=elfv1)
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aflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mabi=elfv2
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endif
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cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mlittle-endian
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cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(call cc-option,-mbig-endian)
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ifneq ($(cc-name),clang)
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cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mno-strict-align
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endif
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|
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cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(call cc-option,-mbig-endian)
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cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mlittle-endian
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aflags-$(CONFIG_CPU_BIG_ENDIAN) += $(call cc-option,-mbig-endian)
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aflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mlittle-endian
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ifeq ($(HAS_BIARCH),y)
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override AS += -a$(BITS)
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override LD += -m elf$(BITS)$(LDEMULATION)
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override CC += -m$(BITS)
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KBUILD_CFLAGS += -m$(BITS)
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KBUILD_AFLAGS += -m$(BITS) -Wl,-a$(BITS)
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LDFLAGS += -m elf$(BITS)$(LDEMULATION)
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KBUILD_ARFLAGS += --target=elf$(BITS)-$(GNUTARGET)
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endif
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@@ -178,6 +181,7 @@ CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6)
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CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)
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CFLAGS-$(CONFIG_POWER8_CPU) += $(call cc-option,-mcpu=power8)
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CFLAGS-$(CONFIG_POWER9_CPU) += $(call cc-option,-mcpu=power9)
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CFLAGS-$(CONFIG_PPC_8xx) += $(call cc-option,-mcpu=860)
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# Altivec option not allowed with e500mc64 in GCC.
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ifeq ($(CONFIG_ALTIVEC),y)
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@@ -23,19 +23,23 @@ all: $(obj)/zImage
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compress-$(CONFIG_KERNEL_GZIP) := CONFIG_KERNEL_GZIP
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compress-$(CONFIG_KERNEL_XZ) := CONFIG_KERNEL_XZ
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ifdef CROSS32_COMPILE
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BOOTCC := $(CROSS32_COMPILE)gcc
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BOOTAR := $(CROSS32_COMPILE)ar
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else
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BOOTCC := $(CC)
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BOOTAR := $(AR)
|
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endif
|
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|
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BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
|
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-fno-strict-aliasing -Os -msoft-float -pipe \
|
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-fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
|
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-D$(compress-y)
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|
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BOOTCC := $(CC)
|
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ifdef CONFIG_PPC64_BOOT_WRAPPER
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BOOTCFLAGS += -m64
|
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else
|
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BOOTCFLAGS += -m32
|
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ifdef CROSS32_COMPILE
|
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BOOTCC := $(CROSS32_COMPILE)gcc
|
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endif
|
||||
endif
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BOOTCFLAGS += -isystem $(shell $(BOOTCC) -print-file-name=include)
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@@ -49,6 +53,8 @@ endif
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|
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BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
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BOOTARFLAGS := -cr$(KBUILD_ARFLAGS)
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ifdef CONFIG_DEBUG_INFO
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BOOTCFLAGS += -g
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endif
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@@ -120,7 +126,7 @@ src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
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src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
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src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
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src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
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src-wlib-$(CONFIG_EMBEDDED6xx) += mpsc.c mv64x60.c mv64x60_i2c.c ugecon.c fsl-soc.c
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src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
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src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
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src-wlib-$(CONFIG_CPM) += cpm-serial.c
|
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@@ -143,8 +149,8 @@ src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
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src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
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src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
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src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
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cuboot-c2k.c gamecube-head.S \
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gamecube.c wii-head.S wii.c holly.c \
|
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gamecube-head.S gamecube.c \
|
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wii-head.S wii.c holly.c \
|
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fixed-head.S mvme5100.c
|
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src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
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src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
|
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@@ -202,7 +208,7 @@ quiet_cmd_bootas = BOOTAS $@
|
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cmd_bootas = $(BOOTCC) -Wp,-MD,$(depfile) $(BOOTAFLAGS) -c -o $@ $<
|
||||
|
||||
quiet_cmd_bootar = BOOTAR $@
|
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cmd_bootar = $(CROSS32AR) -cr$(KBUILD_ARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
|
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cmd_bootar = $(BOOTAR) $(BOOTARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
|
||||
|
||||
$(obj-libfdt): $(obj)/%.o: $(srctree)/scripts/dtc/libfdt/%.c FORCE
|
||||
$(call if_changed_dep,bootcc)
|
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@@ -339,7 +345,6 @@ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
|
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# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
|
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image-$(CONFIG_STORCENTER) += cuImage.storcenter
|
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image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
|
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image-$(CONFIG_PPC_C2K) += cuImage.c2k
|
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image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
|
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image-$(CONFIG_WII) += dtbImage.wii
|
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image-$(CONFIG_MVME5100) += dtbImage.mvme5100
|
||||
|
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@@ -1,189 +0,0 @@
|
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/*
|
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* GEFanuc C2K platform code.
|
||||
*
|
||||
* Author: Remi Machet <rmachet@slac.stanford.edu>
|
||||
*
|
||||
* Originated from prpmc2800.c
|
||||
*
|
||||
* 2008 (c) Stanford University
|
||||
* 2007 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "types.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include "ops.h"
|
||||
#include "elf.h"
|
||||
#include "mv64x60.h"
|
||||
#include "cuboot.h"
|
||||
#include "ppcboot.h"
|
||||
|
||||
static u8 *bridge_base;
|
||||
|
||||
static void c2k_bridge_setup(u32 mem_size)
|
||||
{
|
||||
u32 i, v[30], enables, acc_bits;
|
||||
u32 pci_base_hi, pci_base_lo, size, buf[2];
|
||||
unsigned long cpu_base;
|
||||
int rc;
|
||||
void *devp, *mv64x60_devp;
|
||||
u8 *bridge_pbase, is_coherent;
|
||||
struct mv64x60_cpu2pci_win *tbl;
|
||||
int bus;
|
||||
|
||||
bridge_pbase = mv64x60_get_bridge_pbase();
|
||||
is_coherent = mv64x60_is_coherent();
|
||||
|
||||
if (is_coherent)
|
||||
acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
|
||||
| MV64x60_PCI_ACC_CNTL_SWAP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
|
||||
| MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
|
||||
else
|
||||
acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_SWAP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
|
||||
| MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
|
||||
|
||||
mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
|
||||
mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360");
|
||||
if (mv64x60_devp == NULL)
|
||||
fatal("Error: Missing marvell,mv64360 device tree node\n\r");
|
||||
|
||||
enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
|
||||
enables |= 0x007ffe00; /* Disable all cpu->pci windows */
|
||||
out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
|
||||
|
||||
/* Get the cpu -> pci i/o & mem mappings from the device tree */
|
||||
devp = NULL;
|
||||
for (bus = 0; ; bus++) {
|
||||
char name[] = "pci ";
|
||||
|
||||
name[strlen(name)-1] = bus+'0';
|
||||
|
||||
devp = find_node_by_alias(name);
|
||||
if (devp == NULL)
|
||||
break;
|
||||
|
||||
if (bus >= 2)
|
||||
fatal("Error: Only 2 PCI controllers are supported at" \
|
||||
" this time.\n");
|
||||
|
||||
mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,
|
||||
mem_size, acc_bits);
|
||||
|
||||
rc = getprop(devp, "ranges", v, sizeof(v));
|
||||
if (rc == 0)
|
||||
fatal("Error: Can't find marvell,mv64360-pci ranges"
|
||||
" property\n\r");
|
||||
|
||||
/* Get the cpu -> pci i/o & mem mappings from the device tree */
|
||||
|
||||
for (i = 0; i < rc; i += 6) {
|
||||
switch (v[i] & 0xff000000) {
|
||||
case 0x01000000: /* PCI I/O Space */
|
||||
tbl = mv64x60_cpu2pci_io;
|
||||
break;
|
||||
case 0x02000000: /* PCI MEM Space */
|
||||
tbl = mv64x60_cpu2pci_mem;
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
pci_base_hi = v[i+1];
|
||||
pci_base_lo = v[i+2];
|
||||
cpu_base = v[i+3];
|
||||
size = v[i+5];
|
||||
|
||||
buf[0] = cpu_base;
|
||||
buf[1] = size;
|
||||
|
||||
if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
|
||||
fatal("Error: Can't translate PCI address " \
|
||||
"0x%x\n\r", (u32)cpu_base);
|
||||
|
||||
mv64x60_config_cpu2pci_window(bridge_base, bus,
|
||||
pci_base_hi, pci_base_lo, cpu_base, size, tbl);
|
||||
}
|
||||
|
||||
enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci<bus> i/o,
|
||||
cpu->pci<bus> mem0 */
|
||||
out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),
|
||||
enables);
|
||||
};
|
||||
}
|
||||
|
||||
static void c2k_fixups(void)
|
||||
{
|
||||
u32 mem_size;
|
||||
|
||||
mem_size = mv64x60_get_mem_size(bridge_base);
|
||||
c2k_bridge_setup(mem_size); /* Do necessary bridge setup */
|
||||
}
|
||||
|
||||
#define MV64x60_MPP_CNTL_0 0xf000
|
||||
#define MV64x60_MPP_CNTL_2 0xf008
|
||||
#define MV64x60_GPP_IO_CNTL 0xf100
|
||||
#define MV64x60_GPP_LEVEL_CNTL 0xf110
|
||||
#define MV64x60_GPP_VALUE_SET 0xf118
|
||||
|
||||
static void c2k_reset(void)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
udelay(5000000);
|
||||
|
||||
if (bridge_base != 0) {
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
|
||||
temp &= 0xFFFF0FFF;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
|
||||
temp |= 0x00000004;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
|
||||
temp |= 0x00000004;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
|
||||
temp &= 0xFFFF0FFF;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
|
||||
temp |= 0x00080000;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
|
||||
temp |= 0x00080000;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
|
||||
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
|
||||
0x00080004);
|
||||
}
|
||||
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
fdt_init(_dtb_start);
|
||||
|
||||
bridge_base = mv64x60_get_bridge_base();
|
||||
|
||||
platform_ops.fixups = c2k_fixups;
|
||||
platform_ops.exit = c2k_reset;
|
||||
|
||||
if (serial_console_init() < 0)
|
||||
exit();
|
||||
}
|
||||
@@ -1,366 +0,0 @@
|
||||
/* Device Tree Source for GEFanuc C2K
|
||||
*
|
||||
* Author: Remi Machet <rmachet@slac.stanford.edu>
|
||||
*
|
||||
* Originated from prpmc2800.dts
|
||||
*
|
||||
* 2008 (c) Stanford University
|
||||
* 2007 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "C2K";
|
||||
compatible = "GEFanuc,C2K";
|
||||
coherency-off;
|
||||
|
||||
aliases {
|
||||
pci0 = &PCI0;
|
||||
pci1 = &PCI1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "PowerPC,7447";
|
||||
reg = <0>;
|
||||
clock-frequency = <996000000>; /* 996 MHz */
|
||||
bus-frequency = <166666667>; /* 166.6666 MHz */
|
||||
timebase-frequency = <41666667>; /* 166.6666/4 MHz */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
system-controller@d8000000 { /* Marvell Discovery */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "mv64460";
|
||||
compatible = "marvell,mv64360";
|
||||
clock-frequency = <166666667>; /* 166.66... MHz */
|
||||
reg = <0xd8000000 0x00010000>;
|
||||
virtual-reg = <0xd8000000>;
|
||||
ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
|
||||
0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
|
||||
0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
|
||||
0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
|
||||
0xd8100000 0xd8100000 0x00010000 /* FPGA */
|
||||
0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
|
||||
0xf8000000 0xf8000000 0x08000000 /* User FLASH */
|
||||
0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
|
||||
0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
|
||||
|
||||
mdio@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-mdio";
|
||||
reg = <0x2000 4>;
|
||||
PHY0: ethernet-phy@0 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0>;
|
||||
};
|
||||
PHY1: ethernet-phy@1 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <1>;
|
||||
};
|
||||
PHY2: ethernet-phy@2 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-group@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-eth-group";
|
||||
reg = <0x2000 0x2000>;
|
||||
ethernet@0 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <0>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY0>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@1 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <1>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@2 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <2>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY2>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
};
|
||||
|
||||
SDMA0: sdma@4000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x4000 0xc18>;
|
||||
virtual-reg = <0xd8004000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <36>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
SDMA1: sdma@6000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x6000 0xc18>;
|
||||
virtual-reg = <0xd8006000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <38>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
BRG0: brg@b200 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb200 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
BRG1: brg@b208 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb208 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
CUNIT: cunit@f200 {
|
||||
reg = <0xf200 0x200>;
|
||||
};
|
||||
|
||||
MPSCROUTING: mpscrouting@b400 {
|
||||
reg = <0xb400 0xc>;
|
||||
};
|
||||
|
||||
MPSCINTR: mpscintr@b800 {
|
||||
reg = <0xb800 0x100>;
|
||||
virtual-reg = <0xd800b800>;
|
||||
};
|
||||
|
||||
MPSC0: mpsc@8000 {
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x8000 0x38>;
|
||||
virtual-reg = <0xd8008000>;
|
||||
sdma = <&SDMA0>;
|
||||
brg = <&BRG0>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <0>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
MPSC1: mpsc@9000 {
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x9000 0x38>;
|
||||
virtual-reg = <0xd8009000>;
|
||||
sdma = <&SDMA1>;
|
||||
brg = <&BRG1>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <1>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
wdt@b410 { /* watchdog timer */
|
||||
compatible = "marvell,mv64360-wdt";
|
||||
reg = <0xb410 0x8>;
|
||||
};
|
||||
|
||||
i2c@c000 {
|
||||
compatible = "marvell,mv64360-i2c";
|
||||
reg = <0xc000 0x20>;
|
||||
virtual-reg = <0xd800c000>;
|
||||
interrupts = <37>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
PIC: pic {
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
compatible = "marvell,mv64360-pic";
|
||||
reg = <0x0000 0x88>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
mpp@f000 {
|
||||
compatible = "marvell,mv64360-mpp";
|
||||
reg = <0xf000 0x10>;
|
||||
};
|
||||
|
||||
gpp@f100 {
|
||||
compatible = "marvell,mv64360-gpp";
|
||||
reg = <0xf100 0x20>;
|
||||
};
|
||||
|
||||
PCI0: pci@80000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0cf8 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0c34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* Only one interrupt line for PMC0 slot (INTA) */
|
||||
0x0000 0 0 1 &PIC 88
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
PCI1: pci@a0000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0c78 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0cb4>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x01: PMC1 ? */
|
||||
0x0800 0 0 1 &PIC 88
|
||||
/* IDSEL 0x02: cPCI bridge */
|
||||
0x1000 0 0 1 &PIC 88
|
||||
/* IDSEL 0x03: USB controller */
|
||||
0x1800 0 0 1 &PIC 91
|
||||
/* IDSEL 0x04: SATA controller */
|
||||
0x2000 0 0 1 &PIC 95
|
||||
>;
|
||||
};
|
||||
|
||||
cpu-error@70 {
|
||||
compatible = "marvell,mv64360-cpu-error";
|
||||
reg = <0x0070 0x10 0x0128 0x28>;
|
||||
interrupts = <3>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
sram-ctrl@380 {
|
||||
compatible = "marvell,mv64360-sram-ctrl";
|
||||
reg = <0x0380 0x80>;
|
||||
interrupts = <13>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1d40 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1d40 0x40 0x0c28 0x4>;
|
||||
interrupts = <12>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1dc0 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1dc0 0x40 0x0ca8 0x4>;
|
||||
interrupts = <16>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
mem-ctrl@1400 {
|
||||
compatible = "marvell,mv64360-mem-ctrl";
|
||||
reg = <0x1400 0x60>;
|
||||
interrupts = <17>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
/* Devices attached to the device controller */
|
||||
devicebus@45c {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "marvell,mv64306-devctrl";
|
||||
reg = <0x45C 0x88>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
ranges = <0 0 0xd8100000 0x10000
|
||||
2 0 0xd8110000 0x10000
|
||||
4 0 0xf8000000 0x8000000>;
|
||||
fpga@0,0 {
|
||||
compatible = "sbs,fpga-c2k";
|
||||
reg = <0 0 0x10000>;
|
||||
};
|
||||
fpga_usart@2,0 {
|
||||
compatible = "sbs,fpga_usart-c2k";
|
||||
reg = <2 0 0x10000>;
|
||||
};
|
||||
nor_flash@4,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <4 0 0x8000000>; /* 128MB */
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "boot";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "kernel";
|
||||
reg = <0x00080000 0x00400000>;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "initrd";
|
||||
reg = <0x00480000 0x00B80000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "rootfs";
|
||||
reg = <0x01000000 0x06800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "recovery";
|
||||
reg = <0x07800000 0x00800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
chosen {
|
||||
stdout-path = &MPSC0;
|
||||
};
|
||||
};
|
||||
@@ -269,7 +269,7 @@
|
||||
|
||||
i2c@118000 {
|
||||
pca9547@77 {
|
||||
compatible = "philips,pca9547";
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
};
|
||||
rtc@68 {
|
||||
|
||||
@@ -1,331 +0,0 @@
|
||||
/*
|
||||
* SBC8349E Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Wind River Inc.
|
||||
*
|
||||
* Paul Gortmaker (see MAINTAINERS for contact information)
|
||||
*
|
||||
* -based largely on the Freescale MPC834x_MDS dts.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "SBC8349E";
|
||||
compatible = "SBC834xE";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8349@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; // 256MB at 0
|
||||
};
|
||||
|
||||
soc8349@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port0;
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
linux,network-index = <0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@19 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <20 0x8>;
|
||||
reg = <0x19>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1a {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <21 0x8>;
|
||||
reg = <0x1a>;
|
||||
};
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
linux,network-index = <1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x7e>;
|
||||
fsl,descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-localbus", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
ranges = <0x0 0x0 0xff800000 0x00800000 /* 8MB Flash */
|
||||
0x1 0x0 0xf8000000 0x00002000 /* 8KB EEPROM */
|
||||
0x2 0x0 0x10000000 0x04000000 /* 64MB SDRAM */
|
||||
0x3 0x0 0x10000000 0x04000000>; /* 64MB SDRAM */
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "intel,28F640J3A", "cfi-flash";
|
||||
reg = <0x0 0x0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x006c0000>;
|
||||
};
|
||||
|
||||
partition@700000 {
|
||||
label = "legacy u-boot";
|
||||
reg = <0x00700000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
0x8800 0x0 0x0 0x1 &ipic 48 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 17 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 18 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 19 0x8>;
|
||||
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <0x42 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100 /* internal registers */
|
||||
0xe0008300 0x8>; /* config space access registers */
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
@@ -24,7 +24,7 @@ u32 mpc885_get_clock(u32 crystal)
|
||||
{
|
||||
u32 *immr;
|
||||
u32 plprcr;
|
||||
int mfi, mfn, mfd, pdf, div;
|
||||
int mfi, mfn, mfd, pdf;
|
||||
u32 ret;
|
||||
|
||||
immr = fsl_get_immr();
|
||||
@@ -43,7 +43,6 @@ u32 mpc885_get_clock(u32 crystal)
|
||||
}
|
||||
|
||||
pdf = (plprcr >> 1) & 0xf;
|
||||
div = (plprcr >> 20) & 3;
|
||||
mfd = (plprcr >> 22) & 0x1f;
|
||||
mfn = (plprcr >> 27) & 0x1f;
|
||||
|
||||
|
||||
@@ -1,169 +0,0 @@
|
||||
/*
|
||||
* MPSC/UART driver for the Marvell mv64360, mv64460, ...
|
||||
*
|
||||
* Author: Mark A. Greer <mgreer@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include "ops.h"
|
||||
|
||||
|
||||
#define MPSC_CHR_1 0x000c
|
||||
|
||||
#define MPSC_CHR_2 0x0010
|
||||
#define MPSC_CHR_2_TA (1<<7)
|
||||
#define MPSC_CHR_2_TCS (1<<9)
|
||||
#define MPSC_CHR_2_RA (1<<23)
|
||||
#define MPSC_CHR_2_CRD (1<<25)
|
||||
#define MPSC_CHR_2_EH (1<<31)
|
||||
|
||||
#define MPSC_CHR_4 0x0018
|
||||
#define MPSC_CHR_4_Z (1<<29)
|
||||
|
||||
#define MPSC_CHR_5 0x001c
|
||||
#define MPSC_CHR_5_CTL1_INTR (1<<12)
|
||||
#define MPSC_CHR_5_CTL1_VALID (1<<15)
|
||||
|
||||
#define MPSC_CHR_10 0x0030
|
||||
|
||||
#define MPSC_INTR_CAUSE 0x0000
|
||||
#define MPSC_INTR_CAUSE_RCC (1<<6)
|
||||
#define MPSC_INTR_MASK 0x0080
|
||||
|
||||
#define SDMA_SDCM 0x0008
|
||||
#define SDMA_SDCM_AR (1<<15)
|
||||
#define SDMA_SDCM_AT (1<<31)
|
||||
|
||||
static volatile char *mpsc_base;
|
||||
static volatile char *mpscintr_base;
|
||||
static u32 chr1, chr2;
|
||||
|
||||
static int mpsc_open(void)
|
||||
{
|
||||
chr1 = in_le32((u32 *)(mpsc_base + MPSC_CHR_1)) & 0x00ff0000;
|
||||
chr2 = in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & ~(MPSC_CHR_2_TA
|
||||
| MPSC_CHR_2_TCS | MPSC_CHR_2_RA | MPSC_CHR_2_CRD
|
||||
| MPSC_CHR_2_EH);
|
||||
out_le32((u32 *)(mpsc_base + MPSC_CHR_4), MPSC_CHR_4_Z);
|
||||
out_le32((u32 *)(mpsc_base + MPSC_CHR_5),
|
||||
MPSC_CHR_5_CTL1_INTR | MPSC_CHR_5_CTL1_VALID);
|
||||
out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_EH);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mpsc_putc(unsigned char c)
|
||||
{
|
||||
while (in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & MPSC_CHR_2_TCS);
|
||||
|
||||
out_le32((u32 *)(mpsc_base + MPSC_CHR_1), chr1 | c);
|
||||
out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_TCS);
|
||||
}
|
||||
|
||||
static unsigned char mpsc_getc(void)
|
||||
{
|
||||
u32 cause = 0;
|
||||
unsigned char c;
|
||||
|
||||
while (!(cause & MPSC_INTR_CAUSE_RCC))
|
||||
cause = in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE));
|
||||
|
||||
c = in_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2));
|
||||
out_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2), c);
|
||||
out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE),
|
||||
cause & ~MPSC_INTR_CAUSE_RCC);
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
static u8 mpsc_tstc(void)
|
||||
{
|
||||
return (u8)((in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE))
|
||||
& MPSC_INTR_CAUSE_RCC) != 0);
|
||||
}
|
||||
|
||||
static void mpsc_stop_dma(volatile char *sdma_base)
|
||||
{
|
||||
out_le32((u32 *)(mpsc_base + MPSC_CHR_2),MPSC_CHR_2_TA | MPSC_CHR_2_RA);
|
||||
out_le32((u32 *)(sdma_base + SDMA_SDCM), SDMA_SDCM_AR | SDMA_SDCM_AT);
|
||||
|
||||
while ((in_le32((u32 *)(sdma_base + SDMA_SDCM))
|
||||
& (SDMA_SDCM_AR | SDMA_SDCM_AT)) != 0)
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
static volatile char *mpsc_get_virtreg_of_phandle(void *devp, char *prop)
|
||||
{
|
||||
void *v;
|
||||
int n;
|
||||
|
||||
n = getprop(devp, prop, &v, sizeof(v));
|
||||
if (n != sizeof(v))
|
||||
goto err_out;
|
||||
|
||||
devp = find_node_by_linuxphandle((u32)v);
|
||||
if (devp == NULL)
|
||||
goto err_out;
|
||||
|
||||
n = getprop(devp, "virtual-reg", &v, sizeof(v));
|
||||
if (n == sizeof(v))
|
||||
return v;
|
||||
|
||||
err_out:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int mpsc_console_init(void *devp, struct serial_console_data *scdp)
|
||||
{
|
||||
void *v;
|
||||
int n, reg_set;
|
||||
volatile char *sdma_base;
|
||||
|
||||
n = getprop(devp, "virtual-reg", &v, sizeof(v));
|
||||
if (n != sizeof(v))
|
||||
goto err_out;
|
||||
mpsc_base = v;
|
||||
|
||||
sdma_base = mpsc_get_virtreg_of_phandle(devp, "sdma");
|
||||
if (sdma_base == NULL)
|
||||
goto err_out;
|
||||
|
||||
mpscintr_base = mpsc_get_virtreg_of_phandle(devp, "mpscintr");
|
||||
if (mpscintr_base == NULL)
|
||||
goto err_out;
|
||||
|
||||
n = getprop(devp, "cell-index", &v, sizeof(v));
|
||||
if (n != sizeof(v))
|
||||
goto err_out;
|
||||
reg_set = (int)v;
|
||||
|
||||
mpscintr_base += (reg_set == 0) ? 0x4 : 0xc;
|
||||
|
||||
/* Make sure the mpsc ctlrs are shutdown */
|
||||
out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
|
||||
out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
|
||||
out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
|
||||
out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
|
||||
|
||||
mpsc_stop_dma(sdma_base);
|
||||
|
||||
scdp->open = mpsc_open;
|
||||
scdp->putc = mpsc_putc;
|
||||
scdp->getc = mpsc_getc;
|
||||
scdp->tstc = mpsc_tstc;
|
||||
scdp->close = NULL;
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
return -1;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,70 +0,0 @@
|
||||
/*
|
||||
* Author: Mark A. Greer <source@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef _PPC_BOOT_MV64x60_H_
|
||||
#define _PPC_BOOT_MV64x60_H_
|
||||
|
||||
#define MV64x60_CPU_BAR_ENABLE 0x0278
|
||||
|
||||
#define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0)
|
||||
#define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1)
|
||||
#define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
|
||||
#define MV64x60_PCI_ACC_CNTL_SNOOP_WT 0x00000004
|
||||
#define MV64x60_PCI_ACC_CNTL_SNOOP_WB 0x00000008
|
||||
#define MV64x60_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
|
||||
#define MV64x60_PCI_ACC_CNTL_ACCPROT (1<<4)
|
||||
#define MV64x60_PCI_ACC_CNTL_WRPROT (1<<5)
|
||||
#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
|
||||
#define MV64x60_PCI_ACC_CNTL_SWAP_NONE 0x00000040
|
||||
#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
|
||||
#define MV64x60_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
|
||||
#define MV64x60_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
|
||||
#define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
|
||||
#define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
|
||||
#define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
|
||||
#define MV64x60_PCI_ACC_CNTL_MBURST_MASK 0x00000300
|
||||
#define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
|
||||
#define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
|
||||
#define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
|
||||
#define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
|
||||
#define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
|
||||
|
||||
struct mv64x60_cpu2pci_win {
|
||||
u32 lo;
|
||||
u32 size;
|
||||
u32 remap_hi;
|
||||
u32 remap_lo;
|
||||
};
|
||||
|
||||
extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2];
|
||||
extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2];
|
||||
|
||||
u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
|
||||
u8 offset);
|
||||
void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
|
||||
u8 offset, u32 val);
|
||||
|
||||
void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
|
||||
u8 is_coherent);
|
||||
void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
|
||||
u8 bus, u32 mem_size, u32 acc_bits);
|
||||
void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
|
||||
u32 pci_base_lo, u32 cpu_base, u32 size,
|
||||
struct mv64x60_cpu2pci_win *offset_tbl);
|
||||
u32 mv64x60_get_mem_size(u8 *bridge_base);
|
||||
u8 *mv64x60_get_bridge_pbase(void);
|
||||
u8 *mv64x60_get_bridge_base(void);
|
||||
u8 mv64x60_is_coherent(void);
|
||||
|
||||
int mv64x60_i2c_open(void);
|
||||
int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
|
||||
u32 count);
|
||||
void mv64x60_i2c_close(void);
|
||||
|
||||
#endif /* _PPC_BOOT_MV64x60_H_ */
|
||||
@@ -1,204 +0,0 @@
|
||||
/*
|
||||
* Bootloader version of the i2c driver for the MV64x60.
|
||||
*
|
||||
* Author: Dale Farnsworth <dfarnsworth@mvista.com>
|
||||
* Maintained by: Mark A. Greer <mgreer@mvista.com>
|
||||
*
|
||||
* 2003, 2007 (c) MontaVista, Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express or
|
||||
* implied.
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "elf.h"
|
||||
#include "page.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include "ops.h"
|
||||
#include "mv64x60.h"
|
||||
|
||||
/* Register defines */
|
||||
#define MV64x60_I2C_REG_SLAVE_ADDR 0x00
|
||||
#define MV64x60_I2C_REG_DATA 0x04
|
||||
#define MV64x60_I2C_REG_CONTROL 0x08
|
||||
#define MV64x60_I2C_REG_STATUS 0x0c
|
||||
#define MV64x60_I2C_REG_BAUD 0x0c
|
||||
#define MV64x60_I2C_REG_EXT_SLAVE_ADDR 0x10
|
||||
#define MV64x60_I2C_REG_SOFT_RESET 0x1c
|
||||
|
||||
#define MV64x60_I2C_CONTROL_ACK 0x04
|
||||
#define MV64x60_I2C_CONTROL_IFLG 0x08
|
||||
#define MV64x60_I2C_CONTROL_STOP 0x10
|
||||
#define MV64x60_I2C_CONTROL_START 0x20
|
||||
#define MV64x60_I2C_CONTROL_TWSIEN 0x40
|
||||
#define MV64x60_I2C_CONTROL_INTEN 0x80
|
||||
|
||||
#define MV64x60_I2C_STATUS_BUS_ERR 0x00
|
||||
#define MV64x60_I2C_STATUS_MAST_START 0x08
|
||||
#define MV64x60_I2C_STATUS_MAST_REPEAT_START 0x10
|
||||
#define MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
|
||||
#define MV64x60_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
|
||||
#define MV64x60_I2C_STATUS_MAST_WR_ACK 0x28
|
||||
#define MV64x60_I2C_STATUS_MAST_WR_NO_ACK 0x30
|
||||
#define MV64x60_I2C_STATUS_MAST_LOST_ARB 0x38
|
||||
#define MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
|
||||
#define MV64x60_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
|
||||
#define MV64x60_I2C_STATUS_MAST_RD_DATA_ACK 0x50
|
||||
#define MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
|
||||
#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
|
||||
#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
|
||||
#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
|
||||
#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
|
||||
#define MV64x60_I2C_STATUS_NO_STATUS 0xf8
|
||||
|
||||
static u8 *ctlr_base;
|
||||
|
||||
static int mv64x60_i2c_wait_for_status(int wanted)
|
||||
{
|
||||
int i;
|
||||
int status;
|
||||
|
||||
for (i=0; i<1000; i++) {
|
||||
udelay(10);
|
||||
status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS))
|
||||
& 0xff;
|
||||
if (status == wanted)
|
||||
return status;
|
||||
}
|
||||
return -status;
|
||||
}
|
||||
|
||||
static int mv64x60_i2c_control(int control, int status)
|
||||
{
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
|
||||
return mv64x60_i2c_wait_for_status(status);
|
||||
}
|
||||
|
||||
static int mv64x60_i2c_read_byte(int control, int status)
|
||||
{
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
|
||||
if (mv64x60_i2c_wait_for_status(status) < 0)
|
||||
return -1;
|
||||
return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff;
|
||||
}
|
||||
|
||||
static int mv64x60_i2c_write_byte(int data, int control, int status)
|
||||
{
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff);
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
|
||||
return mv64x60_i2c_wait_for_status(status);
|
||||
}
|
||||
|
||||
int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
|
||||
u32 count)
|
||||
{
|
||||
int i;
|
||||
int data;
|
||||
int control;
|
||||
int status;
|
||||
|
||||
if (ctlr_base == NULL)
|
||||
return -1;
|
||||
|
||||
/* send reset */
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0);
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0);
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0);
|
||||
out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4);
|
||||
|
||||
if (mv64x60_i2c_control(MV64x60_I2C_CONTROL_TWSIEN,
|
||||
MV64x60_I2C_STATUS_NO_STATUS) < 0)
|
||||
return -1;
|
||||
|
||||
/* send start */
|
||||
control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_MAST_START;
|
||||
if (mv64x60_i2c_control(control, status) < 0)
|
||||
return -1;
|
||||
|
||||
/* select device for writing */
|
||||
data = devaddr & ~0x1;
|
||||
control = MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK;
|
||||
if (mv64x60_i2c_write_byte(data, control, status) < 0)
|
||||
return -1;
|
||||
|
||||
/* send offset of data */
|
||||
control = MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_MAST_WR_ACK;
|
||||
if (offset_size > 1) {
|
||||
if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0)
|
||||
return -1;
|
||||
}
|
||||
if (mv64x60_i2c_write_byte(offset, control, status) < 0)
|
||||
return -1;
|
||||
|
||||
/* resend start */
|
||||
control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_MAST_REPEAT_START;
|
||||
if (mv64x60_i2c_control(control, status) < 0)
|
||||
return -1;
|
||||
|
||||
/* select device for reading */
|
||||
data = devaddr | 0x1;
|
||||
control = MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK;
|
||||
if (mv64x60_i2c_write_byte(data, control, status) < 0)
|
||||
return -1;
|
||||
|
||||
/* read all but last byte of data */
|
||||
control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_MAST_RD_DATA_ACK;
|
||||
|
||||
for (i=1; i<count; i++) {
|
||||
data = mv64x60_i2c_read_byte(control, status);
|
||||
if (data < 0) {
|
||||
printf("errors on iteration %d\n", i);
|
||||
return -1;
|
||||
}
|
||||
*buf++ = data;
|
||||
}
|
||||
|
||||
/* read last byte of data */
|
||||
control = MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK;
|
||||
data = mv64x60_i2c_read_byte(control, status);
|
||||
if (data < 0)
|
||||
return -1;
|
||||
*buf++ = data;
|
||||
|
||||
/* send stop */
|
||||
control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN;
|
||||
status = MV64x60_I2C_STATUS_NO_STATUS;
|
||||
if (mv64x60_i2c_control(control, status) < 0)
|
||||
return -1;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
int mv64x60_i2c_open(void)
|
||||
{
|
||||
u32 v;
|
||||
void *devp;
|
||||
|
||||
devp = find_node_by_compatible(NULL, "marvell,mv64360-i2c");
|
||||
if (devp == NULL)
|
||||
goto err_out;
|
||||
if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
|
||||
goto err_out;
|
||||
|
||||
ctlr_base = (u8 *)v;
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
return -1;
|
||||
}
|
||||
|
||||
void mv64x60_i2c_close(void)
|
||||
{
|
||||
ctlr_base = NULL;
|
||||
}
|
||||
@@ -86,7 +86,6 @@ void start(void);
|
||||
void fdt_init(void *blob);
|
||||
int serial_console_init(void);
|
||||
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int mpsc_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int cpm_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
|
||||
int uartlite_console_init(void *devp, struct serial_console_data *scdp);
|
||||
|
||||
@@ -120,10 +120,6 @@ int serial_console_init(void)
|
||||
if (dt_is_compatible(devp, "ns16550") ||
|
||||
dt_is_compatible(devp, "pnpPNP,501"))
|
||||
rc = ns16550_console_init(devp, &serial_cd);
|
||||
#ifdef CONFIG_EMBEDDED6xx
|
||||
else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
|
||||
rc = mpsc_console_init(devp, &serial_cd);
|
||||
#endif
|
||||
#ifdef CONFIG_CPM
|
||||
else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
|
||||
dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
|
||||
|
||||
@@ -1,74 +0,0 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_KALLSYMS is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_83xx=y
|
||||
CONFIG_SBC834x=y
|
||||
CONFIG_GEN_RTC=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=32768
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_SERIAL_8250_PCI is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_WATCHDOG=y
|
||||
# CONFIG_USB_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_FSL=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CRYPTO_ECB=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
@@ -1,389 +0,0 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=m
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_OSF_PARTITION=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_BSD_DISKLABEL=y
|
||||
CONFIG_MINIX_SUBPARTITION=y
|
||||
CONFIG_SOLARIS_X86_PARTITION=y
|
||||
CONFIG_UNIXWARE_DISKLABEL=y
|
||||
CONFIG_SGI_PARTITION=y
|
||||
CONFIG_SUN_PARTITION=y
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_EMBEDDED6xx=y
|
||||
CONFIG_PPC_C2K=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
|
||||
CONFIG_GEN_RTC=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_PREEMPT_VOLUNTARY=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
CONFIG_HOTPLUG_PCI_SHPC=m
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_MATCH_ECN=m
|
||||
CONFIG_IP_NF_MATCH_TTL=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_TARGET_ECN=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_IP_NF_ARPTABLES=m
|
||||
CONFIG_IP_NF_ARPFILTER=m
|
||||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_MATCH_EUI64=m
|
||||
CONFIG_IP6_NF_MATCH_FRAG=m
|
||||
CONFIG_IP6_NF_MATCH_OPTS=m
|
||||
CONFIG_IP6_NF_MATCH_HL=m
|
||||
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
|
||||
CONFIG_IP6_NF_MATCH_RT=m
|
||||
CONFIG_IP6_NF_FILTER=m
|
||||
CONFIG_IP6_NF_MANGLE=m
|
||||
CONFIG_IP6_NF_RAW=m
|
||||
CONFIG_BRIDGE_NF_EBTABLES=m
|
||||
CONFIG_BRIDGE_EBT_BROUTE=m
|
||||
CONFIG_BRIDGE_EBT_T_FILTER=m
|
||||
CONFIG_BRIDGE_EBT_T_NAT=m
|
||||
CONFIG_BRIDGE_EBT_802_3=m
|
||||
CONFIG_BRIDGE_EBT_AMONG=m
|
||||
CONFIG_BRIDGE_EBT_ARP=m
|
||||
CONFIG_BRIDGE_EBT_IP=m
|
||||
CONFIG_BRIDGE_EBT_LIMIT=m
|
||||
CONFIG_BRIDGE_EBT_MARK=m
|
||||
CONFIG_BRIDGE_EBT_PKTTYPE=m
|
||||
CONFIG_BRIDGE_EBT_STP=m
|
||||
CONFIG_BRIDGE_EBT_VLAN=m
|
||||
CONFIG_BRIDGE_EBT_ARPREPLY=m
|
||||
CONFIG_BRIDGE_EBT_DNAT=m
|
||||
CONFIG_BRIDGE_EBT_MARK_T=m
|
||||
CONFIG_BRIDGE_EBT_REDIRECT=m
|
||||
CONFIG_BRIDGE_EBT_SNAT=m
|
||||
CONFIG_BRIDGE_EBT_LOG=m
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_ATM=m
|
||||
CONFIG_ATM_CLIP=m
|
||||
CONFIG_ATM_LANE=m
|
||||
CONFIG_ATM_BR2684=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_CBQ=m
|
||||
CONFIG_NET_SCH_HTB=m
|
||||
CONFIG_NET_SCH_HFSC=m
|
||||
CONFIG_NET_SCH_ATM=m
|
||||
CONFIG_NET_SCH_PRIO=m
|
||||
CONFIG_NET_SCH_RED=m
|
||||
CONFIG_NET_SCH_SFQ=m
|
||||
CONFIG_NET_SCH_TEQL=m
|
||||
CONFIG_NET_SCH_TBF=m
|
||||
CONFIG_NET_SCH_GRED=m
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_NETEM=m
|
||||
CONFIG_NET_CLS_TCINDEX=m
|
||||
CONFIG_NET_CLS_ROUTE4=m
|
||||
CONFIG_NET_CLS_FW=m
|
||||
CONFIG_NET_CLS_U32=m
|
||||
CONFIG_CLS_U32_PERF=y
|
||||
CONFIG_NET_CLS_RSVP=m
|
||||
CONFIG_NET_CLS_RSVP6=m
|
||||
CONFIG_NET_CLS_IND=y
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_RFCOMM=m
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=m
|
||||
CONFIG_BT_BNEP_MC_FILTER=y
|
||||
CONFIG_BT_BNEP_PROTO_FILTER=y
|
||||
CONFIG_BT_HIDP=m
|
||||
CONFIG_BT_HCIUART=m
|
||||
CONFIG_BT_HCIUART_H4=y
|
||||
CONFIG_BT_HCIUART_BCSP=y
|
||||
CONFIG_BT_HCIBCM203X=m
|
||||
CONFIG_BT_HCIBFUSB=m
|
||||
CONFIG_BT_HCIVHCI=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_SCSI=m
|
||||
CONFIG_BLK_DEV_SD=m
|
||||
CONFIG_CHR_DEV_ST=m
|
||||
CONFIG_CHR_DEV_OSST=m
|
||||
CONFIG_BLK_DEV_SR=m
|
||||
CONFIG_BLK_DEV_SR_VENDOR=y
|
||||
CONFIG_CHR_DEV_SG=m
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_ISCSI_ATTRS=m
|
||||
CONFIG_BLK_DEV_3W_XXXX_RAID=m
|
||||
CONFIG_SCSI_3W_9XXX=m
|
||||
CONFIG_SCSI_ACARD=m
|
||||
CONFIG_SCSI_AACRAID=m
|
||||
CONFIG_SCSI_AIC7XXX=m
|
||||
CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
|
||||
CONFIG_AIC7XXX_RESET_DELAY_MS=15000
|
||||
# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
|
||||
# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
|
||||
CONFIG_SCSI_AIC79XX=m
|
||||
CONFIG_AIC79XX_CMDS_PER_DEVICE=4
|
||||
CONFIG_AIC79XX_RESET_DELAY_MS=15000
|
||||
# CONFIG_AIC79XX_DEBUG_ENABLE is not set
|
||||
# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
|
||||
CONFIG_SCSI_ARCMSR=m
|
||||
CONFIG_MEGARAID_NEWGEN=y
|
||||
CONFIG_MEGARAID_MM=m
|
||||
CONFIG_MEGARAID_MAILBOX=m
|
||||
CONFIG_MEGARAID_SAS=m
|
||||
CONFIG_SCSI_GDTH=m
|
||||
CONFIG_SCSI_IPS=m
|
||||
CONFIG_SCSI_INITIO=m
|
||||
CONFIG_SCSI_SYM53C8XX_2=m
|
||||
CONFIG_SCSI_QLOGIC_1280=m
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BONDING=m
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_NETCONSOLE=m
|
||||
CONFIG_TUN=m
|
||||
# CONFIG_ATM_DRIVERS is not set
|
||||
CONFIG_MV643XX_ETH=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_UINPUT=m
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_NONSTANDARD=y
|
||||
CONFIG_SERIAL_MPSC=y
|
||||
CONFIG_SERIAL_MPSC_CONSOLE=y
|
||||
CONFIG_NVRAM=m
|
||||
CONFIG_RAW_DRIVER=y
|
||||
CONFIG_MAX_RAW_DEVS=8192
|
||||
CONFIG_I2C=m
|
||||
CONFIG_I2C_CHARDEV=m
|
||||
CONFIG_I2C_MV64XXX=m
|
||||
CONFIG_HWMON=m
|
||||
CONFIG_SENSORS_ADM1021=m
|
||||
CONFIG_SENSORS_ADM1025=m
|
||||
CONFIG_SENSORS_ADM1026=m
|
||||
CONFIG_SENSORS_ADM1031=m
|
||||
CONFIG_SENSORS_DS1621=m
|
||||
CONFIG_SENSORS_GL518SM=m
|
||||
CONFIG_SENSORS_MAX1619=m
|
||||
CONFIG_SENSORS_LM75=m
|
||||
CONFIG_SENSORS_LM77=m
|
||||
CONFIG_SENSORS_LM78=m
|
||||
CONFIG_SENSORS_LM80=m
|
||||
CONFIG_SENSORS_LM83=m
|
||||
CONFIG_SENSORS_LM85=m
|
||||
CONFIG_SENSORS_LM87=m
|
||||
CONFIG_SENSORS_LM90=m
|
||||
CONFIG_SENSORS_PCF8591=m
|
||||
CONFIG_SENSORS_VIA686A=m
|
||||
CONFIG_SENSORS_W83781D=m
|
||||
CONFIG_SENSORS_W83L785TS=m
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_SOFT_WATCHDOG=m
|
||||
CONFIG_PCIPCWATCHDOG=m
|
||||
CONFIG_WDTPCI=m
|
||||
CONFIG_USBPCWATCHDOG=m
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_USB=m
|
||||
CONFIG_USB_MON=m
|
||||
CONFIG_USB_EHCI_HCD=m
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
CONFIG_USB_OHCI_HCD=m
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
|
||||
CONFIG_USB_UHCI_HCD=m
|
||||
CONFIG_USB_ACM=m
|
||||
CONFIG_USB_PRINTER=m
|
||||
CONFIG_USB_STORAGE=m
|
||||
CONFIG_USB_STORAGE_DATAFAB=m
|
||||
CONFIG_USB_STORAGE_FREECOM=m
|
||||
CONFIG_USB_STORAGE_ISD200=m
|
||||
CONFIG_USB_STORAGE_SDDR09=m
|
||||
CONFIG_USB_STORAGE_SDDR55=m
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=m
|
||||
CONFIG_USB_MDC800=m
|
||||
CONFIG_USB_MICROTEK=m
|
||||
CONFIG_USB_SERIAL=m
|
||||
CONFIG_USB_SERIAL_GENERIC=y
|
||||
CONFIG_USB_SERIAL_BELKIN=m
|
||||
CONFIG_USB_SERIAL_WHITEHEAT=m
|
||||
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
|
||||
CONFIG_USB_SERIAL_EMPEG=m
|
||||
CONFIG_USB_SERIAL_FTDI_SIO=m
|
||||
CONFIG_USB_SERIAL_VISOR=m
|
||||
CONFIG_USB_SERIAL_IPAQ=m
|
||||
CONFIG_USB_SERIAL_IR=m
|
||||
CONFIG_USB_SERIAL_EDGEPORT=m
|
||||
CONFIG_USB_SERIAL_EDGEPORT_TI=m
|
||||
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
|
||||
CONFIG_USB_SERIAL_KEYSPAN=m
|
||||
CONFIG_USB_SERIAL_KLSI=m
|
||||
CONFIG_USB_SERIAL_KOBIL_SCT=m
|
||||
CONFIG_USB_SERIAL_MCT_U232=m
|
||||
CONFIG_USB_SERIAL_PL2303=m
|
||||
CONFIG_USB_SERIAL_SAFE=m
|
||||
CONFIG_USB_SERIAL_SAFE_PADDED=y
|
||||
CONFIG_USB_SERIAL_CYBERJACK=m
|
||||
CONFIG_USB_SERIAL_XIRCOM=m
|
||||
CONFIG_USB_SERIAL_OMNINET=m
|
||||
CONFIG_USB_EMI62=m
|
||||
CONFIG_USB_RIO500=m
|
||||
CONFIG_USB_LEGOTOWER=m
|
||||
CONFIG_USB_LCD=m
|
||||
CONFIG_USB_LED=m
|
||||
CONFIG_USB_TEST=m
|
||||
CONFIG_USB_ATM=m
|
||||
CONFIG_USB_SPEEDTOUCH=m
|
||||
CONFIG_INFINIBAND=m
|
||||
CONFIG_INFINIBAND_USER_MAD=m
|
||||
CONFIG_INFINIBAND_USER_ACCESS=m
|
||||
CONFIG_INFINIBAND_MTHCA=m
|
||||
CONFIG_INFINIBAND_IPOIB=m
|
||||
CONFIG_INFINIBAND_IPOIB_CM=y
|
||||
CONFIG_INFINIBAND_SRP=m
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_EXT4_FS=m
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QFMT_V2=y
|
||||
CONFIG_AUTOFS4_FS=m
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_HFS_FS=m
|
||||
CONFIG_HFSPLUS_FS=m
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_CRAMFS=m
|
||||
CONFIG_VXFS_FS=m
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_DEFAULT="utf8"
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
CONFIG_NLS_CODEPAGE_852=m
|
||||
CONFIG_NLS_CODEPAGE_855=m
|
||||
CONFIG_NLS_CODEPAGE_857=m
|
||||
CONFIG_NLS_CODEPAGE_860=m
|
||||
CONFIG_NLS_CODEPAGE_861=m
|
||||
CONFIG_NLS_CODEPAGE_862=m
|
||||
CONFIG_NLS_CODEPAGE_863=m
|
||||
CONFIG_NLS_CODEPAGE_864=m
|
||||
CONFIG_NLS_CODEPAGE_865=m
|
||||
CONFIG_NLS_CODEPAGE_866=m
|
||||
CONFIG_NLS_CODEPAGE_869=m
|
||||
CONFIG_NLS_CODEPAGE_936=m
|
||||
CONFIG_NLS_CODEPAGE_950=m
|
||||
CONFIG_NLS_CODEPAGE_932=m
|
||||
CONFIG_NLS_CODEPAGE_949=m
|
||||
CONFIG_NLS_CODEPAGE_874=m
|
||||
CONFIG_NLS_ISO8859_8=m
|
||||
CONFIG_NLS_CODEPAGE_1250=m
|
||||
CONFIG_NLS_CODEPAGE_1251=m
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_NLS_ISO8859_2=m
|
||||
CONFIG_NLS_ISO8859_3=m
|
||||
CONFIG_NLS_ISO8859_4=m
|
||||
CONFIG_NLS_ISO8859_5=m
|
||||
CONFIG_NLS_ISO8859_6=m
|
||||
CONFIG_NLS_ISO8859_7=m
|
||||
CONFIG_NLS_ISO8859_9=m
|
||||
CONFIG_NLS_ISO8859_13=m
|
||||
CONFIG_NLS_ISO8859_14=m
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_KOI8_R=m
|
||||
CONFIG_NLS_KOI8_U=m
|
||||
CONFIG_CRC_CCITT=m
|
||||
CONFIG_CRC_T10DIF=m
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
CONFIG_DEBUG_HIGHMEM=y
|
||||
CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_BOOTX_TEXT=y
|
||||
CONFIG_PPC_EARLY_DEBUG=y
|
||||
CONFIG_SECURITY=y
|
||||
CONFIG_SECURITY_NETWORK=y
|
||||
CONFIG_SECURITY_SELINUX=y
|
||||
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
|
||||
CONFIG_SECURITY_SELINUX_DISABLE=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
@@ -38,7 +38,9 @@ CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_SCOM_DEBUGFS=y
|
||||
CONFIG_OPAL_PRD=y
|
||||
CONFIG_PPC_MEMTRACE=y
|
||||
# CONFIG_PPC_PSERIES is not set
|
||||
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
@@ -54,7 +56,10 @@ CONFIG_NUMA=y
|
||||
CONFIG_MEMORY_HOTPLUG=y
|
||||
CONFIG_MEMORY_HOTREMOVE=y
|
||||
CONFIG_KSM=y
|
||||
CONFIG_MEMORY_FAILURE=y
|
||||
CONFIG_HWPOISON_INJECT=m
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_DEFERRED_STRUCT_PAGE_INIT=y
|
||||
CONFIG_PPC_64K_PAGES=y
|
||||
CONFIG_PPC_SUBPAGE_PROT=y
|
||||
CONFIG_SCHED_SMT=y
|
||||
@@ -72,7 +77,13 @@ CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET6_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_INET6_XFRM_MODE_BEET=m
|
||||
CONFIG_IPV6_SIT=m
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_NETFILTER_ADVANCED is not set
|
||||
CONFIG_BRIDGE=m
|
||||
@@ -81,33 +92,28 @@ CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_CLS_BPF=m
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_BPF=m
|
||||
CONFIG_DNS_RESOLVER=y
|
||||
CONFIG_BPF_JIT=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_POWERNV_FLASH=y
|
||||
CONFIG_PARPORT=m
|
||||
CONFIG_PARPORT_PC=m
|
||||
CONFIG_BLK_DEV_FD=m
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM=m
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
CONFIG_VIRTIO_BLK=m
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECD=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_AMD74XX=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=m
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_BLK_DEV_SR=m
|
||||
CONFIG_BLK_DEV_SR_VENDOR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_SG=m
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_FC_ATTRS=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_SCSI_FC_ATTRS=m
|
||||
CONFIG_SCSI_SRP_ATTRS=y
|
||||
CONFIG_SCSI_CXGB3_ISCSI=m
|
||||
CONFIG_SCSI_CXGB4_ISCSI=m
|
||||
@@ -121,7 +127,6 @@ CONFIG_SCSI_IPR=y
|
||||
CONFIG_SCSI_QLA_FC=m
|
||||
CONFIG_SCSI_QLA_ISCSI=m
|
||||
CONFIG_SCSI_LPFC=m
|
||||
CONFIG_SCSI_VIRTIO=m
|
||||
CONFIG_SCSI_DH=y
|
||||
CONFIG_SCSI_DH_RDAC=m
|
||||
CONFIG_SCSI_DH_ALUA=m
|
||||
@@ -152,16 +157,16 @@ CONFIG_DUMMY=m
|
||||
CONFIG_MACVLAN=m
|
||||
CONFIG_MACVTAP=m
|
||||
CONFIG_VXLAN=m
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_NETCONSOLE=m
|
||||
CONFIG_TUN=m
|
||||
CONFIG_VETH=m
|
||||
CONFIG_VIRTIO_NET=m
|
||||
CONFIG_VORTEX=m
|
||||
CONFIG_ACENIC=m
|
||||
CONFIG_ACENIC_OMIT_TIGON_I=y
|
||||
CONFIG_PCNET32=m
|
||||
CONFIG_TIGON3=y
|
||||
CONFIG_BNX2X=m
|
||||
# CONFIG_CAVIUM_PTP is not set
|
||||
CONFIG_CHELSIO_T1=m
|
||||
CONFIG_BE2NET=m
|
||||
CONFIG_S2IO=m
|
||||
@@ -172,46 +177,62 @@ CONFIG_IXGB=m
|
||||
CONFIG_IXGBE=m
|
||||
CONFIG_I40E=m
|
||||
CONFIG_MLX4_EN=m
|
||||
CONFIG_MLX5_CORE=m
|
||||
CONFIG_MLX5_FPGA=y
|
||||
CONFIG_MLX5_CORE_EN=y
|
||||
CONFIG_MLX5_CORE_IPOIB=y
|
||||
CONFIG_MYRI10GE=m
|
||||
CONFIG_QLGE=m
|
||||
CONFIG_NETXEN_NIC=m
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_BSDCOMP=m
|
||||
CONFIG_PPP_DEFLATE=m
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPP_SYNC_TTY=m
|
||||
CONFIG_USB_NET_DRIVERS=m
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_EVDEV=m
|
||||
CONFIG_INPUT_MISC=y
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_PCI=m
|
||||
CONFIG_SERIAL_JSM=m
|
||||
CONFIG_VIRTIO_CONSOLE=m
|
||||
CONFIG_IPMI_HANDLER=y
|
||||
CONFIG_IPMI_DEVICE_INTERFACE=y
|
||||
CONFIG_IPMI_POWERNV=y
|
||||
CONFIG_RAW_DRIVER=y
|
||||
CONFIG_MAX_RAW_DEVS=1024
|
||||
# CONFIG_DEVPORT is not set
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_AST=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
CONFIG_FB_OF=y
|
||||
CONFIG_FB_MATROX=y
|
||||
CONFIG_FB_MATROX=m
|
||||
CONFIG_FB_MATROX_MILLENIUM=y
|
||||
CONFIG_FB_MATROX_MYSTIQUE=y
|
||||
CONFIG_FB_MATROX_G=y
|
||||
CONFIG_FB_RADEON=y
|
||||
CONFIG_FB_IBM_GXT4500=y
|
||||
CONFIG_FB_RADEON=m
|
||||
CONFIG_FB_IBM_GXT4500=m
|
||||
CONFIG_LCD_PLATFORM=m
|
||||
CONFIG_BACKLIGHT_GENERIC=m
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_HID_A4TECH=m
|
||||
CONFIG_HID_APPLE=m
|
||||
CONFIG_HID_BELKIN=m
|
||||
CONFIG_HID_CHERRY=m
|
||||
CONFIG_HID_CHICONY=m
|
||||
CONFIG_HID_CYPRESS=m
|
||||
CONFIG_HID_EZKEY=m
|
||||
CONFIG_HID_GYRATION=m
|
||||
CONFIG_HID_ITE=m
|
||||
CONFIG_HID_KENSINGTON=m
|
||||
CONFIG_HID_LOGITECH=m
|
||||
CONFIG_HID_MICROSOFT=m
|
||||
CONFIG_HID_MONTEREY=m
|
||||
CONFIG_HID_PANTHERLORD=m
|
||||
CONFIG_HID_PETALYNX=m
|
||||
CONFIG_HID_SAMSUNG=m
|
||||
CONFIG_HID_SUNPLUS=m
|
||||
CONFIG_USB_HID=m
|
||||
CONFIG_USB_HIDDEV=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=m
|
||||
@@ -219,6 +240,7 @@ CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PCI=m
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=m
|
||||
@@ -236,8 +258,9 @@ CONFIG_INFINIBAND_SRP=m
|
||||
CONFIG_INFINIBAND_ISER=m
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_GENERIC=y
|
||||
CONFIG_VIRTIO_PCI=m
|
||||
CONFIG_VIRTIO_BALLOON=m
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_LIBNVDIMM=y
|
||||
# CONFIG_ND_BLK is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
@@ -253,12 +276,13 @@ CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_BTRFS_FS=m
|
||||
CONFIG_BTRFS_FS_POSIX_ACL=y
|
||||
CONFIG_NILFS2_FS=m
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_AUTOFS4_FS=m
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_OVERLAY_FS=m
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
@@ -270,9 +294,9 @@ CONFIG_SQUASHFS_XATTR=y
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_FS=m
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4=m
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_NFSD_V3_ACL=y
|
||||
CONFIG_NFSD_V4=y
|
||||
@@ -291,9 +315,7 @@ CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
CONFIG_SOFTLOCKUP_DETECTOR=y
|
||||
CONFIG_HARDLOCKUP_DETECTOR=y
|
||||
CONFIG_LATENCYTOP=y
|
||||
CONFIG_FTRACE=y
|
||||
CONFIG_FUNCTION_TRACER=y
|
||||
CONFIG_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_SCHED_TRACER=y
|
||||
CONFIG_FTRACE_SYSCALLS=y
|
||||
CONFIG_BLK_DEV_IO_TRACE=y
|
||||
@@ -303,10 +325,10 @@ CONFIG_FTR_FIXUP_SELFTEST=y
|
||||
CONFIG_MSI_BITMAP_SELFTEST=y
|
||||
CONFIG_XMON=y
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_CCM=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_CRC32C_VPMSUM=m
|
||||
CONFIG_CRYPTO_CRCT10DIF_VPMSUM=m
|
||||
CONFIG_CRYPTO_MD5_PPC=m
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_SHA1_PPC=m
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user