mirror of
https://github.com/t2linux/kernel.git
synced 2026-04-30 13:48:59 -07:00
Merge tag 'sfi-removal-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull Simple Firmware Interface (SFI) support removal from Rafael Wysocki: "Drop support for depercated platforms using SFI, drop the entire support for SFI that has been long deprecated too and make some janitorial changes on top of that (Andy Shevchenko)" * tag 'sfi-removal-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: x86/platform/intel-mid: Update Copyright year and drop file names x86/platform/intel-mid: Remove unused header inclusion in intel-mid.h x86/platform/intel-mid: Drop unused __intel_mid_cpu_chip and Co. x86/platform/intel-mid: Get rid of intel_scu_ipc_legacy.h x86/PCI: Describe @reg for type1_access_ok() x86/PCI: Get rid of custom x86 model comparison sfi: Remove framework for deprecated firmware cpufreq: sfi-cpufreq: Remove driver for deprecated firmware media: atomisp: Remove unused header mfd: intel_msic: Remove driver for deprecated platform x86/apb_timer: Remove driver for deprecated platform x86/platform/intel-mid: Remove unused leftovers (vRTC) x86/platform/intel-mid: Remove unused leftovers (msic) x86/platform/intel-mid: Remove unused leftovers (msic_thermal) x86/platform/intel-mid: Remove unused leftovers (msic_power_btn) x86/platform/intel-mid: Remove unused leftovers (msic_gpio) x86/platform/intel-mid: Remove unused leftovers (msic_battery) x86/platform/intel-mid: Remove unused leftovers (msic_ocd) x86/platform/intel-mid: Remove unused leftovers (msic_audio) platform/x86: intel_scu_wdt: Drop mistakenly added const
This commit is contained in:
Linus Torvalds
@@ -1,15 +0,0 @@
|
||||
What: /sys/firmware/sfi/tables/
|
||||
Date: May 2010
|
||||
Contact: Len Brown <lenb@kernel.org>
|
||||
Description:
|
||||
SFI defines a number of small static memory tables
|
||||
so the kernel can get platform information from firmware.
|
||||
|
||||
The tables are defined in the latest SFI specification:
|
||||
http://simplefirmware.org/documentation
|
||||
|
||||
While the tables are used by the kernel, user-space
|
||||
can observe them this way::
|
||||
|
||||
# cd /sys/firmware/sfi/tables
|
||||
# cat $TABLENAME > $TABLENAME.bin
|
||||
@@ -7,7 +7,7 @@ Description:
|
||||
is connected. example: "/dev/ttyS0".
|
||||
|
||||
The device name flows down to architecture specific board
|
||||
initialization file from the SFI/ATAGS bootloader
|
||||
initialization file from the ATAGS bootloader
|
||||
firmware. The name exposed is read from the user-space
|
||||
dameon and opens the device when install is requested.
|
||||
|
||||
|
||||
@@ -5990,12 +5990,6 @@
|
||||
default x2apic cluster mode on platforms
|
||||
supporting x2apic.
|
||||
|
||||
x86_intel_mid_timer= [X86-32,APBT]
|
||||
Choose timer option for x86 Intel MID platform.
|
||||
Two valid options are apbt timer only and lapic timer
|
||||
plus one apbt timer for broadcast timer.
|
||||
x86_intel_mid_timer=apbt_only | lapic_and_apbt
|
||||
|
||||
xen_512gb_limit [KNL,X86-64,XEN]
|
||||
Restricts the kernel running paravirtualized under Xen
|
||||
to use only up to 512 GB of RAM. The reason to do so is
|
||||
|
||||
@@ -9122,9 +9122,7 @@ F: drivers/gpio/gpio-*cove.c
|
||||
INTEL PMIC MULTIFUNCTION DEVICE DRIVERS
|
||||
M: Andy Shevchenko <andy@kernel.org>
|
||||
S: Maintained
|
||||
F: drivers/mfd/intel_msic.c
|
||||
F: drivers/mfd/intel_soc_pmic*
|
||||
F: include/linux/mfd/intel_msic.h
|
||||
F: include/linux/mfd/intel_soc_pmic*
|
||||
|
||||
INTEL PMT DRIVER
|
||||
@@ -16322,13 +16320,6 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml
|
||||
F: drivers/i3c/master/svc-i3c-master.c
|
||||
|
||||
SIMPLE FIRMWARE INTERFACE (SFI)
|
||||
S: Obsolete
|
||||
W: http://simplefirmware.org/
|
||||
F: arch/x86/platform/sfi/
|
||||
F: drivers/sfi/
|
||||
F: include/linux/sfi*.h
|
||||
|
||||
SIMPLEFB FB DRIVER
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
L: linux-fbdev@vger.kernel.org
|
||||
|
||||
+2
-17
@@ -448,7 +448,7 @@ config X86_X2APIC
|
||||
If you don't know what to do here, say N.
|
||||
|
||||
config X86_MPPARSE
|
||||
bool "Enable MPS table" if ACPI || SFI
|
||||
bool "Enable MPS table" if ACPI
|
||||
default y
|
||||
depends on X86_LOCAL_APIC
|
||||
help
|
||||
@@ -607,7 +607,6 @@ config X86_INTEL_MID
|
||||
depends on PCI
|
||||
depends on X86_64 || (PCI_GOANY && X86_32)
|
||||
depends on X86_IO_APIC
|
||||
select SFI
|
||||
select I2C
|
||||
select DW_APB_TIMER
|
||||
select APB_TIMER
|
||||
@@ -896,18 +895,6 @@ config HPET_EMULATE_RTC
|
||||
def_bool y
|
||||
depends on HPET_TIMER && (RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)
|
||||
|
||||
config APB_TIMER
|
||||
def_bool y if X86_INTEL_MID
|
||||
prompt "Intel MID APB Timer Support" if X86_INTEL_MID
|
||||
select DW_APB_TIMER
|
||||
depends on X86_INTEL_MID && SFI
|
||||
help
|
||||
APB timer is the replacement for 8254, HPET on X86 MID platforms.
|
||||
The APBT provides a stable time base on SMP
|
||||
systems, unlike the TSC, but it is more expensive to access,
|
||||
as it is off-chip. APB timers are always running regardless of CPU
|
||||
C states, they are used as per CPU clockevent device when possible.
|
||||
|
||||
# Mark as expert because too many people got it wrong.
|
||||
# The code disables itself when not needed.
|
||||
config DMI
|
||||
@@ -2469,8 +2456,6 @@ source "kernel/power/Kconfig"
|
||||
|
||||
source "drivers/acpi/Kconfig"
|
||||
|
||||
source "drivers/sfi/Kconfig"
|
||||
|
||||
config X86_APM_BOOT
|
||||
def_bool y
|
||||
depends on APM
|
||||
@@ -2657,7 +2642,7 @@ config PCI_DIRECT
|
||||
config PCI_MMCONFIG
|
||||
bool "Support mmconfig PCI config space access" if X86_64
|
||||
default y
|
||||
depends on PCI && (ACPI || SFI || JAILHOUSE_GUEST)
|
||||
depends on PCI && (ACPI || JAILHOUSE_GUEST)
|
||||
depends on X86_64 || (PCI_GOANY || PCI_GOMMCONFIG)
|
||||
|
||||
config PCI_OLPC
|
||||
|
||||
@@ -1,40 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare
|
||||
*
|
||||
* (C) Copyright 2009 Intel Corporation
|
||||
* Author: Jacob Pan (jacob.jun.pan@intel.com)
|
||||
*
|
||||
* Note:
|
||||
*/
|
||||
|
||||
#ifndef ASM_X86_APBT_H
|
||||
#define ASM_X86_APBT_H
|
||||
#include <linux/sfi.h>
|
||||
|
||||
#ifdef CONFIG_APB_TIMER
|
||||
|
||||
/* default memory mapped register base */
|
||||
#define LNW_SCU_ADDR 0xFF100000
|
||||
#define LNW_EXT_TIMER_OFFSET 0x1B800
|
||||
#define APBT_DEFAULT_BASE (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)
|
||||
#define LNW_EXT_TIMER_PGOFFSET 0x800
|
||||
|
||||
/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
|
||||
#define APBT_MAX_FREQ 50000000
|
||||
#define APBT_MIN_FREQ 1000000
|
||||
#define APBT_MMAP_SIZE 1024
|
||||
|
||||
extern void apbt_time_init(void);
|
||||
extern void apbt_setup_secondary_clock(void);
|
||||
|
||||
extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
|
||||
extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
|
||||
extern int sfi_mtimer_num;
|
||||
|
||||
#else /* CONFIG_APB_TIMER */
|
||||
|
||||
static inline void apbt_time_init(void) { }
|
||||
|
||||
#endif
|
||||
#endif /* ASM_X86_APBT_H */
|
||||
@@ -108,9 +108,6 @@ enum fixed_addresses {
|
||||
#ifdef CONFIG_PARAVIRT_XXL
|
||||
FIX_PARAVIRT_BOOTMAP,
|
||||
#endif
|
||||
#ifdef CONFIG_X86_INTEL_MID
|
||||
FIX_LNW_VRTC,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ACPI_APEI_GHES
|
||||
/* Used for GHES mapping from assorted contexts */
|
||||
|
||||
@@ -1,15 +1,13 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* intel-mid.h: Intel MID specific setup code
|
||||
* Intel MID specific setup code
|
||||
*
|
||||
* (C) Copyright 2009 Intel Corporation
|
||||
* (C) Copyright 2009, 2021 Intel Corporation
|
||||
*/
|
||||
#ifndef _ASM_X86_INTEL_MID_H
|
||||
#define _ASM_X86_INTEL_MID_H
|
||||
|
||||
#include <linux/sfi.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
extern int intel_mid_pci_init(void);
|
||||
extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
|
||||
@@ -22,93 +20,18 @@ extern void intel_mid_pwr_power_off(void);
|
||||
|
||||
extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
|
||||
|
||||
extern int get_gpio_by_name(const char *name);
|
||||
extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
|
||||
extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
|
||||
extern int sfi_mrtc_num;
|
||||
extern struct sfi_rtc_table_entry sfi_mrtc_array[];
|
||||
|
||||
/*
|
||||
* Here defines the array of devices platform data that IAFW would export
|
||||
* through SFI "DEVS" table, we use name and type to match the device and
|
||||
* its platform data.
|
||||
*/
|
||||
struct devs_id {
|
||||
char name[SFI_NAME_LEN + 1];
|
||||
u8 type;
|
||||
u8 delay;
|
||||
u8 msic;
|
||||
void *(*get_platform_data)(void *info);
|
||||
};
|
||||
|
||||
#define sfi_device(i) \
|
||||
static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
|
||||
__section(".x86_intel_mid_dev.init") = &i
|
||||
|
||||
/**
|
||||
* struct mid_sd_board_info - template for SD device creation
|
||||
* @name: identifies the driver
|
||||
* @bus_num: board-specific identifier for a given SD controller
|
||||
* @max_clk: the maximum frequency device supports
|
||||
* @platform_data: the particular data stored there is driver-specific
|
||||
*/
|
||||
struct mid_sd_board_info {
|
||||
char name[SFI_NAME_LEN];
|
||||
int bus_num;
|
||||
unsigned short addr;
|
||||
u32 max_clk;
|
||||
void *platform_data;
|
||||
};
|
||||
|
||||
/*
|
||||
* Medfield is the follow-up of Moorestown, it combines two chip solution into
|
||||
* one. Other than that it also added always-on and constant tsc and lapic
|
||||
* timers. Medfield is the platform name, and the chip name is called Penwell
|
||||
* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
|
||||
* identified via MSRs.
|
||||
*/
|
||||
enum intel_mid_cpu_type {
|
||||
/* 1 was Moorestown */
|
||||
INTEL_MID_CPU_CHIP_PENWELL = 2,
|
||||
INTEL_MID_CPU_CHIP_CLOVERVIEW,
|
||||
INTEL_MID_CPU_CHIP_TANGIER,
|
||||
};
|
||||
|
||||
extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
|
||||
|
||||
#ifdef CONFIG_X86_INTEL_MID
|
||||
|
||||
static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
|
||||
{
|
||||
return __intel_mid_cpu_chip;
|
||||
}
|
||||
|
||||
static inline bool intel_mid_has_msic(void)
|
||||
{
|
||||
return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
|
||||
}
|
||||
|
||||
extern void intel_scu_devices_create(void);
|
||||
extern void intel_scu_devices_destroy(void);
|
||||
|
||||
#else /* !CONFIG_X86_INTEL_MID */
|
||||
|
||||
#define intel_mid_identify_cpu() 0
|
||||
#define intel_mid_has_msic() 0
|
||||
|
||||
static inline void intel_scu_devices_create(void) { }
|
||||
static inline void intel_scu_devices_destroy(void) { }
|
||||
|
||||
#endif /* !CONFIG_X86_INTEL_MID */
|
||||
|
||||
enum intel_mid_timer_options {
|
||||
INTEL_MID_TIMER_DEFAULT,
|
||||
INTEL_MID_TIMER_APBT_ONLY,
|
||||
INTEL_MID_TIMER_LAPIC_APBT,
|
||||
};
|
||||
|
||||
extern enum intel_mid_timer_options intel_mid_timer_options;
|
||||
|
||||
/* Bus Select SoC Fuse value */
|
||||
#define BSEL_SOC_FUSE_MASK 0x7
|
||||
/* FSB 133MHz */
|
||||
@@ -118,16 +41,4 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
|
||||
/* FSB 83MHz */
|
||||
#define BSEL_SOC_FUSE_111 0x7
|
||||
|
||||
#define SFI_MTMR_MAX_NUM 8
|
||||
#define SFI_MRTC_MAX 8
|
||||
|
||||
/* VRTC timer */
|
||||
#define MRST_VRTC_MAP_SZ 1024
|
||||
/* #define MRST_VRTC_PGOFFSET 0xc00 */
|
||||
|
||||
extern void intel_mid_rtc_init(void);
|
||||
|
||||
/* The offset for the mapping of global gpio pin to irq */
|
||||
#define INTEL_MID_IRQ_OFFSET 0x100
|
||||
|
||||
#endif /* _ASM_X86_INTEL_MID_H */
|
||||
|
||||
@@ -1,10 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _INTEL_MID_VRTC_H
|
||||
#define _INTEL_MID_VRTC_H
|
||||
|
||||
extern unsigned char vrtc_cmos_read(unsigned char reg);
|
||||
extern void vrtc_cmos_write(unsigned char val, unsigned char reg);
|
||||
extern void vrtc_get_time(struct timespec64 *now);
|
||||
extern int vrtc_set_mmss(const struct timespec64 *now);
|
||||
|
||||
#endif
|
||||
@@ -65,6 +65,4 @@ static inline int intel_scu_ipc_dev_command(struct intel_scu_ipc_dev *scu, int c
|
||||
inlen, out, outlen);
|
||||
}
|
||||
|
||||
#include <asm/intel_scu_ipc_legacy.h>
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,91 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _ASM_X86_INTEL_SCU_IPC_LEGACY_H_
|
||||
#define _ASM_X86_INTEL_SCU_IPC_LEGACY_H_
|
||||
|
||||
#include <linux/notifier.h>
|
||||
|
||||
#define IPCMSG_INDIRECT_READ 0x02
|
||||
#define IPCMSG_INDIRECT_WRITE 0x05
|
||||
|
||||
#define IPCMSG_COLD_OFF 0x80 /* Only for Tangier */
|
||||
|
||||
#define IPCMSG_WARM_RESET 0xF0
|
||||
#define IPCMSG_COLD_RESET 0xF1
|
||||
#define IPCMSG_SOFT_RESET 0xF2
|
||||
#define IPCMSG_COLD_BOOT 0xF3
|
||||
|
||||
#define IPCMSG_VRTC 0xFA /* Set vRTC device */
|
||||
/* Command id associated with message IPCMSG_VRTC */
|
||||
#define IPC_CMD_VRTC_SETTIME 1 /* Set time */
|
||||
#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */
|
||||
|
||||
/* Don't call these in new code - they will be removed eventually */
|
||||
|
||||
/* Read single register */
|
||||
static inline int intel_scu_ipc_ioread8(u16 addr, u8 *data)
|
||||
{
|
||||
return intel_scu_ipc_dev_ioread8(NULL, addr, data);
|
||||
}
|
||||
|
||||
/* Read a vector */
|
||||
static inline int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
|
||||
{
|
||||
return intel_scu_ipc_dev_readv(NULL, addr, data, len);
|
||||
}
|
||||
|
||||
/* Write single register */
|
||||
static inline int intel_scu_ipc_iowrite8(u16 addr, u8 data)
|
||||
{
|
||||
return intel_scu_ipc_dev_iowrite8(NULL, addr, data);
|
||||
}
|
||||
|
||||
/* Write a vector */
|
||||
static inline int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
|
||||
{
|
||||
return intel_scu_ipc_dev_writev(NULL, addr, data, len);
|
||||
}
|
||||
|
||||
/* Update single register based on the mask */
|
||||
static inline int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask)
|
||||
{
|
||||
return intel_scu_ipc_dev_update(NULL, addr, data, mask);
|
||||
}
|
||||
|
||||
/* Issue commands to the SCU with or without data */
|
||||
static inline int intel_scu_ipc_simple_command(int cmd, int sub)
|
||||
{
|
||||
return intel_scu_ipc_dev_simple_command(NULL, cmd, sub);
|
||||
}
|
||||
|
||||
static inline int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
|
||||
u32 *out, int outlen)
|
||||
{
|
||||
/* New API takes both inlen and outlen as bytes so convert here */
|
||||
size_t inbytes = inlen * sizeof(u32);
|
||||
size_t outbytes = outlen * sizeof(u32);
|
||||
|
||||
return intel_scu_ipc_dev_command_with_size(NULL, cmd, sub, in, inbytes,
|
||||
inlen, out, outbytes);
|
||||
}
|
||||
|
||||
extern struct blocking_notifier_head intel_scu_notifier;
|
||||
|
||||
static inline void intel_scu_notifier_add(struct notifier_block *nb)
|
||||
{
|
||||
blocking_notifier_chain_register(&intel_scu_notifier, nb);
|
||||
}
|
||||
|
||||
static inline void intel_scu_notifier_remove(struct notifier_block *nb)
|
||||
{
|
||||
blocking_notifier_chain_unregister(&intel_scu_notifier, nb);
|
||||
}
|
||||
|
||||
static inline int intel_scu_notifier_post(unsigned long v, void *p)
|
||||
{
|
||||
return blocking_notifier_call_chain(&intel_scu_notifier, v, p);
|
||||
}
|
||||
|
||||
#define SCU_AVAILABLE 1
|
||||
#define SCU_DOWN 2
|
||||
|
||||
#endif
|
||||
@@ -10,8 +10,6 @@
|
||||
#ifndef _PLATFORM_SST_AUDIO_H_
|
||||
#define _PLATFORM_SST_AUDIO_H_
|
||||
|
||||
#include <linux/sfi.h>
|
||||
|
||||
#define MAX_NUM_STREAMS_MRFLD 25
|
||||
#define MAX_NUM_STREAMS MAX_NUM_STREAMS_MRFLD
|
||||
|
||||
|
||||
@@ -116,7 +116,6 @@ obj-$(CONFIG_VM86) += vm86_32.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
|
||||
obj-$(CONFIG_HPET_TIMER) += hpet.o
|
||||
obj-$(CONFIG_APB_TIMER) += apb_timer.o
|
||||
|
||||
obj-$(CONFIG_AMD_NB) += amd_nb.o
|
||||
obj-$(CONFIG_DEBUG_NMI_SELFTEST) += nmi_selftest.o
|
||||
|
||||
@@ -1,347 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* apb_timer.c: Driver for Langwell APB timers
|
||||
*
|
||||
* (C) Copyright 2009 Intel Corporation
|
||||
* Author: Jacob Pan (jacob.jun.pan@intel.com)
|
||||
*
|
||||
* Note:
|
||||
* Langwell is the south complex of Intel Moorestown MID platform. There are
|
||||
* eight external timers in total that can be used by the operating system.
|
||||
* The timer information, such as frequency and addresses, is provided to the
|
||||
* OS via SFI tables.
|
||||
* Timer interrupts are routed via FW/HW emulated IOAPIC independently via
|
||||
* individual redirection table entries (RTE).
|
||||
* Unlike HPET, there is no master counter, therefore one of the timers are
|
||||
* used as clocksource. The overall allocation looks like:
|
||||
* - timer 0 - NR_CPUs for per cpu timer
|
||||
* - one timer for clocksource
|
||||
* - one timer for watchdog driver.
|
||||
* It is also worth notice that APB timer does not support true one-shot mode,
|
||||
* free-running mode will be used here to emulate one-shot mode.
|
||||
* APB timer can also be used as broadcast timer along with per cpu local APIC
|
||||
* timer, but by default APB timer has higher rating than local APIC timers.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dw_apb_timer.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/sfi.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/fixmap.h>
|
||||
#include <asm/apb_timer.h>
|
||||
#include <asm/intel-mid.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#define APBT_CLOCKEVENT_RATING 110
|
||||
#define APBT_CLOCKSOURCE_RATING 250
|
||||
|
||||
#define APBT_CLOCKEVENT0_NUM (0)
|
||||
#define APBT_CLOCKSOURCE_NUM (2)
|
||||
|
||||
static phys_addr_t apbt_address;
|
||||
static int apb_timer_block_enabled;
|
||||
static void __iomem *apbt_virt_address;
|
||||
|
||||
/*
|
||||
* Common DW APB timer info
|
||||
*/
|
||||
static unsigned long apbt_freq;
|
||||
|
||||
struct apbt_dev {
|
||||
struct dw_apb_clock_event_device *timer;
|
||||
unsigned int num;
|
||||
int cpu;
|
||||
unsigned int irq;
|
||||
char name[10];
|
||||
};
|
||||
|
||||
static struct dw_apb_clocksource *clocksource_apbt;
|
||||
|
||||
static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
|
||||
{
|
||||
return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
|
||||
}
|
||||
|
||||
static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static unsigned int apbt_num_timers_used;
|
||||
#endif
|
||||
|
||||
static inline void apbt_set_mapping(void)
|
||||
{
|
||||
struct sfi_timer_table_entry *mtmr;
|
||||
int phy_cs_timer_id = 0;
|
||||
|
||||
if (apbt_virt_address) {
|
||||
pr_debug("APBT base already mapped\n");
|
||||
return;
|
||||
}
|
||||
mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
|
||||
if (mtmr == NULL) {
|
||||
printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
|
||||
APBT_CLOCKEVENT0_NUM);
|
||||
return;
|
||||
}
|
||||
apbt_address = (phys_addr_t)mtmr->phys_addr;
|
||||
if (!apbt_address) {
|
||||
printk(KERN_WARNING "No timer base from SFI, use default\n");
|
||||
apbt_address = APBT_DEFAULT_BASE;
|
||||
}
|
||||
apbt_virt_address = ioremap(apbt_address, APBT_MMAP_SIZE);
|
||||
if (!apbt_virt_address) {
|
||||
pr_debug("Failed mapping APBT phy address at %lu\n",\
|
||||
(unsigned long)apbt_address);
|
||||
goto panic_noapbt;
|
||||
}
|
||||
apbt_freq = mtmr->freq_hz;
|
||||
sfi_free_mtmr(mtmr);
|
||||
|
||||
/* Now figure out the physical timer id for clocksource device */
|
||||
mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
|
||||
if (mtmr == NULL)
|
||||
goto panic_noapbt;
|
||||
|
||||
/* Now figure out the physical timer id */
|
||||
pr_debug("Use timer %d for clocksource\n",
|
||||
(int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
|
||||
phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
|
||||
APBTMRS_REG_SIZE;
|
||||
|
||||
clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
|
||||
"apbt0", apbt_virt_address + phy_cs_timer_id *
|
||||
APBTMRS_REG_SIZE, apbt_freq);
|
||||
return;
|
||||
|
||||
panic_noapbt:
|
||||
panic("Failed to setup APB system timer\n");
|
||||
|
||||
}
|
||||
|
||||
static inline void apbt_clear_mapping(void)
|
||||
{
|
||||
iounmap(apbt_virt_address);
|
||||
apbt_virt_address = NULL;
|
||||
}
|
||||
|
||||
static int __init apbt_clockevent_register(void)
|
||||
{
|
||||
struct sfi_timer_table_entry *mtmr;
|
||||
struct apbt_dev *adev = this_cpu_ptr(&cpu_apbt_dev);
|
||||
|
||||
mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
|
||||
if (mtmr == NULL) {
|
||||
printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
|
||||
APBT_CLOCKEVENT0_NUM);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
adev->num = smp_processor_id();
|
||||
adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
|
||||
intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?
|
||||
APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
|
||||
adev_virt_addr(adev), 0, apbt_freq);
|
||||
/* Firmware does EOI handling for us. */
|
||||
adev->timer->eoi = NULL;
|
||||
|
||||
if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
|
||||
global_clock_event = &adev->timer->ced;
|
||||
printk(KERN_DEBUG "%s clockevent registered as global\n",
|
||||
global_clock_event->name);
|
||||
}
|
||||
|
||||
dw_apb_clockevent_register(adev->timer);
|
||||
|
||||
sfi_free_mtmr(mtmr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
static void apbt_setup_irq(struct apbt_dev *adev)
|
||||
{
|
||||
irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
|
||||
irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
|
||||
}
|
||||
|
||||
/* Should be called with per cpu */
|
||||
void apbt_setup_secondary_clock(void)
|
||||
{
|
||||
struct apbt_dev *adev;
|
||||
int cpu;
|
||||
|
||||
/* Don't register boot CPU clockevent */
|
||||
cpu = smp_processor_id();
|
||||
if (!cpu)
|
||||
return;
|
||||
|
||||
adev = this_cpu_ptr(&cpu_apbt_dev);
|
||||
if (!adev->timer) {
|
||||
adev->timer = dw_apb_clockevent_init(cpu, adev->name,
|
||||
APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
|
||||
adev->irq, apbt_freq);
|
||||
adev->timer->eoi = NULL;
|
||||
} else {
|
||||
dw_apb_clockevent_resume(adev->timer);
|
||||
}
|
||||
|
||||
printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
|
||||
cpu, adev->name, adev->cpu);
|
||||
|
||||
apbt_setup_irq(adev);
|
||||
dw_apb_clockevent_register(adev->timer);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* this notify handler process CPU hotplug events. in case of S0i3, nonboot
|
||||
* cpus are disabled/enabled frequently, for performance reasons, we keep the
|
||||
* per cpu timer irq registered so that we do need to do free_irq/request_irq.
|
||||
*
|
||||
* TODO: it might be more reliable to directly disable percpu clockevent device
|
||||
* without the notifier chain. currently, cpu 0 may get interrupts from other
|
||||
* cpu timers during the offline process due to the ordering of notification.
|
||||
* the extra interrupt is harmless.
|
||||
*/
|
||||
static int apbt_cpu_dead(unsigned int cpu)
|
||||
{
|
||||
struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
|
||||
|
||||
dw_apb_clockevent_pause(adev->timer);
|
||||
if (system_state == SYSTEM_RUNNING) {
|
||||
pr_debug("skipping APBT CPU %u offline\n", cpu);
|
||||
} else {
|
||||
pr_debug("APBT clockevent for cpu %u offline\n", cpu);
|
||||
dw_apb_clockevent_stop(adev->timer);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int apbt_late_init(void)
|
||||
{
|
||||
if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||
|
||||
!apb_timer_block_enabled)
|
||||
return 0;
|
||||
return cpuhp_setup_state(CPUHP_X86_APB_DEAD, "x86/apb:dead", NULL,
|
||||
apbt_cpu_dead);
|
||||
}
|
||||
fs_initcall(apbt_late_init);
|
||||
#else
|
||||
|
||||
void apbt_setup_secondary_clock(void) {}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
static int apbt_clocksource_register(void)
|
||||
{
|
||||
u64 start, now;
|
||||
u64 t1;
|
||||
|
||||
/* Start the counter, use timer 2 as source, timer 0/1 for event */
|
||||
dw_apb_clocksource_start(clocksource_apbt);
|
||||
|
||||
/* Verify whether apbt counter works */
|
||||
t1 = dw_apb_clocksource_read(clocksource_apbt);
|
||||
start = rdtsc();
|
||||
|
||||
/*
|
||||
* We don't know the TSC frequency yet, but waiting for
|
||||
* 200000 TSC cycles is safe:
|
||||
* 4 GHz == 50us
|
||||
* 1 GHz == 200us
|
||||
*/
|
||||
do {
|
||||
rep_nop();
|
||||
now = rdtsc();
|
||||
} while ((now - start) < 200000UL);
|
||||
|
||||
/* APBT is the only always on clocksource, it has to work! */
|
||||
if (t1 == dw_apb_clocksource_read(clocksource_apbt))
|
||||
panic("APBT counter not counting. APBT disabled\n");
|
||||
|
||||
dw_apb_clocksource_register(clocksource_apbt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Early setup the APBT timer, only use timer 0 for booting then switch to
|
||||
* per CPU timer if possible.
|
||||
* returns 1 if per cpu apbt is setup
|
||||
* returns 0 if no per cpu apbt is chosen
|
||||
* panic if set up failed, this is the only platform timer on Moorestown.
|
||||
*/
|
||||
void __init apbt_time_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
int i;
|
||||
struct sfi_timer_table_entry *p_mtmr;
|
||||
struct apbt_dev *adev;
|
||||
#endif
|
||||
|
||||
if (apb_timer_block_enabled)
|
||||
return;
|
||||
apbt_set_mapping();
|
||||
if (!apbt_virt_address)
|
||||
goto out_noapbt;
|
||||
/*
|
||||
* Read the frequency and check for a sane value, for ESL model
|
||||
* we extend the possible clock range to allow time scaling.
|
||||
*/
|
||||
|
||||
if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
|
||||
pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
|
||||
goto out_noapbt;
|
||||
}
|
||||
if (apbt_clocksource_register()) {
|
||||
pr_debug("APBT has failed to register clocksource\n");
|
||||
goto out_noapbt;
|
||||
}
|
||||
if (!apbt_clockevent_register())
|
||||
apb_timer_block_enabled = 1;
|
||||
else {
|
||||
pr_debug("APBT has failed to register clockevent\n");
|
||||
goto out_noapbt;
|
||||
}
|
||||
#ifdef CONFIG_SMP
|
||||
/* kernel cmdline disable apb timer, so we will use lapic timers */
|
||||
if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
|
||||
printk(KERN_INFO "apbt: disabled per cpu timer\n");
|
||||
return;
|
||||
}
|
||||
pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
|
||||
if (num_possible_cpus() <= sfi_mtimer_num)
|
||||
apbt_num_timers_used = num_possible_cpus();
|
||||
else
|
||||
apbt_num_timers_used = 1;
|
||||
pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
|
||||
|
||||
/* here we set up per CPU timer data structure */
|
||||
for (i = 0; i < apbt_num_timers_used; i++) {
|
||||
adev = &per_cpu(cpu_apbt_dev, i);
|
||||
adev->num = i;
|
||||
adev->cpu = i;
|
||||
p_mtmr = sfi_get_mtmr(i);
|
||||
if (p_mtmr)
|
||||
adev->irq = p_mtmr->irq;
|
||||
else
|
||||
printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
|
||||
snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
|
||||
}
|
||||
#endif
|
||||
|
||||
return;
|
||||
|
||||
out_noapbt:
|
||||
apbt_clear_mapping();
|
||||
apb_timer_block_enabled = 0;
|
||||
panic("failed to enable APB timer\n");
|
||||
}
|
||||
@@ -198,7 +198,7 @@ static int __init parse_noapic(char *str)
|
||||
}
|
||||
early_param("noapic", parse_noapic);
|
||||
|
||||
/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
|
||||
/* Will be called in mpparse/ACPI codes for saving IRQ info */
|
||||
void mp_save_irq(struct mpc_intsrc *m)
|
||||
{
|
||||
int i;
|
||||
@@ -2863,7 +2863,7 @@ int mp_register_ioapic(int id, u32 address, u32 gsi_base,
|
||||
|
||||
/*
|
||||
* If mp_register_ioapic() is called during early boot stage when
|
||||
* walking ACPI/SFI/DT tables, it's too early to create irqdomain,
|
||||
* walking ACPI/DT tables, it's too early to create irqdomain,
|
||||
* we are still using bootmem allocator. So delay it to setup_IO_APIC().
|
||||
*/
|
||||
if (hotplug) {
|
||||
|
||||
@@ -16,7 +16,6 @@
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/sfi.h>
|
||||
#include <linux/hugetlb.h>
|
||||
#include <linux/tboot.h>
|
||||
#include <linux/usb/xhci-dbgp.h>
|
||||
@@ -1185,7 +1184,6 @@ void __init setup_arch(char **cmdline_p)
|
||||
* Read APIC and some other early information from ACPI tables.
|
||||
*/
|
||||
acpi_boot_init();
|
||||
sfi_init();
|
||||
x86_dtb_init();
|
||||
|
||||
/*
|
||||
|
||||
@@ -28,10 +28,12 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/segment.h>
|
||||
#include <asm/pci_x86.h>
|
||||
#include <asm/hw_irq.h>
|
||||
#include <asm/io_apic.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/intel-mid.h>
|
||||
#include <asm/acpi.h>
|
||||
|
||||
@@ -140,6 +142,7 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
|
||||
* type1_access_ok - check whether to use type 1
|
||||
* @bus: bus number
|
||||
* @devfn: device & function in question
|
||||
* @reg: configuration register offset
|
||||
*
|
||||
* If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
|
||||
* all, the we can go ahead with any reads & writes. If it's on a Lincroft,
|
||||
@@ -212,10 +215,17 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
||||
where, size, value);
|
||||
}
|
||||
|
||||
static const struct x86_cpu_id intel_mid_cpu_ids[] = {
|
||||
X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
static int intel_mid_pci_irq_enable(struct pci_dev *dev)
|
||||
{
|
||||
const struct x86_cpu_id *id;
|
||||
struct irq_alloc_info info;
|
||||
bool polarity_low;
|
||||
u16 model = 0;
|
||||
int ret;
|
||||
u8 gsi;
|
||||
|
||||
@@ -228,8 +238,12 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (intel_mid_identify_cpu()) {
|
||||
case INTEL_MID_CPU_CHIP_TANGIER:
|
||||
id = x86_match_cpu(intel_mid_cpu_ids);
|
||||
if (id)
|
||||
model = id->model;
|
||||
|
||||
switch (model) {
|
||||
case INTEL_FAM6_ATOM_SILVERMONT_MID:
|
||||
polarity_low = false;
|
||||
|
||||
/* Special treatment for IRQ0 */
|
||||
|
||||
@@ -11,9 +11,9 @@
|
||||
* themselves.
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sfi_acpi.h>
|
||||
#include <linux/bitmap.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/slab.h>
|
||||
@@ -665,7 +665,7 @@ void __init pci_mmcfg_early_init(void)
|
||||
if (pci_mmcfg_check_hostbridge())
|
||||
known_bridge = 1;
|
||||
else
|
||||
acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
|
||||
acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
|
||||
__pci_mmcfg_init(1);
|
||||
|
||||
set_apei_filter();
|
||||
@@ -683,7 +683,7 @@ void __init pci_mmcfg_late_init(void)
|
||||
|
||||
/* MMCONFIG hasn't been enabled yet, try again */
|
||||
if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
|
||||
acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
|
||||
acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
|
||||
__pci_mmcfg_init(0);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -10,6 +10,5 @@ obj-y += intel-mid/
|
||||
obj-y += intel-quark/
|
||||
obj-y += olpc/
|
||||
obj-y += scx200/
|
||||
obj-y += sfi/
|
||||
obj-y += ts5500/
|
||||
obj-y += uv/
|
||||
|
||||
@@ -1,7 +1,2 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o pwr.o
|
||||
|
||||
# SFI specific code
|
||||
ifdef CONFIG_X86_INTEL_MID
|
||||
obj-$(CONFIG_SFI) += sfi.o device_libs/
|
||||
endif
|
||||
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o pwr.o
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user