mirror of
https://github.com/t2linux/kernel.git
synced 2026-04-30 13:48:59 -07:00
Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson: "This is a branch with updates for Marvell's mvebu/kirkwood platforms. They came in late-ish, and were heavily interdependent such that it didn't make sense to split them up across the cross-platform topic branches. So here they are (for the second release in a row) in a branch on their own." * tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits) arm: l2x0: add aurora related properties to OF binding arm: mvebu: add Aurora L2 Cache Controller to the DT arm: mvebu: add L2 cache support dma: mv_xor: fix error handling path dma: mv_xor: fix error checking of irq_of_parse_and_map() dma: mv_xor: use request_irq() instead of devm_request_irq() dma: mv_xor: clear the window override control registers arm: mvebu: fix address decoding armada_cfg_base() function ARM: mvebu: update defconfig with I2C and RTC support ARM: mvebu: Add SATA support for OpenBlocks AX3-4 ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4 ARM: mvebu: Add support for I2C on OpenBlocks AX3-4 ARM: mvebu: Add support for I2C controllers in Armada 370/XP arm: mvebu: Add hardware I/O Coherency support arm: plat-orion: Add coherency attribute when setup mbus target arm: dma mapping: Export a dma ops function arm_dma_set_mask arm: mvebu: Add SMP support for Armada XP arm: mm: Add support for PJ4B cpu and init routines arm: mvebu: Add IPI support via doorbells arm: mvebu: Add initial support for power managmement service unit ...
This commit is contained in:
Linus Torvalds
@@ -6,9 +6,15 @@ Required properties:
|
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
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The cell is the IRQ number
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- reg: Should contain PMIC registers location and length. First pair
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for the main interrupt registers, second pair for the per-CPU
|
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interrupt registers
|
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interrupt registers. For this last pair, to be compliant with SMP
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support, the "virtual" must be use (For the record, these registers
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automatically map to the interrupt controller registers of the
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current CPU)
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|
||||
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||||
|
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Example:
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@@ -18,6 +24,6 @@ Example:
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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reg = <0xd0020000 0x1000>,
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<0xd0021000 0x1000>;
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reg = <0xd0020a00 0x1d0>,
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<0xd0021070 0x58>;
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};
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@@ -0,0 +1,20 @@
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Power Management Service Unit(PMSU)
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-----------------------------------
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Available on Marvell SOCs: Armada 370 and Armada XP
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Required properties:
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- compatible: "marvell,armada-370-xp-pmsu"
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- reg: Should contain PMSU registers location and length. First pair
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for the per-CPU SW Reset Control registers, second pair for the
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Power Management Service Unit.
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Example:
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armada-370-xp-pmsu@d0022000 {
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compatible = "marvell,armada-370-xp-pmsu";
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reg = <0xd0022100 0x430>,
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<0xd0020800 0x20>;
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};
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@@ -5,6 +5,7 @@ Required properties:
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- compatible: Should be "marvell,armada-370-xp-timer"
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- interrupts: Should contain the list of Global Timer interrupts
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- reg: Should contain the base address of the Global Timer registers
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- clocks: clock driving the timer hardware
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Optional properties:
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- marvell,timer-25Mhz: Tells whether the Global timer supports the 25
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@@ -0,0 +1,21 @@
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Coherency fabric
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----------------
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Available on Marvell SOCs: Armada 370 and Armada XP
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Required properties:
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- compatible: "marvell,coherency-fabric"
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- reg: Should contain coherency fabric registers location and
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length. First pair for the coherency fabric registers, second pair
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for the per-CPU fabric registers registers.
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Example:
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coherency-fabric@d0020200 {
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compatible = "marvell,coherency-fabric";
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reg = <0xd0020200 0xb0>,
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<0xd0021810 0x1c>;
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};
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@@ -10,6 +10,12 @@ Required properties:
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"arm,pl310-cache"
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"arm,l220-cache"
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"arm,l210-cache"
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"marvell,aurora-system-cache": Marvell Controller designed to be
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compatible with the ARM one, with system cache mode (meaning
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maintenance operations on L1 are broadcasted to the L2 and L2
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performs the same operation).
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"marvell,"aurora-outer-cache: Marvell Controller designed to be
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compatible with the ARM one with outer cache mode.
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- cache-unified : Specifies the cache is a unified cache.
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- cache-level : Should be set to 2 for a level 2 cache.
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- reg : Physical base address and size of cache controller's memory mapped
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@@ -29,6 +35,9 @@ Optional properties:
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filter. Addresses in the filter window are directed to the M1 port. Other
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addresses will go to the M0 port.
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- interrupts : 1 combined interrupt.
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- cache-id-part: cache id part number to be used if it is not present
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on hardware
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- wt-override: If present then L2 is forced to Write through mode
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Example:
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@@ -0,0 +1,47 @@
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* Core Clock bindings for Marvell MVEBU SoCs
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Marvell MVEBU SoCs usually allow to determine core clock frequencies by
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reading the Sample-At-Reset (SAR) register. The core clock consumer should
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specify the desired clock by having the clock ID in its "clocks" phandle cell.
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The following is a list of provided IDs and clock names on Armada 370/XP:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU clock)
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2 = nbclk (L2 Cache clock)
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3 = hclk (DRAM control clock)
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4 = dramclk (DDR clock)
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The following is a list of provided IDs and clock names on Kirkwood and Dove:
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0 = tclk (Internal Bus clock)
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1 = cpuclk (CPU0 clock)
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2 = l2clk (L2 Cache clock derived from CPU0 clock)
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3 = ddrclk (DDR controller clock derived from CPU0 clock)
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
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"marvell,dove-core-clock" - for Dove SoC core clocks
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"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
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"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
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- reg : shall be the register address of the Sample-At-Reset (SAR) register
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- #clock-cells : from common clock binding; shall be set to 1
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Optional properties:
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- clock-output-names : from common clock binding; allows overwrite default clock
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output names ("tclk", "cpuclk", "l2clk", "ddrclk")
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Example:
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core_clk: core-clocks@d0214 {
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compatible = "marvell,dove-core-clock";
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reg = <0xd0214 0x4>;
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#clock-cells = <1>;
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};
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spi0: spi@10600 {
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compatible = "marvell,orion-spi";
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/* ... */
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/* get tclk from core clock provider */
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clocks = <&core_clk 0>;
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};
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@@ -0,0 +1,21 @@
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Device Tree Clock bindings for cpu clock of Marvell EBU platforms
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
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- reg : Address and length of the clock complex register set
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- #clock-cells : should be set to 1.
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- clocks : shall be the input parent clock phandle for the clock.
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cpuclk: clock-complex@d0018700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0xd0018700 0xA0>;
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clocks = <&coreclk 1>;
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}
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cpu@0 {
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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};
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@@ -0,0 +1,119 @@
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* Gated Clock bindings for Marvell Orion SoCs
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Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save
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some power. The clock consumer should specify the desired clock by having
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the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
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the corresponding clock gating control bit in HW to ease manual clock lookup
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in datasheet.
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The following is a list of provided IDs for Armada 370:
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ID Clock Peripheral
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-----------------------------------
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||||
0 Audio AC97 Cntrl
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1 pex0_en PCIe 0 Clock out
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2 pex1_en PCIe 1 Clock out
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3 ge1 Gigabit Ethernet 1
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4 ge0 Gigabit Ethernet 0
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5 pex0 PCIe Cntrl 0
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9 pex1 PCIe Cntrl 1
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15 sata0 SATA Host 0
|
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17 sdio SDHCI Host
|
||||
25 tdm Time Division Mplx
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28 ddr DDR Cntrl
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30 sata1 SATA Host 0
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||||
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The following is a list of provided IDs for Armada XP:
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ID Clock Peripheral
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||||
-----------------------------------
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0 audio Audio Cntrl
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||||
1 ge3 Gigabit Ethernet 3
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||||
2 ge2 Gigabit Ethernet 2
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||||
3 ge1 Gigabit Ethernet 1
|
||||
4 ge0 Gigabit Ethernet 0
|
||||
5 pex0 PCIe Cntrl 0
|
||||
6 pex1 PCIe Cntrl 1
|
||||
7 pex2 PCIe Cntrl 2
|
||||
8 pex3 PCIe Cntrl 3
|
||||
13 bp
|
||||
14 sata0lnk
|
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15 sata0 SATA Host 0
|
||||
16 lcd LCD Cntrl
|
||||
17 sdio SDHCI Host
|
||||
18 usb0 USB Host 0
|
||||
19 usb1 USB Host 1
|
||||
20 usb2 USB Host 2
|
||||
22 xor0 XOR DMA 0
|
||||
23 crypto CESA engine
|
||||
25 tdm Time Division Mplx
|
||||
28 xor1 XOR DMA 1
|
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29 sata1lnk
|
||||
30 sata1 SATA Host 0
|
||||
|
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The following is a list of provided IDs for Dove:
|
||||
ID Clock Peripheral
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||||
-----------------------------------
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||||
0 usb0 USB Host 0
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1 usb1 USB Host 1
|
||||
2 ge Gigabit Ethernet
|
||||
3 sata SATA Host
|
||||
4 pex0 PCIe Cntrl 0
|
||||
5 pex1 PCIe Cntrl 1
|
||||
8 sdio0 SDHCI Host 0
|
||||
9 sdio1 SDHCI Host 1
|
||||
10 nand NAND Cntrl
|
||||
11 camera Camera Cntrl
|
||||
12 i2s0 I2S Cntrl 0
|
||||
13 i2s1 I2S Cntrl 1
|
||||
15 crypto CESA engine
|
||||
21 ac97 AC97 Cntrl
|
||||
22 pdma Peripheral DMA
|
||||
23 xor0 XOR DMA 0
|
||||
24 xor1 XOR DMA 1
|
||||
30 gephy Gigabit Ethernel PHY
|
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Note: gephy(30) is implemented as a parent clock of ge(2)
|
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|
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The following is a list of provided IDs for Kirkwood:
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ID Clock Peripheral
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||||
-----------------------------------
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0 ge0 Gigabit Ethernet 0
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2 pex0 PCIe Cntrl 0
|
||||
3 usb0 USB Host 0
|
||||
4 sdio SDIO Cntrl
|
||||
5 tsu Transp. Stream Unit
|
||||
6 dunit SDRAM Cntrl
|
||||
7 runit Runit
|
||||
8 xor0 XOR DMA 0
|
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9 audio I2S Cntrl 0
|
||||
14 sata0 SATA Host 0
|
||||
15 sata1 SATA Host 1
|
||||
16 xor1 XOR DMA 1
|
||||
17 crypto CESA engine
|
||||
18 pex1 PCIe Cntrl 1
|
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19 ge1 Gigabit Ethernet 0
|
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20 tdm Time Division Mplx
|
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|
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Required properties:
|
||||
- compatible : shall be one of the following:
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"marvell,dove-gating-clock" - for Dove SoC clock gating
|
||||
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
|
||||
- reg : shall be the register address of the Clock Gating Control register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
Optional properties:
|
||||
- clocks : default parent clock phandle (e.g. tclk)
|
||||
|
||||
Example:
|
||||
|
||||
gate_clk: clock-gating-control@d0038 {
|
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compatible = "marvell,dove-gating-clock";
|
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reg = <0xd0038 0x4>;
|
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/* default parent clock is tclk */
|
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clocks = <&core_clk 0>;
|
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#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sdio0: sdio@92000 {
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compatible = "marvell,dove-sdhci";
|
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/* get clk gate bit 8 (sdio0) */
|
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clocks = <&gate_clk 8>;
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
* Marvell XOR engines
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,orion-xor"
|
||||
- reg: Should contain registers location and length (two sets)
|
||||
the first set is the low registers, the second set the high
|
||||
registers for the XOR engine.
|
||||
- clocks: pointer to the reference clock
|
||||
|
||||
The DT node must also contains sub-nodes for each XOR channel that the
|
||||
XOR engine has. Those sub-nodes have the following required
|
||||
properties:
|
||||
- interrupts: interrupt of the XOR channel
|
||||
|
||||
And the following optional properties:
|
||||
- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
|
||||
- dmacap,memset to indicate that the XOR channel is capable of memset operations
|
||||
- dmacap,xor to indicate that the XOR channel is capable of xor operations
|
||||
|
||||
Example:
|
||||
|
||||
xor@d0060900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xd0060900 0x100
|
||||
0xd0060b00 0x100>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <51>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <52>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,23 @@
|
||||
* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "marvell,armada-370-neta".
|
||||
- reg: address and length of the register set for the device.
|
||||
- interrupts: interrupt for the device
|
||||
- phy: A phandle to a phy node defining the PHY address (as the reg
|
||||
property, a single integer).
|
||||
- phy-mode: The interface between the SoC and the PHY (a string that
|
||||
of_get_phy_mode() can understand)
|
||||
- clocks: a pointer to the reference clock for this device.
|
||||
|
||||
Example:
|
||||
|
||||
ethernet@d0070000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0xd0070000 0x2500>;
|
||||
interrupts = <8>;
|
||||
clocks = <&gate_clk 4>;
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
@@ -0,0 +1,35 @@
|
||||
* Marvell MDIO Ethernet Controller interface
|
||||
|
||||
The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x,
|
||||
MV78xx0, Armada 370 and Armada XP have an identical unit that provides
|
||||
an interface with the MDIO bus. This driver handles this MDIO
|
||||
interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,orion-mdio"
|
||||
- reg: address and length of the SMI register
|
||||
|
||||
The child nodes of the MDIO driver are the individual PHY devices
|
||||
connected to this MDIO bus. They must have a "reg" property given the
|
||||
PHY address on the MDIO bus.
|
||||
|
||||
Example at the SoC level:
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0xd0072004 0x4>;
|
||||
};
|
||||
|
||||
And at the board level:
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
}
|
||||
@@ -4871,6 +4871,12 @@ S: Maintained
|
||||
F: drivers/net/ethernet/marvell/mv643xx_eth.*
|
||||
F: include/linux/mv643xx.h
|
||||
|
||||
MARVELL MVNETA ETHERNET DRIVER
|
||||
M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/marvell/mvneta.*
|
||||
|
||||
MARVELL MWIFIEX WIRELESS DRIVER
|
||||
M: Bing Zhao <bzhao@marvell.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
|
||||
@@ -533,6 +533,7 @@ config ARCH_IXP4XX
|
||||
config ARCH_DOVE
|
||||
bool "Marvell Dove"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select COMMON_CLK_DOVE
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MIGHT_HAVE_PCI
|
||||
|
||||
@@ -77,7 +77,9 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
|
||||
dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
|
||||
msm8960-cdp.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
|
||||
armada-xp-db.dtb
|
||||
armada-370-mirabox.dtb \
|
||||
armada-xp-db.dtb \
|
||||
armada-xp-openblocks-ax3-4.dtb
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
|
||||
imx53-ard.dtb \
|
||||
imx53-evk.dtb \
|
||||
|
||||
@@ -34,9 +34,30 @@
|
||||
clock-frequency = <200000000>;
|
||||
status = "okay";
|
||||
};
|
||||
timer@d0020300 {
|
||||
clock-frequency = <600000000>;
|
||||
sata@d00a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@d0070000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@d0074000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Device Tree file for Globalscale Mirabox
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Globalscale Mirabox";
|
||||
compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
serial@d0012000 {
|
||||
clock-frequency = <200000000>;
|
||||
status = "okay";
|
||||
};
|
||||
timer@d0020300 {
|
||||
clock-frequency = <600000000>;
|
||||
status = "okay";
|
||||
};
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
ethernet@d0070000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@d0074000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -20,7 +20,7 @@
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 and XP SoC";
|
||||
compatible = "marvell,armada_370_xp";
|
||||
compatible = "marvell,armada-370-xp";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
@@ -36,6 +36,12 @@
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
coherency-fabric@d0020200 {
|
||||
compatible = "marvell,coherency-fabric";
|
||||
reg = <0xd0020200 0xb0>,
|
||||
<0xd0021810 0x1c>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -62,12 +68,67 @@
|
||||
compatible = "marvell,armada-370-xp-timer";
|
||||
reg = <0xd0020300 0x30>;
|
||||
interrupts = <37>, <38>, <39>, <40>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
addr-decoding@d0020000 {
|
||||
compatible = "marvell,armada-addr-decoding-controller";
|
||||
reg = <0xd0020000 0x258>;
|
||||
};
|
||||
|
||||
sata@d00a0000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0xd00a0000 0x2400>;
|
||||
interrupts = <55>;
|
||||
clocks = <&gateclk 15>, <&gateclk 30>;
|
||||
clock-names = "0", "1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0xd0072004 0x4>;
|
||||
};
|
||||
|
||||
ethernet@d0070000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0xd0070000 0x2500>;
|
||||
interrupts = <8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@d0074000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0xd0074000 0x2500>;
|
||||
interrupts = <10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@d0011000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0xd0011000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <31>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@d0011100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0xd0011100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <32>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -20,6 +20,12 @@
|
||||
/ {
|
||||
model = "Marvell Armada 370 family SoC";
|
||||
compatible = "marvell,armada370", "marvell,armada-370-xp";
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,aurora-outer-cache";
|
||||
reg = <0xd0008000 0x1000>;
|
||||
cache-id-part = <0x100>;
|
||||
wt-override;
|
||||
};
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
@@ -75,5 +81,56 @@
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@d0018230 {
|
||||
compatible = "marvell,armada-370-core-clock";
|
||||
reg = <0xd0018230 0x08>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@d0018220 {
|
||||
compatible = "marvell,armada-370-gating-clock";
|
||||
reg = <0xd0018220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
xor@d0060800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xd0060800 0x100
|
||||
0xd0060A00 0x100>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <51>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <52>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@d0060900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xd0060900 0x100
|
||||
0xd0060b00 0x100>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <94>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <95>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -46,5 +46,49 @@
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sata@d00a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <25>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <27>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@d0070000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@d0074000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@d0030000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
ethernet@d0034000 {
|
||||
status = "okay";
|
||||
phy = <&phy3>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -24,6 +24,18 @@
|
||||
gpio1 = &gpio1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
};
|
||||
}
|
||||
|
||||
soc {
|
||||
pinctrl {
|
||||
compatible = "marvell,mv78230-pinctrl";
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user