mirror of
https://github.com/t2linux/kernel.git
synced 2026-04-30 13:48:59 -07:00
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann: "As usual, the drivers/tee and drivers/reset subsystems get merged here, with the expected set of smaller updates and some new hardware support. The tee subsystem now supports device drivers to be attached to a tee, the first example here is a random number driver with its implementation in the secure world. Three new power domain drivers get added for specific chip families: - Broadcom BCM283x chips (used in Raspberry Pi) - Qualcomm Snapdragon phone chips - Xilinx ZynqMP FPGA SoCs One new driver is added to talk to the BPMP firmware on NVIDIA Tegra210 Existing drivers are extended for new SoC variants from NXP, NVIDIA, Amlogic and Qualcomm" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (113 commits) tee: optee: update optee_msg.h and optee_smc.h to dual license tee: add cancellation support to client interface dpaa2-eth: configure the cache stashing amount on a queue soc: fsl: dpio: configure cache stashing destination soc: fsl: dpio: enable frame data cache stashing per software portal soc: fsl: guts: make fsl_guts_get_svr() static hwrng: make symbol 'optee_rng_id_table' static tee: optee: Fix unsigned comparison with less than zero hwrng: Fix unsigned comparison with less than zero tee: fix possible error pointer ctx dereferencing hwrng: optee: Initialize some structs using memset instead of braces tee: optee: Initialize some structs using memset instead of braces soc: fsl: dpio: fix memory leak of a struct qbman on error exit path clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static soc: qcom: llcc-slice: Fix typos qcom: soc: llcc-slice: Consolidate some code qcom: soc: llcc-slice: Clear the global drv_data pointer on error drivers: soc: xilinx: Add ZynqMP power domain driver firmware: xilinx: Add APIs to control node status/power dt-bindings: power: Add ZynqMP power domain bindings ...
This commit is contained in:
Linus Torvalds
@@ -58,7 +58,11 @@ This binding for the SCU power domain providers uses the generic power
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domain binding[2].
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Required properties:
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- compatible: Should be "fsl,imx8qxp-scu-pd".
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- compatible: Should be one of:
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"fsl,imx8qm-scu-pd",
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"fsl,imx8qxp-scu-pd"
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followed by "fsl,scu-pd"
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- #power-domain-cells: Must be 1. Contains the Resource ID used by
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SCU commands.
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See detailed Resource ID list from:
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@@ -157,7 +161,7 @@ firmware {
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};
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pd: imx8qx-pd {
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compatible = "fsl,imx8qxp-scu-pd";
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compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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@@ -47,9 +47,9 @@ Optional properties:
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Timing property for child nodes. It is mandatory, not optional.
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- fsl,weim-cs-timing: The timing array, contains timing values for the
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child node. We can get the CS index from the child
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node's "reg" property. The number of registers depends
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on the selected chip.
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child node. We get the CS indexes from the address
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ranges in the child node's "reg" property.
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The number of registers depends on the selected chip:
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For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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registers: CSxU, CSxL.
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For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
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@@ -80,3 +80,29 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
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0x0000c000 0x1404a38e 0x00000000>;
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};
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};
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Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
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In this case, both chip select 0 and 1 will be configured with the same timing
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array values.
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weim: weim@21b8000 {
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compatible = "fsl,imx6q-weim";
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reg = <0x021b8000 0x4000>;
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clocks = <&clks 196>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x02000000
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1 0 0x0a000000 0x02000000
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2 0 0x0c000000 0x02000000
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3 0 0x0e000000 0x02000000>;
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fsl,weim-cs-gpr = <&gpr>;
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acme@0 {
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compatible = "acme,whatever";
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reg = <0 0 0x100>, <0 0x400000 0x800>,
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<1 0x400000 0x800>;
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fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
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0x00000000 0xa0000240 0x00000000>;
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};
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};
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@@ -0,0 +1,46 @@
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--------------------------------------------------------------------------
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= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
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--------------------------------------------------------------------------
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The nvmem_firmware node provides access to the hardware related data
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like soc revision, IDCODE... etc, By using the firmware interface.
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Required properties:
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- compatible: should be "xlnx,zynqmp-nvmem-fw"
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= Data cells =
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Are child nodes of silicon id, bindings of which as described in
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bindings/nvmem/nvmem.txt
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-------
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Example
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-------
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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method = "smc";
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nvmem_firmware {
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compatible = "xlnx,zynqmp-nvmem-fw";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Data cells */
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soc_revision: soc_revision {
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reg = <0x0 0x4>;
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};
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};
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};
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};
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= Data consumers =
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Are device nodes which consume nvmem data cells.
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For example:
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pcap {
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...
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nvmem-cells = <&soc_revision>;
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nvmem-cell-names = "soc_revision";
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...
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};
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@@ -129,6 +129,9 @@ Optional properties:
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- opp-microamp-<name>: Named opp-microamp property. Similar to
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opp-microvolt-<name> property, but for microamp instead.
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- opp-level: A value representing the performance level of the device,
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expressed as a 32-bit integer.
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- clock-latency-ns: Specifies the maximum possible transition latency (in
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nanoseconds) for switching to this OPP from any other OPP.
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@@ -32,6 +32,9 @@ Required properties:
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Optional properties:
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- power-supply: Power supply used to power the domain
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- clocks: a number of phandles to clocks that need to be enabled during
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domain power-up sequencing to ensure reset propagation into devices
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located inside this power domain
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Example:
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@@ -0,0 +1,145 @@
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Qualcomm RPM/RPMh Power domains
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For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh
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which then translates it into a corresponding voltage on a rail
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Required Properties:
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- compatible: Should be one of the following
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* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
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* qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC
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- #power-domain-cells: number of cells in Power domain specifier
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must be 1.
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- operating-points-v2: Phandle to the OPP table for the Power domain.
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Refer to Documentation/devicetree/bindings/power/power_domain.txt
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and Documentation/devicetree/bindings/opp/opp.txt for more details
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Refer to <dt-bindings/power/qcom-rpmpd.h> for the level values for
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various OPPs for different platforms as well as Power domain indexes
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Example: rpmh power domain controller and OPP table
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#include <dt-bindings/power/qcom-rpmhpd.h>
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opp-level values specified in the OPP tables for RPMh power domains
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should use the RPMH_REGULATOR_LEVEL_* constants from
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<dt-bindings/power/qcom-rpmhpd.h>
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rpmhpd: power-controller {
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compatible = "qcom,sdm845-rpmhpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmhpd_opp_table>;
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rpmhpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmhpd_opp_ret: opp1 {
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opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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};
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rpmhpd_opp_min_svs: opp2 {
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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rpmhpd_opp_low_svs: opp3 {
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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rpmhpd_opp_svs: opp4 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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rpmhpd_opp_svs_l1: opp5 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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rpmhpd_opp_nom: opp6 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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rpmhpd_opp_nom_l1: opp7 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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rpmhpd_opp_nom_l2: opp8 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
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};
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rpmhpd_opp_turbo: opp9 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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rpmhpd_opp_turbo_l1: opp10 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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};
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};
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Example: rpm power domain controller and OPP table
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rpmpd: power-controller {
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compatible = "qcom,msm8996-rpmpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmpd_opp_table>;
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rpmpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmpd_opp_low: opp1 {
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opp-level = <1>;
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};
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rpmpd_opp_ret: opp2 {
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opp-level = <2>;
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};
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rpmpd_opp_svs: opp3 {
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opp-level = <3>;
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};
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rpmpd_opp_normal: opp4 {
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opp-level = <4>;
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};
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rpmpd_opp_high: opp5 {
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opp-level = <5>;
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};
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rpmpd_opp_turbo: opp6 {
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opp-level = <6>;
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};
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};
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};
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Example: Client/Consumer device using OPP table
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leaky-device0@12350000 {
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compatible = "foo,i-leak-current";
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reg = <0x12350000 0x1000>;
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power-domains = <&rpmhpd SDM845_MX>;
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operating-points-v2 = <&leaky_opp_table>;
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};
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leaky_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp1 {
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opp-hz = /bits/ 64 <144000>;
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required-opps = <&rpmhpd_opp_low>;
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};
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opp2 {
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opp-hz = /bits/ 64 <400000>;
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required-opps = <&rpmhpd_opp_ret>;
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};
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opp3 {
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opp-hz = /bits/ 64 <20000000>;
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required-opps = <&rpmpd_opp_svs>;
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};
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opp4 {
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opp-hz = /bits/ 64 <25000000>;
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required-opps = <&rpmpd_opp_normal>;
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};
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};
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@@ -0,0 +1,25 @@
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--------------------------------------------------------------------
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Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
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--------------------------------------------------------------------
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The zynqmp-power node describes the power management configurations.
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It will control remote suspend/shutdown interfaces.
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Required properties:
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- compatible: Must contain: "xlnx,zynqmp-power"
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- interrupts: Interrupt specifier
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-------
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Example
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-------
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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method = "smc";
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zynqmp_power: zynqmp-power {
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compatible = "xlnx,zynqmp-power";
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interrupts = <0 35 4>;
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};
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};
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};
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@@ -0,0 +1,34 @@
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-----------------------------------------------------------
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Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
|
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-----------------------------------------------------------
|
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The binding for zynqmp-power-controller follow the common
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generic PM domain binding[1].
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[1] Documentation/devicetree/bindings/power/power_domain.txt
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|
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== Zynq MPSoC Generic PM Domain Node ==
|
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Required property:
|
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- Below property should be in zynqmp-firmware node.
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- #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
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||||
|
||||
Power domain ID indexes are mentioned in
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include/dt-bindings/power/xlnx-zynqmp-power.h.
|
||||
|
||||
-------
|
||||
Example
|
||||
-------
|
||||
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
...
|
||||
#power-domain-cells = <1>;
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
...
|
||||
power-domains = <&zynqmp_firmware 28>;
|
||||
...
|
||||
};
|
||||
@@ -0,0 +1,27 @@
|
||||
Broadcom STB SW_INIT-style reset controller
|
||||
===========================================
|
||||
|
||||
Broadcom STB SoCs have a SW_INIT-style reset controller with separate
|
||||
SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
|
||||
reset lines.
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be brcm,brcmstb-reset
|
||||
- reg: register base and length
|
||||
- #reset-cells: must be set to 1
|
||||
|
||||
Example:
|
||||
|
||||
reset: reset-controller@8404318 {
|
||||
compatible = "brcm,brcmstb-reset";
|
||||
reg = <0x8404318 0x30>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ðernet_switch {
|
||||
resets = <&reset>;
|
||||
reset-names = "switch";
|
||||
};
|
||||
@@ -5,7 +5,9 @@ Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx7d-src", "syscon"
|
||||
- compatible:
|
||||
- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
|
||||
- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain SRC interrupt
|
||||
@@ -44,4 +46,5 @@ Example:
|
||||
|
||||
|
||||
For list of all valid reset indicies see
|
||||
<dt-bindings/reset/imx7-reset.h>
|
||||
<dt-bindings/reset/imx7-reset.h> for i.MX7 and
|
||||
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
--------------------------------------------------------------------------
|
||||
= Zynq UltraScale+ MPSoC reset driver binding =
|
||||
--------------------------------------------------------------------------
|
||||
The Zynq UltraScale+ MPSoC has several different resets.
|
||||
|
||||
See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
|
||||
about zynqmp resets.
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required Properties:
|
||||
- compatible: "xlnx,zynqmp-reset"
|
||||
- #reset-cells: Specifies the number of cells needed to encode reset
|
||||
line, should be 1
|
||||
|
||||
-------
|
||||
Example
|
||||
-------
|
||||
|
||||
firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
method = "smc";
|
||||
|
||||
zynqmp_reset: reset-controller {
|
||||
compatible = "xlnx,zynqmp-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
|
||||
Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For list of all valid reset indicies see
|
||||
<dt-bindings/reset/xlnx-zynqmp-resets.h>
|
||||
|
||||
Example:
|
||||
|
||||
serdes: zynqmp_phy@fd400000 {
|
||||
...
|
||||
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
|
||||
reset-names = "sata_rst";
|
||||
|
||||
...
|
||||
};
|
||||
@@ -9,6 +9,8 @@ Required properties:
|
||||
"amlogic,meson-gx-clk-measure" for GX SoCs
|
||||
"amlogic,meson8-clk-measure" for Meson8 SoCs
|
||||
"amlogic,meson8b-clk-measure" for Meson8b SoCs
|
||||
"amlogic,meson-axg-clk-measure" for AXG SoCs
|
||||
"amlogic,meson-g12a-clk-measure" for G12a SoCs
|
||||
- reg: base address and size of the Clock Measurer register space.
|
||||
|
||||
Example:
|
||||
|
||||
@@ -0,0 +1,46 @@
|
||||
BCM2835 PM (Power domains, watchdog)
|
||||
|
||||
The PM block controls power domains and some reset lines, and includes
|
||||
a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt
|
||||
binding which covered some of PM's register range and functionality.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "brcm,bcm2835-pm"
|
||||
- reg: Specifies base physical address and size of the two
|
||||
register ranges ("PM" and "ASYNC_BRIDGE" in that
|
||||
order)
|
||||
- clocks: a) v3d: The V3D clock from CPRMAN
|
||||
b) peri_image: The PERI_IMAGE clock from CPRMAN
|
||||
c) h264: The H264 clock from CPRMAN
|
||||
d) isp: The ISP clock from CPRMAN
|
||||
- #reset-cells: Should be 1. This property follows the reset controller
|
||||
bindings[1].
|
||||
- #power-domain-cells: Should be 1. This property follows the power domain
|
||||
bindings[2].
|
||||
|
||||
Optional properties:
|
||||
|
||||
- timeout-sec: Contains the watchdog timeout in seconds
|
||||
- system-power-controller: Whether the watchdog is controlling the
|
||||
system power. This node follows the power controller bindings[3].
|
||||
|
||||
[1] Documentation/devicetree/bindings/reset/reset.txt
|
||||
[2] Documentation/devicetree/bindings/power/power_domain.txt
|
||||
[3] Documentation/devicetree/bindings/power/power-controller.txt
|
||||
|
||||
Example:
|
||||
|
||||
pm {
|
||||
compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x7e100000 0x114>,
|
||||
<0x7e00a000 0x24>;
|
||||
clocks = <&clocks BCM2835_CLOCK_V3D>,
|
||||
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
|
||||
<&clocks BCM2835_CLOCK_H264>,
|
||||
<&clocks BCM2835_CLOCK_ISP>;
|
||||
clock-names = "v3d", "peri_image", "h264", "isp";
|
||||
system-power-controller;
|
||||
};
|
||||
@@ -23,6 +23,7 @@ resources.
|
||||
"qcom,rpm-msm8916"
|
||||
"qcom,rpm-msm8974"
|
||||
"qcom,rpm-msm8998"
|
||||
"qcom,rpm-sdm660"
|
||||
"qcom,rpm-qcs404"
|
||||
|
||||
- qcom,smd-channels:
|
||||
|
||||
+32
-8
@@ -1940,19 +1940,37 @@ M: David Brown <david.brown@linaro.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/soc/qcom/
|
||||
F: Documentation/devicetree/bindings/*/qcom*
|
||||
F: arch/arm/boot/dts/qcom-*.dts
|
||||
F: arch/arm/boot/dts/qcom-*.dtsi
|
||||
F: arch/arm/mach-qcom/
|
||||
F: arch/arm64/boot/dts/qcom/*
|
||||
F: drivers/i2c/busses/i2c-qup.c
|
||||
F: drivers/clk/qcom/
|
||||
F: drivers/dma/qcom/
|
||||
F: drivers/soc/qcom/
|
||||
F: drivers/spi/spi-qup.c
|
||||
F: drivers/tty/serial/msm_serial.c
|
||||
F: arch/arm64/boot/dts/qcom/
|
||||
F: drivers/*/qcom/
|
||||
F: drivers/*/qcom*
|
||||
F: drivers/*/*/qcom/
|
||||
F: drivers/*/*/qcom*
|
||||
F: drivers/*/pm8???-*
|
||||
F: drivers/bluetooth/btqcomsmd.c
|
||||
F: drivers/clocksource/timer-qcom.c
|
||||
F: drivers/extcon/extcon-qcom*
|
||||
F: drivers/iommu/msm*
|
||||
F: drivers/i2c/busses/i2c-qup.c
|
||||
F: drivers/i2c/busses/i2c-qcom-geni.c
|
||||
F: drivers/mfd/ssbi.c
|
||||
F: drivers/firmware/qcom_scm*
|
||||
F: drivers/mmc/host/mmci_qcom*
|
||||
F: drivers/mmc/host/sdhci_msm.c
|
||||
F: drivers/pci/controller/dwc/pcie-qcom.c
|
||||
F: drivers/phy/qualcomm/
|
||||
F: drivers/power/*/msm*
|
||||
F: drivers/reset/reset-qcom-*
|
||||
F: drivers/scsi/ufs/ufs-qcom.*
|
||||
F: drivers/spi/spi-qup.c
|
||||
F: drivers/spi/spi-geni-qcom.c
|
||||
F: drivers/spi/spi-qcom-qspi.c
|
||||
F: drivers/tty/serial/msm_serial.c
|
||||
F: drivers/usb/dwc3/dwc3-qcom.c
|
||||
F: include/dt-bindings/*/qcom*
|
||||
F: include/linux/*/qcom*
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
|
||||
|
||||
ARM/RADISYS ENP2611 MACHINE SUPPORT
|
||||
@@ -11314,6 +11332,11 @@ M: Jens Wiklander <jens.wiklander@linaro.org>
|
||||
S: Maintained
|
||||
F: drivers/tee/optee/
|
||||
|
||||
OP-TEE RANDOM NUMBER GENERATOR (RNG) DRIVER
|
||||
M: Sumit Garg <sumit.garg@linaro.org>
|
||||
S: Maintained
|
||||
F: drivers/char/hw_random/optee-rng.c
|
||||
|
||||
OPA-VNIC DRIVER
|
||||
M: Dennis Dalessandro <dennis.dalessandro@intel.com>
|
||||
M: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
|
||||
@@ -13017,6 +13040,7 @@ F: drivers/reset/
|
||||
F: Documentation/devicetree/bindings/reset/
|
||||
F: include/dt-bindings/reset/
|
||||
F: include/linux/reset.h
|
||||
F: include/linux/reset/
|
||||
F: include/linux/reset-controller.h
|
||||
|
||||
RESTARTABLE SEQUENCES SUPPORT
|
||||
|
||||
@@ -85,10 +85,6 @@
|
||||
power-domains = <&power RPI_POWER_DOMAIN_USB>;
|
||||
};
|
||||
|
||||
&v3d {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_V3D>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
|
||||
status = "okay";
|
||||
|
||||
@@ -3,6 +3,7 @@
|
||||
#include <dt-bindings/clock/bcm2835-aux.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/soc/bcm2835-pm.h>
|
||||
|
||||
/* firmware-provided startup stubs live here, where the secondary CPUs are
|
||||
* spinning.
|
||||
@@ -120,9 +121,18 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
watchdog@7e100000 {
|
||||
compatible = "brcm,bcm2835-pm-wdt";
|
||||
reg = <0x7e100000 0x28>;
|
||||
pm: watchdog@7e100000 {
|
||||
compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x7e100000 0x114>,
|
||||
<0x7e00a000 0x24>;
|
||||
clocks = <&clocks BCM2835_CLOCK_V3D>,
|
||||
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
|
||||
<&clocks BCM2835_CLOCK_H264>,
|
||||
<&clocks BCM2835_CLOCK_ISP>;
|
||||
clock-names = "v3d", "peri_image", "h264", "isp";
|
||||
system-power-controller;
|
||||
};
|
||||
|
||||
clocks: cprman@7e101000 {
|
||||
@@ -629,6 +639,7 @@
|
||||
compatible = "brcm,bcm2835-v3d";
|
||||
reg = <0x7ec00000 0x1000>;
|
||||
interrupts = <1 10>;
|
||||
power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
|
||||
};
|
||||
|
||||
vc4: gpu {
|
||||
|
||||
@@ -167,6 +167,7 @@ config ARCH_BCM2835
|
||||
select BCM2835_TIMER
|
||||
select PINCTRL
|
||||
select PINCTRL_BCM2835
|
||||
select MFD_CORE
|
||||
help
|
||||
This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
|
||||
This SoC is used in the Raspberry Pi and Roku 2 devices.
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/reset/socfpga.h>
|
||||
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
@@ -32,8 +33,6 @@ void __iomem *rst_manager_base_addr;
|
||||
void __iomem *sdr_ctl_base_addr;
|
||||
unsigned long socfpga_cpu1start_addr;
|
||||
|
||||
extern void __init socfpga_reset_init(void);
|
||||
|
||||
static void __init socfpga_sysmgr_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
@@ -14,6 +14,7 @@
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset/sunxi.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/secure_cntvoff.h>
|
||||
@@ -37,7 +38,6 @@ static const char * const sun6i_board_dt_compat[] = {
|
||||
NULL,
|
||||
};
|
||||
|
||||
extern void __init sun6i_reset_init(void);
|
||||
static void __init sun6i_timer_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user