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Merge tag 'drm-msm-next-2021-06-23b' of https://gitlab.freedesktop.org/drm/msm into drm-next
* devcoredump support for display errors * dpu: irq cleanup/refactor * dpu: dt bindings conversion to yaml * dsi: dt bindings conversion to yaml * mdp5: alpha/blend_mode/zpos support * a6xx: cached coherent buffer support * a660 support * gpu iova fault improvements: - info about which block triggered the fault, etc - generation of gpu devcoredump on fault * assortment of other cleanups and fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs4=qsGBBbyn-4JWqW4-YUSTKh67X3DsPQ=T2D9aXKqNA@mail.gmail.com
This commit is contained in:
Dave Airlie
@@ -0,0 +1,146 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MSM Display Port Controller
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maintainers:
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- Kuogee Hsieh <khsieh@codeaurora.org>
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description: |
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Device tree bindings for DisplayPort host controller for MSM targets
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that are compatible with VESA DisplayPort interface specification.
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properties:
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compatible:
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enum:
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- qcom,sc7180-dp
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: AHB clock to enable register access
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- description: Display Port AUX clock
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- description: Display Port Link clock
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- description: Link interface clock between DP and PHY
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- description: Display Port Pixel clock
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clock-names:
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items:
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- const: core_iface
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- const: core_aux
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- const: ctrl_link
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- const: ctrl_link_iface
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- const: stream_pixel
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assigned-clocks:
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items:
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- description: link clock source
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- description: pixel clock source
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assigned-clock-parents:
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items:
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- description: phy 0 parent
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- description: phy 1 parent
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: dp
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operating-points-v2:
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maxItems: 1
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power-domains:
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maxItems: 1
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"#sound-dai-cells":
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const: 0
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input endpoint of the controller
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Output endpoint of the controller
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|
||||
required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phys
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- phy-names
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- "#sound-dai-cells"
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- power-domains
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
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#include <dt-bindings/power/qcom-aoss-qmp.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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displayport-controller@ae90000 {
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compatible = "qcom,sc7180-dp";
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reg = <0xae90000 0x1400>;
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interrupt-parent = <&mdss>;
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interrupts = <12>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
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clock-names = "core_iface", "core_aux",
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"ctrl_link",
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"ctrl_link_iface", "stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
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assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
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phys = <&dp_phy>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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power-domains = <&rpmhpd SC7180_CX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dpu_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&typec>;
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};
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};
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};
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};
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...
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@@ -0,0 +1,228 @@
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
title: Qualcomm Display DPU dt properties for SC7180 target
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maintainers:
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- Krishna Manikandan <mkrishn@codeaurora.org>
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description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS and DPU are mentioned for SC7180 target.
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properties:
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compatible:
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items:
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- const: qcom,sc7180-mdss
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reg:
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maxItems: 1
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reg-names:
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const: mdss
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AHB clock from dispcc
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: ahb
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- const: core
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#address-cells": true
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"#size-cells": true
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"#interrupt-cells":
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const: 1
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iommus:
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items:
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
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ranges: true
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interconnects:
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items:
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- description: Interconnect path specifying the port ids for data bus
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interconnect-names:
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const: mdp0-mem
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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||||
description: Node containing the properties of DPU.
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properties:
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compatible:
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items:
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- const: qcom,sc7180-dpu
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reg:
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items:
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||||
- description: Address offset and size for mdp register set
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||||
- description: Address offset and size for vbif register set
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reg-names:
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||||
items:
|
||||
- const: mdp
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||||
- const: vbif
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||||
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clocks:
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items:
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- description: Display hf axi clock
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||||
- description: Display ahb clock
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- description: Display rotator clock
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||||
- description: Display lut clock
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- description: Display core clock
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- description: Display vsync clock
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||||
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||||
clock-names:
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||||
items:
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||||
- const: bus
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||||
- const: iface
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||||
- const: rot
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- const: lut
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||||
- const: core
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||||
- const: vsync
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||||
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||||
interrupts:
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||||
maxItems: 1
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||||
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||||
power-domains:
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||||
maxItems: 1
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||||
|
||||
operating-points-v2: true
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||||
|
||||
ports:
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||||
$ref: /schemas/graph.yaml#/properties/ports
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||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
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||||
description: DPU_INTF1 (DSI1)
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||||
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||||
port@2:
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||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF0 (DP)
|
||||
|
||||
required:
|
||||
- port@0
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||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
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||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
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||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
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||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
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||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
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||||
#include <dt-bindings/interconnect/qcom,sdm845.h>
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||||
#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sc7180-mdss";
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reg = <0xae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "ahb", "core";
|
||||
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||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
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interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
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ranges;
|
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|
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display-controller@ae01000 {
|
||||
compatible = "qcom,sc7180-dpu";
|
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reg = <0x0ae01000 0x8f000>,
|
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<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "rot", "lut", "core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
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@@ -0,0 +1,212 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SDM845 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SDM845 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
|
||||
|
||||
ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF2 (DSI2)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x880 0x8>,
|
||||
<&apps_smmu 0xc80 0x8>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -1,141 +0,0 @@
|
||||
Qualcomm Technologies, Inc. DPU KMS
|
||||
|
||||
Description:
|
||||
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
||||
The DPU display controller is found in SDM845 SoC.
|
||||
|
||||
MDSS:
|
||||
Required properties:
|
||||
- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
|
||||
- reg: physical base address and length of controller's registers.
|
||||
- reg-names: register region names. The following region is required:
|
||||
* "mdss"
|
||||
- power-domains: a power domain consumer specifier according to
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- clocks: list of clock specifiers for clocks needed by the device.
|
||||
- clock-names: device clock names, must be in same order as clocks property.
|
||||
The following clocks are required:
|
||||
* "iface"
|
||||
* "bus"
|
||||
* "core"
|
||||
- interrupts: interrupt signal from MDSS.
|
||||
- interrupt-controller: identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- iommus: phandle of iommu device node.
|
||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
- ranges: parent bus address space is the same as the child bus address space.
|
||||
- interconnects : interconnect path specifier for MDSS according to
|
||||
Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
|
||||
2 paths corresponding to 2 AXI ports.
|
||||
- interconnect-names : MDSS will have 2 port names to differentiate between the
|
||||
2 interconnect paths defined with interconnect specifier.
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
|
||||
- assigned-clock-rates: list of clock frequencies sorted in the same order as
|
||||
the assigned-clocks property.
|
||||
|
||||
MDP:
|
||||
Required properties:
|
||||
- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
|
||||
- reg: physical base address and length of controller's registers.
|
||||
- reg-names : register region names. The following region is required:
|
||||
* "mdp"
|
||||
* "vbif"
|
||||
- clocks: list of clock specifiers for clocks needed by the device.
|
||||
- clock-names: device clock names, must be in same order as clocks property.
|
||||
The following clocks are required.
|
||||
* "bus"
|
||||
* "iface"
|
||||
* "core"
|
||||
* "vsync"
|
||||
- interrupts: interrupt line from DPU to MDSS.
|
||||
- ports: contains the list of output ports from DPU device. These ports connect
|
||||
to interfaces that are external to the DPU hardware, such as DSI, DP etc.
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Port 0 -> DPU_INTF1 (DSI1)
|
||||
Port 1 -> DPU_INTF2 (DSI2)
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
|
||||
- assigned-clock-rates: list of clock frequencies sorted in the same order as
|
||||
the assigned-clocks property.
|
||||
|
||||
Example:
|
||||
|
||||
mdss: mdss@ae00000 {
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
power-domains = <&clock_dispcc 0>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
assigned-clock-rates = <300000000>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
|
||||
<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
|
||||
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
iommus = <&apps_iommu 0>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xae00000 0xb2008>;
|
||||
|
||||
mdss_mdp: mdp@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <0 0 300000000 19200000>;
|
||||
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,185 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI controller
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "../dsi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: dsi_ctrl
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display byte clock
|
||||
- description: Display byte interface clock
|
||||
- description: Display pixel clock
|
||||
- description: Display escape clock
|
||||
- description: Display AHB clock
|
||||
- description: Display AXI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: dsi
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
syscon-sfpb:
|
||||
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
qcom,dual-dsi-mode:
|
||||
type: boolean
|
||||
description: |
|
||||
Indicates if the DSI controller is driving a panel which needs
|
||||
2 DSI links.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
ports:
|
||||
$ref: "/schemas/graph.yaml#/properties/ports"
|
||||
description: |
|
||||
Contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
description: |
|
||||
Input endpoints of the controller.
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
port@1:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
description: |
|
||||
Output endpoints of the controller.
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 10nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-10nm
|
||||
- const: qcom,dsi-phy-10nm-8998
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy lane register set
|
||||
- description: dsi pll register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_lane
|
||||
- const: dsi_pll
|
||||
|
||||
vdds-supply:
|
||||
description: |
|
||||
Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
|
||||
connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vdds-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 14nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-14nm
|
||||
- const: qcom,dsi-phy-14nm-660
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy lane register set
|
||||
- description: dsi pll register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_lane
|
||||
- const: dsi_pll
|
||||
|
||||
vcca-supply:
|
||||
description: Phandle to vcca regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vcca-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-14nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 20nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-20nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi pll register set
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy regulator register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_pll
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_regulator
|
||||
|
||||
vcca-supply:
|
||||
description: Phandle to vcca regulator device node.
|
||||
|
||||
vddio-supply:
|
||||
description: Phandle to vdd-io regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vddio-supply
|
||||
- vcca-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-20nm";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 28nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-28nm-hpm
|
||||
- const: qcom,dsi-phy-28nm-lp
|
||||
- const: qcom,dsi-phy-28nm-8960
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi pll register set
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy regulator register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_pll
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_regulator
|
||||
|
||||
vddio-supply:
|
||||
description: Phandle to vdd-io regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vddio-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-lp";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,40 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Description of Qualcomm Display DSI PHY common dt properties
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
This defines the DSI PHY dt properties which are common for all
|
||||
dsi phy versions.
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ref
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: true
|
||||
...
|
||||
@@ -1,249 +0,0 @@
|
||||
Qualcomm Technologies Inc. adreno/snapdragon DSI output
|
||||
|
||||
DSI Controller:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdss-dsi-ctrl"
|
||||
- reg: Physical base address and length of the registers of controller
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "dsi_ctrl"
|
||||
- interrupts: The interrupt signal from the DSI block.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: Phandles to device clocks.
|
||||
- clock-names: the following clocks are required:
|
||||
* "mdp_core"
|
||||
* "iface"
|
||||
* "bus"
|
||||
* "core_mmss"
|
||||
* "byte"
|
||||
* "pixel"
|
||||
* "core"
|
||||
For DSIv2, we need an additional clock:
|
||||
* "src"
|
||||
For DSI6G v2.0 onwards, we need also need the clock:
|
||||
* "byte_intf"
|
||||
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
|
||||
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
|
||||
by a DSI PHY block. See [1] for details on clock bindings.
|
||||
- vdd-supply: phandle to vdd regulator device node
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vdda-supply: phandle to vdda regulator device node
|
||||
- phys: phandle to DSI PHY device node
|
||||
- phy-names: the name of the corresponding PHY device
|
||||
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
|
||||
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
|
||||
an endpoint subnode as defined in [2] and [3].
|
||||
|
||||
Optional properties:
|
||||
- panel@0: Node of panel connected to this DSI controller.
|
||||
See files in [4] for each supported panel.
|
||||
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
|
||||
driving a panel which needs 2 DSI links.
|
||||
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
|
||||
the master link of the 2-DSI panel.
|
||||
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
|
||||
driving a 2-DSI panel whose 2 links need receive command simultaneously.
|
||||
- pinctrl-names: the pin control state names; should contain "default"
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-n: the "sleep" pinctrl state
|
||||
- ports: contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
DSI Endpoint properties:
|
||||
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
|
||||
input endpoint. For port@1, set to the MDP interface output. See [2] for
|
||||
device graph info.
|
||||
|
||||
- data-lanes: this describes how the physical DSI data lanes are mapped
|
||||
to the logical lanes on the given platform. The value contained in
|
||||
index n describes what physical lane is mapped to the logical lane n
|
||||
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
|
||||
and can't be changed. Hence, they aren't a part of the DT bindings. See
|
||||
[3] for more info on the data-lanes property.
|
||||
|
||||
For example:
|
||||
|
||||
data-lanes = <3 0 1 2>;
|
||||
|
||||
The above mapping describes that the logical data lane DATA0 is mapped to
|
||||
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
|
||||
to phys DATA1 and logic DATA3 to phys DATA2.
|
||||
|
||||
There are only a limited number of physical to logical mappings possible:
|
||||
<0 1 2 3>
|
||||
<1 2 3 0>
|
||||
<2 3 0 1>
|
||||
<3 0 1 2>
|
||||
<0 3 2 1>
|
||||
<1 0 3 2>
|
||||
<2 1 0 3>
|
||||
<3 2 1 0>
|
||||
|
||||
DSI PHY:
|
||||
Required properties:
|
||||
- compatible: Could be the following
|
||||
* "qcom,dsi-phy-28nm-hpm"
|
||||
* "qcom,dsi-phy-28nm-lp"
|
||||
* "qcom,dsi-phy-20nm"
|
||||
* "qcom,dsi-phy-28nm-8960"
|
||||
* "qcom,dsi-phy-14nm"
|
||||
* "qcom,dsi-phy-14nm-660"
|
||||
* "qcom,dsi-phy-10nm"
|
||||
* "qcom,dsi-phy-10nm-8998"
|
||||
* "qcom,dsi-phy-7nm"
|
||||
* "qcom,dsi-phy-7nm-8150"
|
||||
- reg: Physical base address and length of the registers of PLL, PHY. Some
|
||||
revisions require the PHY regulator base address, whereas others require the
|
||||
PHY lane base address. See below for each PHY revision.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_regulator"
|
||||
For DSI 14nm, 10nm and 7nm PHYs:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_lane"
|
||||
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
|
||||
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
|
||||
- clock-names: the following clocks are required:
|
||||
* "iface"
|
||||
* "ref" (only required for new DTS files/entries)
|
||||
For 28nm HPM/LP, 28nm 8960 PHYs:
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
For 20nm PHY:
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vcca-supply: phandle to vcca regulator device node
|
||||
For 14nm PHY:
|
||||
- vcca-supply: phandle to vcca regulator device node
|
||||
For 10nm and 7nm PHY:
|
||||
- vdds-supply: phandle to vdds regulator device node
|
||||
|
||||
Optional properties:
|
||||
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
||||
regulator is wanted.
|
||||
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
|
||||
panels in microseconds. Driver uses this number to adjust
|
||||
the clock rate according to the expected transfer time.
|
||||
Increasing this value would slow down the mdp processing
|
||||
and can result in slower performance.
|
||||
Decreasing this value can speed up the mdp processing,
|
||||
but this can also impact power consumption.
|
||||
As a rule this time should not be higher than the time
|
||||
that would be expected with the processing at the
|
||||
dsi link rate since anyways this would be the maximum
|
||||
transfer time that could be achieved.
|
||||
If ping pong split is enabled, this time should not be higher
|
||||
than two times the dsi link rate time.
|
||||
If the property is not specified, then the default value is 14000 us.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/graph.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/display/panel/
|
||||
|
||||
Example:
|
||||
dsi0: dsi@fd922800 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
qcom,dsi-host-index = <0>;
|
||||
interrupt-parent = <&mdp>;
|
||||
interrupts = <4 0>;
|
||||
reg-names = "dsi_ctrl";
|
||||
reg = <0xfd922800 0x200>;
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
clock-names =
|
||||
"bus",
|
||||
"byte",
|
||||
"core",
|
||||
"core_mmss",
|
||||
"iface",
|
||||
"mdp_core",
|
||||
"pixel";
|
||||
clocks =
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MDSS_BYTE0_CLK>,
|
||||
<&mmcc MDSS_ESC0_CLK>,
|
||||
<&mmcc MMSS_MISC_AHB_CLK>,
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_PCLK0_CLK>;
|
||||
|
||||
assigned-clocks =
|
||||
<&mmcc BYTE0_CLK_SRC>,
|
||||
<&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents =
|
||||
<&dsi_phy0 0>,
|
||||
<&dsi_phy0 1>;
|
||||
|
||||
vdda-supply = <&pma8084_l2>;
|
||||
vdd-supply = <&pma8084_l22>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
phys = <&dsi_phy0>;
|
||||
phy-names ="dsi-phy";
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
qcom,sync-dual-dsi;
|
||||
|
||||
qcom,mdss-mdp-transfer-time-us = <12000>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&dsi_active>;
|
||||
pinctrl-1 = <&dsi_suspend>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel@0 {
|
||||
compatible = "sharp,lq101r1sx01";
|
||||
reg = <0>;
|
||||
link2 = <&secondary>;
|
||||
|
||||
power-supply = <...>;
|
||||
backlight = <...>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_phy0: dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-hpm";
|
||||
qcom,dsi-phy-index = <0>;
|
||||
reg-names =
|
||||
"dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
clock-names = "iface";
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy-regulator-ldo-mode;
|
||||
};
|
||||
@@ -1,6 +1,7 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Red Hat
|
||||
* Copyright (C) 2014 Intel Corp.
|
||||
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -1609,9 +1610,20 @@ commit:
|
||||
}
|
||||
EXPORT_SYMBOL(__drm_atomic_helper_set_config);
|
||||
|
||||
void drm_atomic_print_state(const struct drm_atomic_state *state)
|
||||
/**
|
||||
* drm_atomic_print_new_state - prints drm atomic state
|
||||
* @state: atomic configuration to check
|
||||
* @p: drm printer
|
||||
*
|
||||
* This functions prints the drm atomic state snapshot using the drm printer
|
||||
* which is passed to it. This snapshot can be used for debugging purposes.
|
||||
*
|
||||
* Note that this function looks into the new state objects and hence its not
|
||||
* safe to be used after the call to drm_atomic_helper_commit_hw_done().
|
||||
*/
|
||||
void drm_atomic_print_new_state(const struct drm_atomic_state *state,
|
||||
struct drm_printer *p)
|
||||
{
|
||||
struct drm_printer p = drm_info_printer(state->dev->dev);
|
||||
struct drm_plane *plane;
|
||||
struct drm_plane_state *plane_state;
|
||||
struct drm_crtc *crtc;
|
||||
@@ -1620,17 +1632,23 @@ void drm_atomic_print_state(const struct drm_atomic_state *state)
|
||||
struct drm_connector_state *connector_state;
|
||||
int i;
|
||||
|
||||
if (!p) {
|
||||
DRM_ERROR("invalid drm printer\n");
|
||||
return;
|
||||
}
|
||||
|
||||
DRM_DEBUG_ATOMIC("checking %p\n", state);
|
||||
|
||||
for_each_new_plane_in_state(state, plane, plane_state, i)
|
||||
drm_atomic_plane_print_state(&p, plane_state);
|
||||
drm_atomic_plane_print_state(p, plane_state);
|
||||
|
||||
for_each_new_crtc_in_state(state, crtc, crtc_state, i)
|
||||
drm_atomic_crtc_print_state(&p, crtc_state);
|
||||
drm_atomic_crtc_print_state(p, crtc_state);
|
||||
|
||||
for_each_new_connector_in_state(state, connector, connector_state, i)
|
||||
drm_atomic_connector_print_state(&p, connector_state);
|
||||
drm_atomic_connector_print_state(p, connector_state);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_atomic_print_new_state);
|
||||
|
||||
static void __drm_state_dump(struct drm_device *dev, struct drm_printer *p,
|
||||
bool take_locks)
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
* Copyright (C) 2014 Red Hat
|
||||
* Copyright (C) 2014 Intel Corp.
|
||||
* Copyright (C) 2018 Intel Corp.
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -1321,6 +1322,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
|
||||
struct drm_out_fence_state *fence_state;
|
||||
int ret = 0;
|
||||
unsigned int i, j, num_fences;
|
||||
struct drm_printer p = drm_info_printer(dev->dev);
|
||||
|
||||
/* disallow for drivers not supporting atomic: */
|
||||
if (!drm_core_check_feature(dev, DRIVER_ATOMIC))
|
||||
@@ -1453,7 +1455,7 @@ retry:
|
||||
ret = drm_atomic_nonblocking_commit(state);
|
||||
} else {
|
||||
if (drm_debug_enabled(DRM_UT_STATE))
|
||||
drm_atomic_print_state(state);
|
||||
drm_atomic_print_new_state(state, &p);
|
||||
|
||||
ret = drm_atomic_commit(state);
|
||||
}
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
* Jesse Barnes <jesse.barnes@intel.com>
|
||||
* Copyright © 2014 Intel Corporation
|
||||
* Daniel Vetter <daniel.vetter@ffwll.ch>
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -236,7 +237,8 @@ int __drm_atomic_helper_disable_plane(struct drm_plane *plane,
|
||||
int __drm_atomic_helper_set_config(struct drm_mode_set *set,
|
||||
struct drm_atomic_state *state);
|
||||
|
||||
void drm_atomic_print_state(const struct drm_atomic_state *state);
|
||||
void drm_atomic_print_new_state(const struct drm_atomic_state *state,
|
||||
struct drm_printer *p);
|
||||
|
||||
/* drm_atomic_uapi.c */
|
||||
int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state,
|
||||
|
||||
@@ -58,7 +58,6 @@ msm-y := \
|
||||
disp/dpu1/dpu_encoder_phys_cmd.o \
|
||||
disp/dpu1/dpu_encoder_phys_vid.o \
|
||||
disp/dpu1/dpu_formats.o \
|
||||
disp/dpu1/dpu_hw_blk.o \
|
||||
disp/dpu1/dpu_hw_catalog.o \
|
||||
disp/dpu1/dpu_hw_ctl.o \
|
||||
disp/dpu1/dpu_hw_interrupts.o \
|
||||
@@ -77,6 +76,8 @@ msm-y := \
|
||||
disp/dpu1/dpu_plane.o \
|
||||
disp/dpu1/dpu_rm.o \
|
||||
disp/dpu1/dpu_vbif.o \
|
||||
disp/msm_disp_snapshot.o \
|
||||
disp/msm_disp_snapshot_util.o \
|
||||
msm_atomic.o \
|
||||
msm_atomic_tracepoints.o \
|
||||
msm_debugfs.o \
|
||||
|
||||
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@@ -1258,11 +1258,17 @@ static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
|
||||
|
||||
#define REG_A2XX_NQWAIT_UNTIL 0x00000394
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399
|
||||
|
||||
#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a
|
||||
|
||||
#define REG_A2XX_RBBM_DEBUG 0x0000039b
|
||||
|
||||
@@ -2922,10 +2928,28 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e
|
||||
|
||||
#define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f
|
||||
|
||||
#define REG_A2XX_SQ_TEX_0 0x00000000
|
||||
#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
|
||||
#define A2XX_SQ_TEX_0_TYPE__SHIFT 0
|
||||
|
||||
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@@ -1215,7 +1215,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
|
||||
#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
|
||||
@@ -1328,7 +1328,7 @@ static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
|
||||
#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_GREEN 0x000020e5
|
||||
@@ -1342,7 +1342,7 @@ static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
|
||||
#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_BLUE 0x000020e6
|
||||
@@ -1356,7 +1356,7 @@ static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
|
||||
#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
|
||||
@@ -1370,7 +1370,7 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
|
||||
#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
|
||||
|
||||
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@@ -1085,7 +1085,7 @@ static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
|
||||
#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
|
||||
@@ -1113,7 +1113,7 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
|
||||
#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
|
||||
@@ -1141,7 +1141,7 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
|
||||
#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
|
||||
@@ -1169,7 +1169,7 @@ static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
|
||||
#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
||||
static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
|
||||
|
||||
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
|
||||
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
|
||||
|
||||
Copyright (C) 2013-2020 by the following authors:
|
||||
Copyright (C) 2013-2021 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@@ -2021,6 +2021,7 @@ static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
|
||||
#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
|
||||
|
||||
#define REG_A5XX_RBBM_STATUS3 0x00000530
|
||||
#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
|
||||
|
||||
#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
|
||||
|
||||
@@ -2351,6 +2352,7 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
||||
#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
|
||||
|
||||
#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
|
||||
#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
|
||||
|
||||
#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
|
||||
|
||||
@@ -2808,7 +2810,19 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
||||
#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
|
||||
#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E001 0x0000e001
|
||||
#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
|
||||
static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
|
||||
#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
|
||||
static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E004 0x0000e004
|
||||
|
||||
@@ -3345,7 +3359,7 @@ static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
|
||||
#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
|
||||
@@ -3373,7 +3387,7 @@ static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
|
||||
#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
|
||||
@@ -3401,7 +3415,7 @@ static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
|
||||
#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
|
||||
@@ -3429,7 +3443,7 @@ static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
|
||||
#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
|
||||
@@ -3806,7 +3820,25 @@ static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294
|
||||
|
||||
#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E29A 0x0000e29a
|
||||
#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
|
||||
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
|
||||
}
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
|
||||
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
|
||||
}
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
|
||||
#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
|
||||
static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VPC_PACK 0x0000e29d
|
||||
#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
|
||||
@@ -3910,7 +3942,13 @@ static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su
|
||||
}
|
||||
#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E389 0x0000e389
|
||||
#define REG_A5XX_PC_CLIP_CNTL 0x0000e389
|
||||
#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
|
||||
#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
|
||||
static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
|
||||
|
||||
@@ -4302,7 +4340,12 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
||||
#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
|
||||
|
||||
#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
|
||||
#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
|
||||
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
|
||||
#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
|
||||
static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
|
||||
}
|
||||
#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
|
||||
#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
|
||||
|
||||
@@ -5192,8 +5235,8 @@ static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
|
||||
}
|
||||
|
||||
#define REG_A5XX_TEX_SAMP_2 0x00000002
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
|
||||
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
|
||||
static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
|
||||
@@ -5273,6 +5316,7 @@ static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
|
||||
}
|
||||
|
||||
#define REG_A5XX_TEX_CONST_2 0x00000002
|
||||
#define A5XX_TEX_CONST_2_UNK4 0x00000010
|
||||
#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
|
||||
#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
|
||||
static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
|
||||
@@ -5291,6 +5335,7 @@ static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
|
||||
{
|
||||
return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
|
||||
}
|
||||
#define A5XX_TEX_CONST_2_UNK31 0x80000000
|
||||
|
||||
#define REG_A5XX_TEX_CONST_3 0x00000003
|
||||
#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
|
||||
|
||||
@@ -902,7 +902,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
|
||||
if (!a5xx_gpu->shadow_bo) {
|
||||
a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
|
||||
sizeof(u32) * gpu->nr_rings,
|
||||
MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
|
||||
MSM_BO_WC | MSM_BO_MAP_PRIV,
|
||||
gpu->aspace, &a5xx_gpu->shadow_bo,
|
||||
&a5xx_gpu->shadow_iova);
|
||||
|
||||
@@ -1075,7 +1075,7 @@ bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
|
||||
return true;
|
||||
}
|
||||
|
||||
static int a5xx_fault_handler(void *arg, unsigned long iova, int flags)
|
||||
static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
|
||||
{
|
||||
struct msm_gpu *gpu = arg;
|
||||
pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
|
||||
@@ -1085,7 +1085,7 @@ static int a5xx_fault_handler(void *arg, unsigned long iova, int flags)
|
||||
gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)),
|
||||
gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));
|
||||
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void a5xx_cp_err_irq(struct msm_gpu *gpu)
|
||||
@@ -1200,6 +1200,15 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu)
|
||||
struct drm_device *dev = gpu->dev;
|
||||
struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
|
||||
|
||||
/*
|
||||
* If stalled on SMMU fault, we could trip the GPU's hang detection,
|
||||
* but the fault handler will trigger the devcore dump, and we want
|
||||
* to otherwise resume normally rather than killing the submit, so
|
||||
* just bail.
|
||||
*/
|
||||
if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24))
|
||||
return;
|
||||
|
||||
DRM_DEV_ERROR(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
|
||||
ring ? ring->id : -1, ring ? ring->seqno : 0,
|
||||
gpu_read(gpu, REG_A5XX_RBBM_STATUS),
|
||||
@@ -1407,7 +1416,7 @@ static int a5xx_crashdumper_init(struct msm_gpu *gpu,
|
||||
struct a5xx_crashdumper *dumper)
|
||||
{
|
||||
dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
|
||||
SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
|
||||
SZ_1M, MSM_BO_WC, gpu->aspace,
|
||||
&dumper->bo, &dumper->iova);
|
||||
|
||||
if (!IS_ERR(dumper->ptr))
|
||||
@@ -1523,6 +1532,7 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu)
|
||||
{
|
||||
struct a5xx_gpu_state *a5xx_state = kzalloc(sizeof(*a5xx_state),
|
||||
GFP_KERNEL);
|
||||
bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24));
|
||||
|
||||
if (!a5xx_state)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
@@ -1535,8 +1545,13 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu)
|
||||
|
||||
a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS);
|
||||
|
||||
/* Get the HLSQ regs with the help of the crashdumper */
|
||||
a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
|
||||
/*
|
||||
* Get the HLSQ regs with the help of the crashdumper, but only if
|
||||
* we are not stalled in an iommu fault (in which case the crashdumper
|
||||
* would not have access to memory)
|
||||
*/
|
||||
if (!stalled)
|
||||
a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
|
||||
|
||||
a5xx_set_hwcg(gpu, true);
|
||||
|
||||
@@ -1705,7 +1720,7 @@ static void check_speed_bin(struct device *dev)
|
||||
nvmem_cell_put(cell);
|
||||
}
|
||||
|
||||
dev_pm_opp_set_supported_hw(dev, &val, 1);
|
||||
devm_pm_opp_set_supported_hw(dev, &val, 1);
|
||||
}
|
||||
|
||||
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user