mirror of
https://github.com/t2linux/kernel.git
synced 2026-04-30 13:48:59 -07:00
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull more clk updates from Stephen Boyd: "Here's some more updates that missed the last pull request because I happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs clk: drop unused function __clk_get_flags clk: hsdk: Fix bad dependency on IOMEM dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: mmp: avoid missing prototype warning clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file clk: qoriq: add LS1021A core pll mux options clk: clk-atlas6: fix return value check in atlas6_clk_init() clk: tegra: pll: Improve PLLM enable-state detection clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset ...
This commit is contained in:
Linus Torvalds
@@ -10,6 +10,15 @@ maintainers:
|
||||
- Eric Anholt <eric@anholt.net>
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: raspberrypi,bcm2835-firmware
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
|
||||
@@ -1,125 +0,0 @@
|
||||
Binding for IDT VersaClock 5,6 programmable i2c clock generators.
|
||||
|
||||
The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
|
||||
generators providing from 3 to 12 output clocks.
|
||||
|
||||
==I2C device node==
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of
|
||||
"idt,5p49v5923"
|
||||
"idt,5p49v5925"
|
||||
"idt,5p49v5933"
|
||||
"idt,5p49v5935"
|
||||
"idt,5p49v6901"
|
||||
"idt,5p49v6965"
|
||||
- reg: i2c device address, shall be 0x68 or 0x6a.
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
- 5p49v5923 and
|
||||
5p49v5925 and
|
||||
5p49v6901: (required) either or both of XTAL or CLKIN
|
||||
reference clock.
|
||||
- 5p49v5933 and
|
||||
- 5p49v5935: (optional) property not present (internal
|
||||
Xtal used) or CLKIN reference
|
||||
clock.
|
||||
- clock-names: from common clock binding; clock input names, can be
|
||||
- 5p49v5923 and
|
||||
5p49v5925 and
|
||||
5p49v6901: (required) either or both of "xin", "clkin".
|
||||
- 5p49v5933 and
|
||||
- 5p49v5935: (optional) property not present or "clkin".
|
||||
|
||||
For all output ports, a corresponding, optional child node named OUT1,
|
||||
OUT2, etc. can represent a each output, and the node can be used to
|
||||
specify the following:
|
||||
|
||||
- itd,mode: can be one of the following:
|
||||
- VC5_LVPECL
|
||||
- VC5_CMOS
|
||||
- VC5_HCSL33
|
||||
- VC5_LVDS
|
||||
- VC5_CMOS2
|
||||
- VC5_CMOSD
|
||||
- VC5_HCSL25
|
||||
|
||||
- idt,voltage-microvolts: can be one of the following
|
||||
- 1800000
|
||||
- 2500000
|
||||
- 3300000
|
||||
- idt,slew-percent: Percent of normal, can be one of
|
||||
- 80
|
||||
- 85
|
||||
- 90
|
||||
- 100
|
||||
|
||||
==Mapping between clock specifier and physical pins==
|
||||
|
||||
When referencing the provided clock in the DT using phandle and
|
||||
clock specifier, the following mapping applies:
|
||||
|
||||
5P49V5923:
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||||
0 -- OUT0_SEL_I2CB
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1 -- OUT1
|
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2 -- OUT2
|
||||
|
||||
5P49V5933:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT4
|
||||
|
||||
5P49V5925 and
|
||||
5P49V5935:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
5P49V6901:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
==Example==
|
||||
|
||||
/* 25MHz reference crystal */
|
||||
ref25: ref25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c-master-node {
|
||||
|
||||
/* IDT 5P49V5923 i2c clock generator */
|
||||
vc5: clock-generator@6a {
|
||||
compatible = "idt,5p49v5923";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* Connect XIN input to 25MHz reference */
|
||||
clocks = <&ref25m>;
|
||||
clock-names = "xin";
|
||||
|
||||
OUT1 {
|
||||
itd,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolts = <1800000>;
|
||||
idt,slew-percent = <80>;
|
||||
};
|
||||
OUT2 {
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
/* Consumer referencing the 5P49V5923 pin OUT1 */
|
||||
consumer {
|
||||
...
|
||||
clocks = <&vc5 1>;
|
||||
...
|
||||
}
|
||||
@@ -0,0 +1,154 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
|
||||
|
||||
description: |
|
||||
The IDT VersaClock 5 and VersaClock 6 are programmable I2C
|
||||
clock generators providing from 3 to 12 output clocks.
|
||||
|
||||
When referencing the provided clock in the DT using phandle and clock
|
||||
specifier, the following mapping applies:
|
||||
|
||||
- 5P49V5923:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
|
||||
- 5P49V5933:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT4
|
||||
|
||||
- other parts:
|
||||
0 -- OUT0_SEL_I2CB
|
||||
1 -- OUT1
|
||||
2 -- OUT2
|
||||
3 -- OUT3
|
||||
4 -- OUT4
|
||||
|
||||
maintainers:
|
||||
- Luca Ceresoli <luca@lucaceresoli.net>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- idt,5p49v5923
|
||||
- idt,5p49v5925
|
||||
- idt,5p49v5933
|
||||
- idt,5p49v5935
|
||||
- idt,5p49v6901
|
||||
- idt,5p49v6965
|
||||
|
||||
reg:
|
||||
description: I2C device address
|
||||
enum: [ 0x68, 0x6a ]
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^OUT[1-4]$":
|
||||
type: object
|
||||
description:
|
||||
Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
|
||||
Configuration" in the Versaclock 5/6/6E Family Register Description
|
||||
and Programming Guide.
|
||||
properties:
|
||||
idt,mode:
|
||||
description:
|
||||
The output drive mode. Values defined in dt-bindings/clk/versaclock.h
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 6
|
||||
idt,voltage-microvolt:
|
||||
description: The output drive voltage.
|
||||
enum: [ 1800000, 2500000, 3300000 ]
|
||||
idt,slew-percent:
|
||||
description: The Slew rate control for CMOS single-ended.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 80, 85, 90, 100 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- idt,5p49v5933
|
||||
- idt,5p49v5935
|
||||
then:
|
||||
# Devices with builtin crystal + optional external input
|
||||
properties:
|
||||
clock-names:
|
||||
const: clkin
|
||||
clocks:
|
||||
maxItems: 1
|
||||
else:
|
||||
# Devices without builtin crystal
|
||||
properties:
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
enum: [ xin, clkin ]
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
required:
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
|
||||
/* 25MHz reference crystal */
|
||||
ref25: ref25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
reg = <0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* IDT 5P49V5923 I2C clock generator */
|
||||
vc5: clock-generator@6a {
|
||||
compatible = "idt,5p49v5923";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
/* Connect XIN input to 25MHz reference */
|
||||
clocks = <&ref25m>;
|
||||
clock-names = "xin";
|
||||
|
||||
OUT1 {
|
||||
idt,drive-mode = <VC5_CMOSD>;
|
||||
idt,voltage-microvolts = <1800000>;
|
||||
idt,slew-percent = <80>;
|
||||
};
|
||||
|
||||
OUT4 {
|
||||
idt,drive-mode = <VC5_LVDS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Consumer referencing the 5P49V5923 pin OUT1 */
|
||||
consumer {
|
||||
/* ... */
|
||||
clocks = <&vc5 1>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
...
|
||||
+13
-5
@@ -1,23 +1,31 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
power domains on SDM845/SC7180/SM8150/SM8250.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sdm845.h.
|
||||
See also:
|
||||
dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-gpucc
|
||||
enum:
|
||||
- qcom,sdm845-gpucc
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sm8150-gpucc
|
||||
- qcom,sm8250-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,kryocc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,msm8996-apcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm clock controller for MSM8996 CPUs
|
||||
@@ -46,11 +46,9 @@ required:
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Example for msm8996
|
||||
- |
|
||||
kryocc: clock-controller@6400000 {
|
||||
compatible = "qcom,msm8996-apcc";
|
||||
reg = <0x6400000 0x90000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
@@ -1,74 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_gpu_gpll0_clk_src
|
||||
- const: gcc_gpu_gpll0_div_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@5090000 {
|
||||
compatible = "qcom,sc7180-gpucc";
|
||||
reg = <0x05090000 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,108 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core Clock Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core clock control module which supports the clocks and
|
||||
power domains on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpasscorecc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-lpasshm
|
||||
- qcom,sc7180-lpasscorecc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: gcc_lpass_sway clock from GCC
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bi_tcxo
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: lpass core cc register
|
||||
- description: lpass audio cc register
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: lpass_core_cc
|
||||
- const: lpass_audio_cc
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc7180-lpasshm
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
|
||||
clock-controller@63000000 {
|
||||
compatible = "qcom,sc7180-lpasshm";
|
||||
reg = <0x63000000 0x28>;
|
||||
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
|
||||
clock-controller@62d00000 {
|
||||
compatible = "qcom,sc7180-lpasscorecc";
|
||||
reg = <0x62d00000 0x50000>, <0x62780000 0x30000>;
|
||||
reg-names = "lpass_core_cc", "lpass_audio_cc";
|
||||
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "bi_tcxo";
|
||||
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
A revision of this SoC is available: rk3288w. The clock tree is a bit
|
||||
different so another dt-compatible is available. Noticed that it is only
|
||||
setting the difference but there is no automatic revision detection. This
|
||||
should be performed by bootloaders.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3288-cru"
|
||||
- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
|
||||
case of this revision of Rockchip rk3288.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
+3
-1
@@ -1540,6 +1540,7 @@ F: drivers/mmc/host/owl-mmc.c
|
||||
F: drivers/pinctrl/actions/*
|
||||
F: drivers/soc/actions/
|
||||
F: include/dt-bindings/power/owl-*
|
||||
F: include/dt-bindings/reset/actions,*
|
||||
F: include/linux/soc/actions/
|
||||
N: owl
|
||||
|
||||
@@ -8409,8 +8410,9 @@ W: https://github.com/o2genum/ideapad-slidebar
|
||||
F: drivers/input/misc/ideapad_slidebar.c
|
||||
|
||||
IDT VersaClock 5 CLOCK DRIVER
|
||||
M: Marek Vasut <marek.vasut@gmail.com>
|
||||
M: Luca Ceresoli <luca@lucaceresoli.net>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
|
||||
F: drivers/clk/clk-versaclock5.c
|
||||
|
||||
IEEE 802.15.4 SUBSYSTEM
|
||||
|
||||
+1
-1
@@ -50,7 +50,7 @@ source "drivers/clk/versatile/Kconfig"
|
||||
config CLK_HSDK
|
||||
bool "PLL Driver for HSDK platform"
|
||||
depends on OF || COMPILE_TEST
|
||||
depends on IOMEM
|
||||
depends on HAS_IOMEM
|
||||
help
|
||||
This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
|
||||
control.
|
||||
|
||||
@@ -28,6 +28,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
|
||||
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
|
||||
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
|
||||
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
|
||||
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
|
||||
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
|
||||
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
|
||||
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
|
||||
|
||||
@@ -23,8 +23,10 @@
|
||||
#include "owl-gate.h"
|
||||
#include "owl-mux.h"
|
||||
#include "owl-pll.h"
|
||||
#include "owl-reset.h"
|
||||
|
||||
#include <dt-bindings/clock/actions,s500-cmu.h>
|
||||
#include <dt-bindings/reset/actions,s500-reset.h>
|
||||
|
||||
#define CMU_COREPLL (0x0000)
|
||||
#define CMU_DEVPLL (0x0004)
|
||||
@@ -175,6 +177,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT
|
||||
static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
|
||||
|
||||
/* gate clocks */
|
||||
static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
|
||||
static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
|
||||
static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
|
||||
static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
|
||||
static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
|
||||
@@ -183,7 +187,8 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
|
||||
static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
|
||||
|
||||
/* divider clocks */
|
||||
static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
|
||||
static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
|
||||
static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
|
||||
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
|
||||
|
||||
/* factor clocks */
|
||||
@@ -428,6 +433,9 @@ static struct owl_clk_common *s500_clks[] = {
|
||||
&spdif_clk.common,
|
||||
&nand_clk.common,
|
||||
&ecc_clk.common,
|
||||
&apb_clk.common,
|
||||
&dmac_clk.common,
|
||||
&gpio_clk.common,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data s500_hw_clks = {
|
||||
@@ -484,24 +492,103 @@ static struct clk_hw_onecell_data s500_hw_clks = {
|
||||
[CLK_SPDIF] = &spdif_clk.common.hw,
|
||||
[CLK_NAND] = &nand_clk.common.hw,
|
||||
[CLK_ECC] = &ecc_clk.common.hw,
|
||||
[CLK_APB] = &apb_clk.common.hw,
|
||||
[CLK_DMAC] = &dmac_clk.common.hw,
|
||||
[CLK_GPIO] = &gpio_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
};
|
||||
|
||||
static const struct owl_reset_map s500_resets[] = {
|
||||
[RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
|
||||
[RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
|
||||
[RESET_DDR] = { CMU_DEVRST0, BIT(2) },
|
||||
[RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
|
||||
[RESET_SD0] = { CMU_DEVRST0, BIT(4) },
|
||||
[RESET_SD1] = { CMU_DEVRST0, BIT(5) },
|
||||
[RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
|
||||
[RESET_DE] = { CMU_DEVRST0, BIT(7) },
|
||||
[RESET_LCD] = { CMU_DEVRST0, BIT(8) },
|
||||
[RESET_SD2] = { CMU_DEVRST0, BIT(9) },
|
||||
[RESET_DSI] = { CMU_DEVRST0, BIT(10) },
|
||||
[RESET_CSI] = { CMU_DEVRST0, BIT(11) },
|
||||
[RESET_BISP] = { CMU_DEVRST0, BIT(12) },
|
||||
[RESET_KEY] = { CMU_DEVRST0, BIT(14) },
|
||||
[RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
|
||||
[RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
|
||||
[RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
|
||||
[RESET_VDE] = { CMU_DEVRST0, BIT(19) },
|
||||
[RESET_VCE] = { CMU_DEVRST0, BIT(20) },
|
||||
[RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
|
||||
[RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
|
||||
[RESET_LENS] = { CMU_DEVRST0, BIT(26) },
|
||||
[RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
|
||||
[RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
|
||||
[RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
|
||||
[RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
|
||||
[RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
|
||||
[RESET_UART6] = { CMU_DEVRST1, BIT(4) },
|
||||
[RESET_UART0] = { CMU_DEVRST1, BIT(5) },
|
||||
[RESET_UART1] = { CMU_DEVRST1, BIT(6) },
|
||||
[RESET_UART2] = { CMU_DEVRST1, BIT(7) },
|
||||
[RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
|
||||
[RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
|
||||
[RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
|
||||
[RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
|
||||
[RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
|
||||
[RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
|
||||
[RESET_USB3] = { CMU_DEVRST1, BIT(14) },
|
||||
[RESET_UART3] = { CMU_DEVRST1, BIT(15) },
|
||||
[RESET_UART4] = { CMU_DEVRST1, BIT(16) },
|
||||
[RESET_UART5] = { CMU_DEVRST1, BIT(17) },
|
||||
[RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
|
||||
[RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
|
||||
[RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
|
||||
[RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
|
||||
[RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
|
||||
[RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
|
||||
[RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
|
||||
[RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
|
||||
[RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
|
||||
[RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
|
||||
[RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
|
||||
[RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
|
||||
[RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
|
||||
};
|
||||
|
||||
static struct owl_clk_desc s500_clk_desc = {
|
||||
.clks = s500_clks,
|
||||
.num_clks = ARRAY_SIZE(s500_clks),
|
||||
|
||||
.hw_clks = &s500_hw_clks,
|
||||
|
||||
.resets = s500_resets,
|
||||
.num_resets = ARRAY_SIZE(s500_resets),
|
||||
};
|
||||
|
||||
static int s500_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct owl_clk_desc *desc;
|
||||
struct owl_reset *reset;
|
||||
int ret;
|
||||
|
||||
desc = &s500_clk_desc;
|
||||
owl_clk_regmap_init(pdev, desc);
|
||||
|
||||
reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
|
||||
if (!reset)
|
||||
return -ENOMEM;
|
||||
|
||||
reset->rcdev.of_node = pdev->dev.of_node;
|
||||
reset->rcdev.ops = &owl_reset_ops;
|
||||
reset->rcdev.nr_resets = desc->num_resets;
|
||||
reset->reset_map = desc->resets;
|
||||
reset->regmap = desc->regmap;
|
||||
|
||||
ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Failed to register reset controller\n");
|
||||
|
||||
return owl_clk_probe(&pdev->dev, desc->hw_clks);
|
||||
}
|
||||
|
||||
|
||||
@@ -23,3 +23,4 @@ obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
|
||||
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
|
||||
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
|
||||
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
|
||||
obj-$(CONFIG_SOC_SAMA7G5) += sama7g5.o
|
||||
|
||||
@@ -160,7 +160,8 @@ static void __init at91rm9200_pmc_setup(struct device_node *np)
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 4, i,
|
||||
&at91rm9200_programmable_layout);
|
||||
&at91rm9200_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
||||
@@ -436,7 +436,8 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 4, i,
|
||||
&at91rm9200_programmable_layout);
|
||||
&at91rm9200_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
||||
@@ -111,7 +111,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
||||
return;
|
||||
mainxtal_name = of_clk_get_parent_name(np, i);
|
||||
|
||||
regmap = syscon_node_to_regmap(np);
|
||||
regmap = device_node_to_regmap(np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@@ -181,7 +181,8 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np)
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
&at91sam9g45_programmable_layout);
|
||||
&at91sam9g45_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
||||
@@ -124,7 +124,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
||||
return;
|
||||
mainxtal_name = of_clk_get_parent_name(np, i);
|
||||
|
||||
regmap = syscon_node_to_regmap(np);
|
||||
regmap = device_node_to_regmap(np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@@ -199,7 +199,8 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
&at91sam9x5_programmable_layout);
|
||||
&at91sam9x5_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
@@ -222,7 +223,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np)
|
||||
at91sam9n12_periphck[i].n,
|
||||
"masterck",
|
||||
at91sam9n12_periphck[i].id,
|
||||
&range);
|
||||
&range, INT_MIN);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
||||
@@ -137,7 +137,8 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
&at91rm9200_programmable_layout);
|
||||
&at91rm9200_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
||||
@@ -226,7 +226,8 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
||||
|
||||
hw = at91_clk_register_programmable(regmap, name,
|
||||
parent_names, 5, i,
|
||||
&at91sam9x5_programmable_layout);
|
||||
&at91sam9x5_programmable_layout,
|
||||
NULL);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
@@ -257,7 +258,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
||||
at91sam9x5_periphck[i].n,
|
||||
"masterck",
|
||||
at91sam9x5_periphck[i].id,
|
||||
&range);
|
||||
&range, INT_MIN);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
@@ -270,7 +271,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
|
||||
extra_pcks[i].n,
|
||||
"masterck",
|
||||
extra_pcks[i].id,
|
||||
&range);
|
||||
&range, INT_MIN);
|
||||
if (IS_ERR(hw))
|
||||
goto err_free;
|
||||
|
||||
|
||||
@@ -18,18 +18,17 @@
|
||||
|
||||
#define GENERATED_MAX_DIV 255
|
||||
|
||||
#define GCK_INDEX_DT_AUDIO_PLL 5
|
||||
|
||||
struct clk_generated {
|
||||
struct clk_hw hw;
|
||||
struct regmap *regmap;
|
||||
struct clk_range range;
|
||||
spinlock_t *lock;
|
||||
u32 *mux_table;
|
||||
u32 id;
|
||||
u32 gckdiv;
|
||||
const struct clk_pcr_layout *layout;
|
||||
u8 parent_id;
|
||||
bool audio_pll_allowed;
|
||||
int chg_pid;
|
||||
};
|
||||
|
||||
#define to_clk_generated(hw) \
|
||||
@@ -83,7 +82,7 @@ static int clk_generated_is_enabled(struct clk_hw *hw)
|
||||
regmap_read(gck->regmap, gck->layout->offset, &status);
|
||||
spin_unlock_irqrestore(gck->lock, flags);
|
||||
|
||||
return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
|
||||
return !!(status & AT91_PMC_PCR_GCKEN);
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
@@ -109,7 +108,7 @@ static void clk_generated_best_diff(struct clk_rate_request *req,
|
||||
tmp_rate = parent_rate / div;
|
||||
tmp_diff = abs(req->rate - tmp_rate);
|
||||
|
||||
if (*best_diff < 0 || *best_diff > tmp_diff) {
|
||||
if (*best_diff < 0 || *best_diff >= tmp_diff) {
|
||||
*best_rate = tmp_rate;
|
||||
*best_diff = tmp_diff;
|
||||
req->best_parent_rate = parent_rate;
|
||||
@@ -129,7 +128,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
|
||||
int i;
|
||||
u32 div;
|
||||
|
||||
for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
|
||||
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
|
||||
if (gck->chg_pid == i)
|
||||
continue;
|
||||
|
||||
parent = clk_hw_get_parent_by_index(hw, i);
|
||||
if (!parent)
|
||||
continue;
|
||||
@@ -161,16 +163,17 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
|
||||
* that the only clks able to modify gck rate are those of audio IPs.
|
||||
*/
|
||||
|
||||
if (!gck->audio_pll_allowed)
|
||||
if (gck->chg_pid < 0)
|
||||
goto end;
|
||||
|
||||
parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
|
||||
parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
|
||||
if (!parent)
|
||||
goto end;
|
||||
|
||||
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
|
||||
req_parent.rate = req->rate * div;
|
||||
__clk_determine_rate(parent, &req_parent);
|
||||
if (__clk_determine_rate(parent, &req_parent))
|
||||
continue;
|
||||
clk_generated_best_diff(req, parent, req_parent.rate, div,
|
||||
&best_diff, &best_rate);
|
||||
|
||||
@@ -184,8 +187,8 @@ end:
|
||||
__clk_get_name((req->best_parent_hw)->clk),
|
||||
req->best_parent_rate);
|
||||
|
||||
if (best_rate < 0)
|
||||
return best_rate;
|
||||
if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
|
||||
return -EINVAL;
|
||||
|
||||
req->rate = best_rate;
|
||||
return 0;
|
||||
@@ -199,7 +202,11 @@ static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
|
||||
if (index >= clk_hw_get_num_parents(hw))
|
||||
return -EINVAL;
|
||||
|
||||
gck->parent_id = index;
|
||||
if (gck->mux_table)
|
||||
gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
|
||||
else
|
||||
gck->parent_id = index;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -271,8 +278,9 @@ struct clk_hw * __init
|
||||
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
|
||||
const struct clk_pcr_layout *layout,
|
||||
const char *name, const char **parent_names,
|
||||
u8 num_parents, u8 id, bool pll_audio,
|
||||
const struct clk_range *range)
|
||||
u32 *mux_table, u8 num_parents, u8 id,
|
||||
const struct clk_range *range,
|
||||
int chg_pid)
|
||||
{
|
||||
struct clk_generated *gck;
|
||||
struct clk_init_data init;
|
||||
@@ -287,16 +295,18 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
|
||||
init.ops = &generated_ops;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
||||
CLK_SET_RATE_PARENT;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
|
||||
if (chg_pid >= 0)
|
||||
init.flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
gck->id = id;
|
||||
gck->hw.init = &init;
|
||||
gck->regmap = regmap;
|
||||
gck->lock = lock;
|
||||
gck->range = *range;
|
||||
gck->audio_pll_allowed = pll_audio;
|
||||
gck->chg_pid = chg_pid;
|
||||
gck->layout = layout;
|
||||
gck->mux_table = mux_table;
|
||||
|
||||
clk_generated_startup(gck);
|
||||
hw = &gck->hw;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user