mirror of
https://github.com/suyu-emu/horinux.git
synced 2026-09-21 14:15:21 -07:00
Merge tag '64bit-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC 64-bit changes and additions from Olof Johansson: "The 64-bit set of updates this release cycle adds support for three new platforms: - Samsunc Exynos 7 - Freescale LS2085a - Mediatek MT8173 For all these, the changes mostly consititude additions of DT contents, but also some Kconfig entries to allow dependency/selection of drivers per-platform, etc" * tag '64bit-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: Kconfig: clean up two no-op Kconfig options from CONFIG_ARCH_TEGRA* arm64: Fix sort of platform Kconfig entries arm64: Add support for FSL's LS2085A SoC in Kconfig and defconfig arm64: Add DTS support for FSL's LS2085A SoC arm64: mediatek: Add MT8173 SoC Kconfig and defconfig arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile Document: DT: Add bindings for mediatek MT8173 SoC Platform arm64: Add Tegra132 support arm64: Enable ARMv8 based exynos7 SoC support arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on exynos7 arm64: dts: Add PMU DT node for exynos7 SoC arm64: dts: Add initial pinctrl support to exynos7 arm64: dts: Add initial device tree support for exynos7
This commit is contained in:
Linus Torvalds
@@ -9,6 +9,7 @@ compatible: Must contain one of
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"mediatek,mt6592"
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"mediatek,mt8127"
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"mediatek,mt8135"
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"mediatek,mt8173"
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Supported boards:
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@@ -25,3 +26,6 @@ Supported boards:
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- MTK mt8135 tablet EVB:
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Required root node properties:
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- compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
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- MTK mt8173 tablet EVB:
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Required root node properties:
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- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
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@@ -5,6 +5,7 @@ interrupt.
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Required properties:
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- compatible: should be one of:
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"mediatek,mt8173-sysirq"
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"mediatek,mt8135-sysirq"
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"mediatek,mt8127-sysirq"
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"mediatek,mt6592-sysirq"
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@@ -10,6 +10,7 @@ Properties:
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- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
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- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
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- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
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- "samsung,exynos7-pmu" - for Exynos7 SoC.
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second value must be always "syscon".
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- reg : offset and length of the register set.
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@@ -4,9 +4,11 @@ Required properties:
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- compatible should contain:
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* "mediatek,mt8135-uart" for MT8135 compatible UARTS
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* "mediatek,mt8127-uart" for MT8127 compatible UARTS
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* "mediatek,mt8173-uart" for MT8173 compatible UARTS
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* "mediatek,mt6589-uart" for MT6589 compatible UARTS
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* "mediatek,mt6582-uart" for MT6582 compatible UARTS
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* "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)
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* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
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MT6577)
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- reg: The base address of the UART register bank.
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@@ -149,11 +149,65 @@ source "kernel/Kconfig.freezer"
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menu "Platform selection"
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config ARCH_EXYNOS
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bool
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help
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This enables support for Samsung Exynos SoC family
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config ARCH_EXYNOS7
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bool "ARMv8 based Samsung Exynos7"
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select ARCH_EXYNOS
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select COMMON_CLK_SAMSUNG
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select PINCTRL
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select PINCTRL_EXYNOS
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help
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This enables support for Samsung Exynos7 SoC family
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config ARCH_FSL_LS2085A
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bool "Freescale LS2085A SOC"
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help
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This enables support for Freescale LS2085A SOC.
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config ARCH_MEDIATEK
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bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
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select ARM_GIC
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help
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Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_TEGRA
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bool "NVIDIA Tegra SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select CLKSRC_OF
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_TEGRA_132_SOC
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bool "NVIDIA Tegra132 SoC"
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depends on ARCH_TEGRA
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select PINCTRL_TEGRA124
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select USB_ULPI if USB_PHY
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select USB_ULPI_VIEWPORT if USB_PHY
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help
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Enable support for NVIDIA Tegra132 SoC, based on the Denver
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ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
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but contains an NVIDIA Denver CPU complex in place of
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Tegra124's "4+1" Cortex-A15 CPU complex.
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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@@ -2,5 +2,8 @@ dts-dirs += amd
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dts-dirs += apm
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dts-dirs += arm
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dts-dirs += cavium
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dts-dirs += exynos
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dts-dirs += freescale
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dts-dirs += mediatek
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subdir-y := $(dts-dirs)
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@@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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@@ -0,0 +1,84 @@
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/*
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* SAMSUNG Exynos7 Espresso board device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "exynos7.dtsi"
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/ {
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model = "Samsung Exynos7 Espresso board based on EXYNOS7";
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compatible = "samsung,exynos7-espresso", "samsung,exynos7";
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aliases {
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serial0 = &serial_2;
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mshc0 = &mmc_0;
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mshc2 = &mmc_2;
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};
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chosen {
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linux,stdout-path = &serial_2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0xC0000000>;
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};
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};
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&fin_pll {
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clock-frequency = <24000000>;
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};
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&serial_2 {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&adc {
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status = "okay";
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};
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&mmc_0 {
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status = "okay";
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num-slots = <1>;
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broken-cd;
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cap-mmc-highspeed;
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non-removable;
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card-detect-delay = <200>;
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clock-frequency = <800000000>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <0 4>;
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samsung,dw-mshc-ddr-timing = <0 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
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bus-width = <8>;
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};
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&mmc_2 {
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status = "okay";
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num-slots = <1>;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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clock-frequency = <400000000>;
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
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bus-width = <4>;
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disable-wp;
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};
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_FSL_LS2085A) += fsl-ls2085a-simu.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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@@ -0,0 +1,65 @@
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/*
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* Device Tree file for Freescale LS2085a software Simulator model
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||||
*
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||||
* Copyright (C) 2014, Freescale Semiconductor
|
||||
*
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||||
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public
|
||||
* License along with this library; if not, write to the Free
|
||||
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl-ls2085a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale Layerscape 2085a software Simulator model";
|
||||
compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
|
||||
|
||||
ethernet@2210000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <0x0 0x2210000 0x0 0x100>;
|
||||
interrupts = <0 58 0x1>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,163 @@
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-2085A family SoC.
|
||||
*
|
||||
* Copyright (C) 2014, Freescale Semiconductor
|
||||
*
|
||||
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public
|
||||
* License along with this library; if not, write to the Free
|
||||
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls2085a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* We expect the enable-method for cpu's to be "psci", but this
|
||||
* is dependent on the SoC FW, which will fill this in.
|
||||
*
|
||||
* Currently supported enable-method is psci v0.2
|
||||
*/
|
||||
|
||||
/* We have 4 clusters having 2 Cortex-A57 cores each */
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
};
|
||||
|
||||
cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
cpu@201 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x201>;
|
||||
};
|
||||
|
||||
cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x300>;
|
||||
};
|
||||
|
||||
cpu@301 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x301>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0 0x80000000>;
|
||||
/* DRAM space - 1, size : 2 GB DRAM */
|
||||
};
|
||||
|
||||
gic: interrupt-controller@6000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
|
||||
<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <1 9 0x4>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
|
||||
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
|
||||
<1 11 0x8>, /* Virtual PPI, active-low */
|
||||
<1 10 0x8>; /* Hypervisor PPI, active-low */
|
||||
};
|
||||
|
||||
serial0: serial@21c0500 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21c0500 0x0 0x100>;
|
||||
clock-frequency = <0>; /* Updated by bootloader */
|
||||
interrupts = <0 32 0x1>; /* edge triggered */
|
||||
};
|
||||
|
||||
serial1: serial@21c0600 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21c0600 0x0 0x100>;
|
||||
clock-frequency = <0>; /* Updated by bootloader */
|
||||
interrupts = <0 32 0x1>; /* edge triggered */
|
||||
};
|
||||
|
||||
fsl_mc: fsl-mc@80c000000 {
|
||||
compatible = "fsl,qoriq-mc";
|
||||
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
||||
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,5 @@
|
||||
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Eddie Huang <eddie.huang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8173.dtsi"
|
||||
|
||||
/ {
|
||||
model = "mediatek,mt8173-evb";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (c) 2014 MediaTek Inc.
|
||||
* Author: Eddie Huang <eddie.huang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt8173";
|
||||
interrupt-parent = <&sysirq>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
cpu_suspend = <0x84000001>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0x84000003>;
|
||||
};
|
||||
|
||||
uart_clk: dummy26m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
sysirq: intpol-controller@10200620 {
|
||||
compatible = "mediatek,mt8173-sysirq",
|
||||
"mediatek,mt6577-sysirq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10200620 0 0x20>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10220000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x10221000 0 0x1000>,
|
||||
<0 0x10222000 0 0x2000>,
|
||||
<0 0x10224000 0 0x2000>,
|
||||
<0 0x10226000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt8173-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x400>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11003000 {
|
||||
compatible = "mediatek,mt8173-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x400>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,mt8173-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x400>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@11005000 {
|
||||
compatible = "mediatek,mt8173-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11005000 0 0x400>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
@@ -31,6 +31,8 @@ CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_ARCH_FSL_LS2085A=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_ARCH_THUNDER=y
|
||||
CONFIG_ARCH_VEXPRESS=y
|
||||
CONFIG_ARCH_XGENE=y
|
||||
@@ -88,6 +90,7 @@ CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_MT6577=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
|
||||
Reference in New Issue
Block a user