mirror of
https://github.com/suyu-emu/horinux.git
synced 2026-09-21 14:15:21 -07:00
Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer changes from Ingo Molnar: "Various clocksource driver updates: extend the core with memory mapped hardware (mmio) support and add new (ARM) Moxart SoC and sun4i hardware support" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) clocksource: arch_timer: Add support for memory mapped timers clocksource: arch_timer: Push the read/write wrappers deeper Documentation: Add memory mapped ARM architected timer binding clocksource: arch_timer: Pass clock event to set_mode callback clocksource: arch_timer: Make register accessors less error-prone ARM: clocksource: moxart: documentation: Update device tree bindings document ARM: clocksource: moxart: Add bitops.h include ARM: clocksource: moxart: documentation: Fix device tree bindings document ARM: clocksource: Add support for MOXA ART SoCs clocksource: cadence_ttc: Reuse clocksource as sched_clock clocksource: cadence_ttc: Remove unused header clocksource: sun4i: Fix bug when switching from periodic to oneshot modes clocksource: sun4i: Cleanup parent clock setup clocksource: sun4i: Remove TIMER_SCAL variable clocksource: sun4i: Factor out some timer code clocksource: sun4i: Fix the next event code clocksource: sun4i: Don't forget to enable the clock we use clocksource: sun4i: Add clocksource and sched clock drivers clocksource: sun4i: rename AUTORELOAD define to RELOAD clocksource: sun4i: Wrap macros arguments in parenthesis ...
This commit is contained in:
Linus Torvalds
@@ -1,10 +1,14 @@
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* ARM architected timer
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ARM cores may have a per-core architected timer, which provides per-cpu timers.
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ARM cores may have a per-core architected timer, which provides per-cpu timers,
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or a memory mapped architected timer, which provides up to 8 frames with a
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physical and optional virtual timer per frame.
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The timer is attached to a GIC to deliver its per-processor interrupts.
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The per-core architected timer is attached to a GIC to deliver its
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per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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to deliver its interrupts via SPIs.
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** Timer node properties:
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** CP15 Timer node properties:
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- compatible : Should at least contain one of
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"arm,armv7-timer"
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@@ -26,3 +30,52 @@ Example:
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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};
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** Memory mapped timer node properties:
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- compatible : Should at least contain "arm,armv7-timer-mem".
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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- reg : The control frame base address.
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Note that #address-cells, #size-cells, and ranges shall be present to ensure
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the CPU can address a frame's registers.
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A timer node has up to 8 frame sub-nodes, each with the following properties:
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- frame-number: 0 to 7.
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- interrupts : Interrupt list for physical and virtual timers in that order.
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The virtual timer interrupt is optional.
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- reg : The first and second view base addresses in that order. The second view
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base address is optional.
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- status : "disabled" indicates the frame is not available for use. Optional.
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Example:
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timer@f0000000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0xf0000000 0x1000>;
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clock-frequency = <50000000>;
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frame@f0001000 {
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frame-number = <0>
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interrupts = <0 13 0x8>,
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<0 14 0x8>;
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reg = <0xf0001000 0x1000>,
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<0xf0002000 0x1000>;
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};
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frame@f0003000 {
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frame-number = <1>
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interrupts = <0 15 0x8>;
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reg = <0xf0003000 0x1000>;
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status = "disabled";
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};
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};
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@@ -0,0 +1,17 @@
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MOXA ART timer
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Required properties:
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- compatible : Must be "moxa,moxart-timer"
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- reg : Should contain registers location and length
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- interrupts : Should contain the timer interrupt number
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- clocks : Should contain phandle for the clock that drives the counter
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Example:
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timer: timer@98400000 {
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compatible = "moxa,moxart-timer";
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reg = <0x98400000 0x42>;
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interrupts = <19 1>;
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clocks = <&coreclk>;
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};
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+8
-2
@@ -2125,6 +2125,13 @@ M: Russell King <linux@arm.linux.org.uk>
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S: Maintained
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F: include/linux/clk.h
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CLOCKSOURCE, CLOCKEVENT DRIVERS
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M: Daniel Lezcano <daniel.lezcano@linaro.org>
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M: Thomas Gleixner <tglx@linutronix.de>
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
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S: Supported
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F: drivers/clocksource
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CISCO FCOE HBA DRIVER
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M: Hiral Patel <hiralpat@cisco.com>
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M: Suma Ramars <sramars@cisco.com>
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@@ -7156,7 +7163,7 @@ S: Maintained
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F: include/linux/mmc/dw_mmc.h
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F: drivers/mmc/host/dw_mmc*
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TIMEKEEPING, NTP
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TIMEKEEPING, CLOCKSOURCE CORE, NTP
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M: John Stultz <john.stultz@linaro.org>
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M: Thomas Gleixner <tglx@linutronix.de>
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/core
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@@ -7169,7 +7176,6 @@ F: include/uapi/linux/timex.h
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F: kernel/time/clocksource.c
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F: kernel/time/time*.c
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F: kernel/time/ntp.c
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F: drivers/clocksource
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TLG2300 VIDEO4LINUX-2 DRIVER
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M: Huang Shijie <shijie8@gmail.com>
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@@ -17,7 +17,8 @@ int arch_timer_arch_init(void);
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* nicely work out which register we want, and chuck away the rest of
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* the code. At least it does so with a recent GCC (4.6.3).
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*/
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static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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@@ -28,9 +29,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
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asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
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break;
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}
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}
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if (access == ARCH_TIMER_VIRT_ACCESS) {
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
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@@ -44,7 +43,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val
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isb();
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}
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static inline u32 arch_timer_reg_read(const int access, const int reg)
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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u32 val = 0;
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@@ -57,9 +57,7 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
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asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
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break;
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}
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}
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if (access == ARCH_TIMER_VIRT_ACCESS) {
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
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@@ -26,7 +26,13 @@
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#include <clocksource/arm_arch_timer.h>
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static inline void arch_timer_reg_write(int access, int reg, u32 val)
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code.
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*/
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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@@ -36,8 +42,6 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val)
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case ARCH_TIMER_REG_TVAL:
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asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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@@ -47,17 +51,14 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val)
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case ARCH_TIMER_REG_TVAL:
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asm volatile("msr cntv_tval_el0, %0" : : "r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else {
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BUILD_BUG();
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}
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isb();
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}
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static inline u32 arch_timer_reg_read(int access, int reg)
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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u32 val;
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@@ -69,8 +70,6 @@ static inline u32 arch_timer_reg_read(int access, int reg)
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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@@ -80,11 +79,7 @@ static inline u32 arch_timer_reg_read(int access, int reg)
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else {
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BUILD_BUG();
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}
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return val;
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@@ -18,6 +18,7 @@ obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
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obj-$(CONFIG_ORION_TIMER) += time-orion.o
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obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
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obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
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obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
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obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
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obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
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obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
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File diff suppressed because it is too large
Load Diff
@@ -21,7 +21,7 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/sched_clock.h>
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/*
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* This driver configures the 2 16-bit count-up timers as follows:
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@@ -95,6 +95,8 @@ struct ttc_timer_clockevent {
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#define to_ttc_timer_clkevent(x) \
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container_of(x, struct ttc_timer_clockevent, ce)
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static void __iomem *ttc_sched_clock_val_reg;
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/**
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* ttc_set_interval - Set the timer interval value
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*
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@@ -156,6 +158,11 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
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TTC_COUNT_VAL_OFFSET);
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}
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static u32 notrace ttc_sched_clock_read(void)
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{
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return __raw_readl(ttc_sched_clock_val_reg);
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}
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/**
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* ttc_set_next_event - Sets the time interval for next event
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*
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@@ -297,6 +304,10 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
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kfree(ttccs);
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return;
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}
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ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
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setup_sched_clock(ttc_sched_clock_read, 16,
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clk_get_rate(ttccs->ttc.clk) / PRESCALE);
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}
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static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
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|
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@@ -0,0 +1,165 @@
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/*
|
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* MOXA ART SoCs timer handling.
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*
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* Copyright (C) 2013 Jonas Jensen
|
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*
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* Jonas Jensen <jonas.jensen@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
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* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
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|
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#include <linux/clk.h>
|
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#include <linux/clockchips.h>
|
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#include <linux/interrupt.h>
|
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#include <linux/irq.h>
|
||||
#include <linux/irqreturn.h>
|
||||
#include <linux/of.h>
|
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#include <linux/of_address.h>
|
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#include <linux/of_irq.h>
|
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#include <linux/io.h>
|
||||
#include <linux/clocksource.h>
|
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#include <linux/bitops.h>
|
||||
|
||||
#define TIMER1_BASE 0x00
|
||||
#define TIMER2_BASE 0x10
|
||||
#define TIMER3_BASE 0x20
|
||||
|
||||
#define REG_COUNT 0x0 /* writable */
|
||||
#define REG_LOAD 0x4
|
||||
#define REG_MATCH1 0x8
|
||||
#define REG_MATCH2 0xC
|
||||
|
||||
#define TIMER_CR 0x30
|
||||
#define TIMER_INTR_STATE 0x34
|
||||
#define TIMER_INTR_MASK 0x38
|
||||
|
||||
/*
|
||||
* TIMER_CR flags:
|
||||
*
|
||||
* TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK
|
||||
* TIMEREG_CR_*_INT overflow interrupt enable bit
|
||||
*/
|
||||
#define TIMEREG_CR_1_ENABLE BIT(0)
|
||||
#define TIMEREG_CR_1_CLOCK BIT(1)
|
||||
#define TIMEREG_CR_1_INT BIT(2)
|
||||
#define TIMEREG_CR_2_ENABLE BIT(3)
|
||||
#define TIMEREG_CR_2_CLOCK BIT(4)
|
||||
#define TIMEREG_CR_2_INT BIT(5)
|
||||
#define TIMEREG_CR_3_ENABLE BIT(6)
|
||||
#define TIMEREG_CR_3_CLOCK BIT(7)
|
||||
#define TIMEREG_CR_3_INT BIT(8)
|
||||
#define TIMEREG_CR_COUNT_UP BIT(9)
|
||||
|
||||
#define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE)
|
||||
#define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE)
|
||||
|
||||
static void __iomem *base;
|
||||
static unsigned int clock_count_per_tick;
|
||||
|
||||
static void moxart_clkevt_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
writel(TIMER1_DISABLE, base + TIMER_CR);
|
||||
writel(~0, base + TIMER1_BASE + REG_LOAD);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
|
||||
writel(TIMER1_ENABLE, base + TIMER_CR);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
default:
|
||||
writel(TIMER1_DISABLE, base + TIMER_CR);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int moxart_clkevt_next_event(unsigned long cycles,
|
||||
struct clock_event_device *unused)
|
||||
{
|
||||
u32 u;
|
||||
|
||||
writel(TIMER1_DISABLE, base + TIMER_CR);
|
||||
|
||||
u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
|
||||
writel(u, base + TIMER1_BASE + REG_MATCH1);
|
||||
|
||||
writel(TIMER1_ENABLE, base + TIMER_CR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clock_event_device moxart_clockevent = {
|
||||
.name = "moxart_timer",
|
||||
.rating = 200,
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = moxart_clkevt_mode,
|
||||
.set_next_event = moxart_clkevt_next_event,
|
||||
};
|
||||
|
||||
static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = dev_id;
|
||||
evt->event_handler(evt);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction moxart_timer_irq = {
|
||||
.name = "moxart-timer",
|
||||
.flags = IRQF_TIMER,
|
||||
.handler = moxart_timer_interrupt,
|
||||
.dev_id = &moxart_clockevent,
|
||||
};
|
||||
|
||||
static void __init moxart_timer_init(struct device_node *node)
|
||||
{
|
||||
int ret, irq;
|
||||
unsigned long pclk;
|
||||
struct clk *clk;
|
||||
|
||||
base = of_iomap(node, 0);
|
||||
if (!base)
|
||||
panic("%s: of_iomap failed\n", node->full_name);
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (irq <= 0)
|
||||
panic("%s: irq_of_parse_and_map failed\n", node->full_name);
|
||||
|
||||
ret = setup_irq(irq, &moxart_timer_irq);
|
||||
if (ret)
|
||||
panic("%s: setup_irq failed\n", node->full_name);
|
||||
|
||||
clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(clk))
|
||||
panic("%s: of_clk_get failed\n", node->full_name);
|
||||
|
||||
pclk = clk_get_rate(clk);
|
||||
|
||||
if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT,
|
||||
"moxart_timer", pclk, 200, 32,
|
||||
clocksource_mmio_readl_down))
|
||||
panic("%s: clocksource_mmio_init failed\n", node->full_name);
|
||||
|
||||
clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
|
||||
|
||||
writel(~0, base + TIMER2_BASE + REG_LOAD);
|
||||
writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR);
|
||||
|
||||
moxart_clockevent.cpumask = cpumask_of(0);
|
||||
moxart_clockevent.irq = irq;
|
||||
|
||||
/*
|
||||
* documentation is not publicly available:
|
||||
* min_delta / max_delta obtained by trial-and-error,
|
||||
* max_delta 0xfffffffe should be ok because count
|
||||
* register size is u32
|
||||
*/
|
||||
clockevents_config_and_register(&moxart_clockevent, pclk,
|
||||
0x4, 0xfffffffe);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);
|
||||
@@ -19,42 +19,83 @@
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqreturn.h>
|
||||
#include <linux/sched_clock.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#define TIMER_IRQ_EN_REG 0x00
|
||||
#define TIMER_IRQ_EN(val) (1 << val)
|
||||
#define TIMER_IRQ_EN(val) BIT(val)
|
||||
#define TIMER_IRQ_ST_REG 0x04
|
||||
#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
|
||||
#define TIMER_CTL_ENABLE (1 << 0)
|
||||
#define TIMER_CTL_AUTORELOAD (1 << 1)
|
||||
#define TIMER_CTL_ONESHOT (1 << 7)
|
||||
#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14)
|
||||
#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
|
||||
|
||||
#define TIMER_SCAL 16
|
||||
#define TIMER_CTL_ENABLE BIT(0)
|
||||
#define TIMER_CTL_RELOAD BIT(1)
|
||||
#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
|
||||
#define TIMER_CTL_CLK_SRC_OSC24M (1)
|
||||
#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
|
||||
#define TIMER_CTL_ONESHOT BIT(7)
|
||||
#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
|
||||
#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
|
||||
|
||||
static void __iomem *timer_base;
|
||||
static u32 ticks_per_jiffy;
|
||||
|
||||
/*
|
||||
* When we disable a timer, we need to wait at least for 2 cycles of
|
||||
* the timer source clock. We will use for that the clocksource timer
|
||||
* that is already setup and runs at the same frequency than the other
|
||||
* timers, and we never will be disabled.
|
||||
*/
|
||||
static void sun4i_clkevt_sync(void)
|
||||
{
|
||||
u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
|
||||
|
||||
while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
static void sun4i_clkevt_time_stop(u8 timer)
|
||||
{
|
||||
u32 val = readl(timer_base + TIMER_CTL_REG(timer));
|
||||
writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
|
||||
sun4i_clkevt_sync();
|
||||
}
|
||||
|
||||
static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
|
||||
{
|
||||
writel(delay, timer_base + TIMER_INTVAL_REG(timer));
|
||||
}
|
||||
|
||||
static void sun4i_clkevt_time_start(u8 timer, bool periodic)
|
||||
{
|
||||
u32 val = readl(timer_base + TIMER_CTL_REG(timer));
|
||||
|
||||
if (periodic)
|
||||
val &= ~TIMER_CTL_ONESHOT;
|
||||
else
|
||||
val |= TIMER_CTL_ONESHOT;
|
||||
|
||||
writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
|
||||
timer_base + TIMER_CTL_REG(timer));
|
||||
}
|
||||
|
||||
static void sun4i_clkevt_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
u32 u = readl(timer_base + TIMER_CTL_REG(0));
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
u &= ~(TIMER_CTL_ONESHOT);
|
||||
writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
|
||||
sun4i_clkevt_time_stop(0);
|
||||
sun4i_clkevt_time_setup(0, ticks_per_jiffy);
|
||||
sun4i_clkevt_time_start(0, true);
|
||||
break;
|
||||
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
|
||||
sun4i_clkevt_time_stop(0);
|
||||
sun4i_clkevt_time_start(0, false);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
default:
|
||||
writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
|
||||
sun4i_clkevt_time_stop(0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -62,10 +103,9 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
|
||||
static int sun4i_clkevt_next_event(unsigned long evt,
|
||||
struct clock_event_device *unused)
|
||||
{
|
||||
u32 u = readl(timer_base + TIMER_CTL_REG(0));
|
||||
writel(evt, timer_base + TIMER_CNTVAL_REG(0));
|
||||
writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
|
||||
timer_base + TIMER_CTL_REG(0));
|
||||
sun4i_clkevt_time_stop(0);
|
||||
sun4i_clkevt_time_setup(0, evt);
|
||||
sun4i_clkevt_time_start(0, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -96,6 +136,11 @@ static struct irqaction sun4i_timer_irq = {
|
||||
.dev_id = &sun4i_clockevent,
|
||||
};
|
||||
|
||||
static u32 sun4i_timer_sched_read(void)
|
||||
{
|
||||
return ~readl(timer_base + TIMER_CNTVAL_REG(1));
|
||||
}
|
||||
|
||||
static void __init sun4i_timer_init(struct device_node *node)
|
||||
{
|
||||
unsigned long rate = 0;
|
||||
@@ -114,22 +159,23 @@ static void __init sun4i_timer_init(struct device_node *node)
|
||||
clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(clk))
|
||||
panic("Can't get timer clock");
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
|
||||
writel(rate / (TIMER_SCAL * HZ),
|
||||
timer_base + TIMER_INTVAL_REG(0));
|
||||
writel(~0, timer_base + TIMER_INTVAL_REG(1));
|
||||
writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
|
||||
TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
|
||||
timer_base + TIMER_CTL_REG(1));
|
||||
|
||||
/* set clock source to HOSC, 16 pre-division */
|
||||
val = readl(timer_base + TIMER_CTL_REG(0));
|
||||
val &= ~(0x07 << 4);
|
||||
val &= ~(0x03 << 2);
|
||||
val |= (4 << 4) | (1 << 2);
|
||||
writel(val, timer_base + TIMER_CTL_REG(0));
|
||||
setup_sched_clock(sun4i_timer_sched_read, 32, rate);
|
||||
clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
|
||||
rate, 300, 32, clocksource_mmio_readl_down);
|
||||
|
||||
/* set mode to auto reload */
|
||||
val = readl(timer_base + TIMER_CTL_REG(0));
|
||||
writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
|
||||
ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
|
||||
|
||||
writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
|
||||
timer_base + TIMER_CTL_REG(0));
|
||||
|
||||
ret = setup_irq(irq, &sun4i_timer_irq);
|
||||
if (ret)
|
||||
@@ -141,8 +187,8 @@ static void __init sun4i_timer_init(struct device_node *node)
|
||||
|
||||
sun4i_clockevent.cpumask = cpumask_of(0);
|
||||
|
||||
clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
|
||||
0x1, 0xff);
|
||||
clockevents_config_and_register(&sun4i_clockevent, rate, 0x1,
|
||||
0xffffffff);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
|
||||
sun4i_timer_init);
|
||||
|
||||
@@ -19,7 +19,7 @@
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/sched_clock.h>
|
||||
#include <linux/sched_clock.h>
|
||||
|
||||
#define TIMER_CTRL 0x00
|
||||
#define TIMER0_EN BIT(0)
|
||||
|
||||
@@ -23,16 +23,20 @@
|
||||
#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
|
||||
#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
|
||||
|
||||
#define ARCH_TIMER_REG_CTRL 0
|
||||
#define ARCH_TIMER_REG_TVAL 1
|
||||
enum arch_timer_reg {
|
||||
ARCH_TIMER_REG_CTRL,
|
||||
ARCH_TIMER_REG_TVAL,
|
||||
};
|
||||
|
||||
#define ARCH_TIMER_PHYS_ACCESS 0
|
||||
#define ARCH_TIMER_VIRT_ACCESS 1
|
||||
#define ARCH_TIMER_MEM_PHYS_ACCESS 2
|
||||
#define ARCH_TIMER_MEM_VIRT_ACCESS 3
|
||||
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER
|
||||
|
||||
extern u32 arch_timer_get_rate(void);
|
||||
extern u64 arch_timer_read_counter(void);
|
||||
extern u64 (*arch_timer_read_counter)(void);
|
||||
extern struct timecounter *arch_timer_get_timecounter(void);
|
||||
|
||||
#else
|
||||
|
||||
Reference in New Issue
Block a user