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Add fpga-xc3s100e and icopyx support

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This commit is contained in:
Philippe Teuwen
2021-08-21 23:45:46 +02:00
parent d56d8f0f65
commit e79fb92074
106 changed files with 4213 additions and 85 deletions
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Makefile
+3 -2
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@@ -123,7 +123,7 @@ nonce2key/%: FORCE
mf_nonce_brute/%: FORCE
$(info [*] MAKE $@)
$(Q)$(MAKE) --no-print-directory -C tools/mf_nonce_brute $(patsubst mf_nonce_brute/%,%,$@) DESTDIR=$(MYDESTDIR)
fpga_compress/%: FORCE
fpga_compress/%: FORCE cleanifplatformchanged
$(info [*] MAKE $@)
$(Q)$(MAKE) --no-print-directory -C tools/fpga_compress $(patsubst fpga_compress/%,%,$@) DESTDIR=$(MYDESTDIR)
bootrom/%: FORCE cleanifplatformchanged
@@ -222,6 +222,7 @@ ifeq ($(PLATFORM_CHANGED),true)
$(Q)$(MAKE) --no-print-directory -C bootrom clean
$(Q)$(MAKE) --no-print-directory -C armsrc clean
$(Q)$(MAKE) --no-print-directory -C recovery clean
$(Q)$(MAKE) --no-print-directory -C tools/fpga_compress clean
$(Q)echo CACHED_PLATFORM=$(PLATFORM) > .Makefile.options.cache
$(Q)echo CACHED_PLATFORM_EXTRAS=$(PLATFORM_EXTRAS) >> .Makefile.options.cache
$(Q)echo CACHED_PLATFORM_DEFS=$(PLATFORM_DEFS) >> .Makefile.options.cache
@@ -252,7 +253,7 @@ style:
# Make sure astyle is installed
@which astyle >/dev/null || ( echo "Please install 'astyle' package first" ; exit 1 )
# Remove spaces & tabs at EOL, add LF at EOF if needed on *.c, *.h, *.cpp. *.lua, *.py, *.pl, Makefile, *.v, pm3
find . \( -not -path "./cov-int/*" -and -not -path "./fpga/xst/*" -and \( -name "*.[ch]" -or \( -name "*.cpp" -and -not -name "*.moc.cpp" \) -or -name "*.lua" -or -name "*.py" -or -name "*.pl" -or -name "Makefile" -or -name "*.v" -or -name "pm3" \) \) \
find . \( -not -path "./cov-int/*" -and -not -path "./fpga*/xst/*" -and \( -name "*.[ch]" -or \( -name "*.cpp" -and -not -name "*.moc.cpp" \) -or -name "*.lua" -or -name "*.py" -or -name "*.pl" -or -name "Makefile" -or -name "*.v" -or -name "pm3" \) \) \
-exec perl -pi -e 's/[ \t]+$$//' {} \; \
-exec sh -c "tail -c1 {} | xxd -p | tail -1 | grep -q -v 0a$$" \; \
-exec sh -c "echo >> {}" \;
armsrc/appmain.c
-16
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@@ -212,11 +212,7 @@ static void MeasureAntennaTuning(void) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER);
SpinDelay(50);
#if defined RDV4
payload.v_hf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
payload.v_hf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
reply_ng(CMD_MEASURE_ANTENNA_TUNING, PM3_SUCCESS, (uint8_t *)&payload, sizeof(payload));
@@ -226,11 +222,7 @@ static void MeasureAntennaTuning(void) {
// Measure HF in milliVolt
static uint16_t MeasureAntennaTuningHfData(void) {
#if defined RDV4
return (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
return (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
}
@@ -610,12 +602,8 @@ void ListenReaderField(uint8_t limit) {
if (limit == HF_ONLY) {
#if defined RDV4
// iceman, useless, since we are measuring readerfield, not our field. My tests shows a max of 20v from a reader.
hf_av = hf_max = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
hf_av = hf_max = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
Dbprintf("HF 13.56MHz Baseline: %dmV", hf_av);
hf_baseline = hf_av;
}
@@ -666,11 +654,7 @@ void ListenReaderField(uint8_t limit) {
LED_B_OFF();
}
#if defined RDV4
hf_av_new = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
hf_av_new = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
// see if there's a significant change
if (ABS(hf_av - hf_av_new) > REPORT_CHANGE) {
Dbprintf("HF 13.56MHz Field Change: %5dmV", hf_av_new);
armsrc/appmain.h
+7 -4
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@@ -18,11 +18,14 @@ extern bool g_hf_field_active;
void hf_field_off(void);
int tearoff_hook(void);
// ADC Vref = 3300mV, and an (10M+1M):1M voltage divider on the HF input can measure voltages up to 36300 mV
#define MAX_ADC_HF_VOLTAGE 36300
#if defined RDV4 || defined ICOPYX
// ADC Vref = 3300mV, and an (10000k+240k):240k voltage divider on the LF input can measure voltages up to 140800 mV
#define MAX_ADC_HF_VOLTAGE 140800
#else
// ADC Vref = 3300mV, and an (10M+1M):1M voltage divider on the HF input can measure voltages up to 36300 mV
#define MAX_ADC_HF_VOLTAGE 36300
#endif
// ADC Vref = 3300mV, (240k-10M):240k voltage divider, 140800 mV
#define MAX_ADC_HF_VOLTAGE_RDV40 140800
// ADC Vref = 3300mV, and an (10000k+240k):240k voltage divider on the LF input can measure voltages up to 140800 mV
#define MAX_ADC_LF_VOLTAGE 140800
extern int ToSendMax;
armsrc/felica.c
+4 -1
View File
@@ -445,8 +445,11 @@ static void iso18092_setup(uint8_t fpga_minor_mode) {
if (g_dbglevel >= DBG_DEBUG) Dbprintf("Start iso18092_setup");
LEDsoff();
#if defined XC3
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
#else
FpgaDownloadAndGo(FPGA_BITSTREAM_HF_FELICA);
#endif
// allocate command receive buffer
BigBuf_free();
BigBuf_Clear_ext(false);
armsrc/fpgaloader.c
+77 -1
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@@ -269,10 +269,11 @@ static void DownloadFPGA_byte(uint8_t w) {
// Download the fpga image starting at current stream position with length FpgaImageLen bytes
static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t compressed_fpga_stream, uint8_t *output_buffer) {
int i = 0;
#if !defined XC3
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
HIGH(GPIO_FPGA_ON); // ensure everything is powered on
#endif
SpinDelay(50);
@@ -285,7 +286,13 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
// PIO controls the following pins
AT91C_BASE_PIOA->PIO_PER =
GPIO_FPGA_NINIT |
#if defined XC3
//3S100E M2 & M3 PIO ENA
GPIO_SPCK |
GPIO_MOSI |
#endif
GPIO_FPGA_DONE;
// Enable pull-ups
AT91C_BASE_PIOA->PIO_PPUER =
GPIO_FPGA_NINIT |
@@ -299,8 +306,19 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
AT91C_BASE_PIOA->PIO_OER =
GPIO_FPGA_NPROGRAM |
GPIO_FPGA_CCLK |
#if defined XC3
//3S100E M2 & M3 OUTPUT ENA
GPIO_SPCK |
GPIO_MOSI |
#endif
GPIO_FPGA_DIN;
#if defined XC3
//3S100E M2 & M3 OUTPUT HIGH
HIGH(GPIO_SPCK);
HIGH(GPIO_MOSI);
#endif
// enter FPGA configuration mode
LOW(GPIO_FPGA_NPROGRAM);
SpinDelay(50);
@@ -319,6 +337,13 @@ static void DownloadFPGA(int bitstream_version, int FpgaImageLen, lz4_streamp_t
return;
}
#if defined XC3
//3S100E M2 & M3 RETURN TO NORMAL
LOW(GPIO_SPCK);
LOW(GPIO_MOSI);
AT91C_BASE_PIOA->PIO_PDR = GPIO_SPCK | GPIO_MOSI;
#endif
for (i = 0; i < FpgaImageLen; i++) {
int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
if (b < 0) {
@@ -396,6 +421,43 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
return result;
}
//----------------------------------------------------------------------------
// Change FPGA image status, if image loaded.
// bitstream_version is your new fpga image version
// return true if can change.
// return false if image is unloaded.
//----------------------------------------------------------------------------
#if defined XC3
static bool FpgaConfCurrentMode(int bitstream_version) {
// fpga "XC3S100E" image merge
// If fpga image is no init
// We need load hf_lf_allinone.bit
if (downloaded_bitstream != 0) {
// test start
// PIO controls the following pins
AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_SWITCH;
// These pins are outputs
AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_SWITCH;
// try to turn off antenna
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
if (bitstream_version == FPGA_BITSTREAM_LF) {
LOW(GPIO_FPGA_SWITCH);
}
else {
HIGH(GPIO_FPGA_SWITCH);
}
// update downloaded_bitstream
downloaded_bitstream = bitstream_version;
// turn off antenna
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
return true;
}
return false;
}
#endif
//----------------------------------------------------------------------------
// Check which FPGA image is currently loaded (if any). If necessary
// decompress and load the correct (HF or LF) image to the FPGA
@@ -408,6 +470,14 @@ void FpgaDownloadAndGo(int bitstream_version) {
return;
}
#if defined XC3
// If we can change image version
// direct return.
if (FpgaConfCurrentMode(bitstream_version)) {
return;
}
#endif
// Send waiting time extension request as this will take a while
send_wtx(1500);
@@ -431,6 +501,12 @@ void FpgaDownloadAndGo(int bitstream_version) {
downloaded_bitstream = bitstream_version;
}
#if defined XC3
// first download fpga image to hf
// we need to change fpga status to hf
FpgaConfCurrentMode(bitstream_version);
#endif
// turn off antenna
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
armsrc/iso14443a.c
-34
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@@ -1972,11 +1972,7 @@ int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *par) {
ADC_MODE_STARTUP_TIME(1) |
ADC_MODE_SAMPLE_HOLD_TIME(15);
#if defined RDV4
AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF_RDV40);
#else
AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
#endif
// start ADC
AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
@@ -2003,35 +1999,6 @@ int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *par) {
++check;
// test if the field exists
#if defined RDV4
if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF_RDV40)) {
analogCnt++;
analogAVG += (AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF_RDV40] & 0x3FF);
AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
if (analogCnt >= 32) {
if ((MAX_ADC_HF_VOLTAGE_RDV40 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
if (timer == 0) {
timer = GetTickCount();
} else {
// 50ms no field --> card to idle state
if (GetTickCountDelta(timer) > 50) {
return 2;
}
}
} else {
timer = 0;
}
analogCnt = 0;
analogAVG = 0;
}
}
#else
if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
analogCnt++;
@@ -2059,7 +2026,6 @@ int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *par) {
analogAVG = 0;
}
}
#endif
// receive and test the miller decoding
if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
armsrc/iso14443b.c
-8
View File
@@ -772,11 +772,7 @@ void SimulateIso14443bTag(uint8_t *pupi) {
// find reader field
if (cardSTATE == SIM_NOFIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
cardSTATE = SIM_IDLE;
LED_A_ON();
@@ -976,11 +972,7 @@ void Simulate_iso14443b_srx_tag(uint8_t *uid) {
// find reader field
if (cardSTATE == SIM_NOFIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
cardSTATE = SIM_IDLE;
LED_A_ON();
armsrc/iso15693.c
-4
View File
@@ -1727,11 +1727,7 @@ void SimTagIso15693(uint8_t *uid) {
// find reader field
if (chip_state == NO_FIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
chip_state = IDLE;
LED_A_ON();
armsrc/mifaresim.c
-4
View File
@@ -543,11 +543,7 @@ void Mifare1ksim(uint16_t flags, uint8_t exitAfterNReads, uint8_t *datain, uint1
// find reader field
if (cardSTATE == MFEMUL_NOFIELD) {
#if defined RDV4
vHf = (MAX_ADC_HF_VOLTAGE_RDV40 * SumAdc(ADC_CHAN_HF_RDV40, 32)) >> 15;
#else
vHf = (MAX_ADC_HF_VOLTAGE * SumAdc(ADC_CHAN_HF, 32)) >> 15;
#endif
if (vHf > MF_MINFIELDV) {
cardSTATE_TO_IDLE();
armsrc/thinfilm.c
-4
View File
@@ -51,11 +51,7 @@ void ReadThinFilm(void) {
static uint16_t FpgaSendQueueDelay;
static uint16_t ReadReaderField(void) {
#if defined RDV4
return AvgAdc(ADC_CHAN_HF_RDV40);
#else
return AvgAdc(ADC_CHAN_HF);
#endif
}
static void CodeThinfilmAsTag(const uint8_t *cmd, uint16_t len) {
common_arm/Makefile.common
+1 -1
View File
@@ -35,7 +35,7 @@ OBJDIR = obj
INCLUDE = -I../include -I../common_arm -I../common_fpga -I../common -I.
# Also search prerequisites in the common directory (for usb.c), the fpga directory (for fpga.bit), and the lz4 directory
VPATH = . ../common_arm ../common ../common/crapto1 ../common/mbedtls ../common/lz4 ../fpga ../armsrc/Standalone
VPATH = . ../common_arm ../common ../common/crapto1 ../common/mbedtls ../common/lz4 ../fpga-$(PLATFORM_FPGA) ../armsrc/Standalone
INCLUDES = ../include/proxmark3_arm.h ../include/at91sam7s512.h ../include/config_gpio.h ../include/pm3_cmd.h
common_arm/Makefile.hal
+12
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@@ -21,6 +21,8 @@ Known definitions:
+--------------------------------------------+
| PM3GENERIC | Proxmark3 generic target |
+--------------------------------------------+
| PM3ICOPYX | iCopy-X with XC3S100E |
+--------------------------------------------+
+============================================+
| PLATFORM_EXTRAS | DESCRIPTION |
@@ -71,15 +73,23 @@ $(HELP_DEFINITIONS)
endef
PLTNAME = Unknown Platform
PLATFORM_FPGA = fpga-undefined
ifeq ($(PLATFORM),PM3RDV4)
PLATFORM_DEFS = -DWITH_SMARTCARD -DWITH_FLASH -DRDV4
PLTNAME = Proxmark3 RDV4
PLATFORM_FPGA = xc2s30
else ifeq ($(PLATFORM),PM3OTHER)
$(warning PLATFORM=PM3OTHER is deprecated, please use PLATFORM=PM3GENERIC)
PLTNAME = Proxmark3 generic target
PLATFORM_FPGA = xc2s30
else ifeq ($(PLATFORM),PM3GENERIC)
PLTNAME = Proxmark3 generic target
PLATFORM_FPGA = xc2s30
else ifeq ($(PLATFORM),PM3ICOPYX)
PLATFORM_DEFS = -DWITH_FLASH -DICOPYX -DXC3
PLTNAME = iCopy-X with XC3S100E
PLATFORM_FPGA = xc3s100e
else
$(error Invalid or empty PLATFORM: $(PLATFORM). $(KNOWN_DEFINITIONS))
@@ -204,6 +214,7 @@ export PLATFORM_EXTRAS
export PLATFORM_EXTRAS_INFO
export PLATFORM_SIZE
export PLTNAME
export PLATFORM_FPGA
export PLATFORM_DEFS
export PLATFORM_DEFS_INFO
export PLATFORM_DEFS_INFO_STANDALONE
@@ -212,6 +223,7 @@ export PLATFORM_CHANGED
$(info ===================================================================)
$(info Platform name: $(PLTNAME))
$(info PLATFORM: $(PLATFORM))
$(info PLATFORM_FPGA: $(PLATFORM_FPGA))
$(info PLATFORM_SIZE: $(PLATFORM_SIZE))
$(info Platform extras: $(PLATFORM_EXTRAS_INFO))
$(info Included options: $(PLATFORM_DEFS_INFO))
common_fpga/fpga.h
+5 -1
View File
@@ -12,7 +12,11 @@
#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(bitparse_fixed_header)
#define FPGA_INTERLEAVE_SIZE 288
#define FPGA_CONFIG_SIZE 42336L // our current fpga_[lh]f.bit files are 42175 bytes. Rounded up to next multiple of FPGA_INTERLEAVE_SIZE
#if defined XC3
#define FPGA_CONFIG_SIZE 72864L // our current fpga_[lh]f.bit files are 72742 bytes. Rounded up to next multiple of FPGA_INTERLEAVE_SIZE
#else
#define FPGA_CONFIG_SIZE 42336L // our current fpga_[lh]f.bit files are 42175 bytes. Rounded up to next multiple of FPGA_INTERLEAVE_SIZE
#endif
#define FPGA_RING_BUFFER_BYTES (1024 * 39)
#define FPGA_TRACE_SIZE 3072
doc/md/Development/Makefile-vs-CMake.md
+1 -1
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@@ -91,7 +91,7 @@ At the moment both are maintained because they don't perfectly overlap yet.
| Feature | Makefile | Remarks |
|-----|---|---|
| Platform choice | `PLATFORM=` | values: `PM3RDV4`, `PM3GENERIC` |
| Platform choice | `PLATFORM=` | values: `PM3RDV4`, `PM3GENERIC`, `PM3ICOPYX` |
| Platform size | `PLATFORM_SIZE=` | values: `256`, `512` |
| Platform extras | `PLATFORM_EXTRAS=` | values: `BTADDON`, `FPC_USART_DEV` |
| Skip LF/HF techs in the firmware | `SKIP_`*`=1` | see `common_arm/Makefile.hal` for a list |
doc/md/Use_of_Proxmark/4_Advanced-compilation-parameters.md
+1
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@@ -45,6 +45,7 @@ Here are the supported values you can assign to `PLATFORM` in `Makefile.platform
|-----------------|--------------------------|
| PM3RDV4 (def) | Proxmark3 RDV4 |
| PM3GENERIC | Proxmark3 generic target |
| PM3ICOPYX | iCopy-X with XC3S100E |
By default `PLATFORM=PM3RDV4`.
fpga/Makefile → fpga-xc2s30/Makefile
View File
fpga/clk_divider.v → fpga-xc2s30/clk_divider.v
View File
fpga/fpga.ucf → fpga-xc2s30/fpga.ucf
View File
fpga/fpga_felica.bit → fpga-xc2s30/fpga_felica.bit
View File
fpga/fpga_felica.v → fpga-xc2s30/fpga_felica.v
View File

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