mirror of
https://github.com/RfidResearchGroup/proxmark3.git
synced 2026-05-12 11:18:11 -07:00
Unified fpga folders
This commit is contained in:
d18c7db
+1
-11
@@ -80,17 +80,7 @@ tools/mfd_aes_brute/mfd_aes_brute
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||||
tools/mfd_aes_brute/mfd_multi_brute
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tools/mfd_aes_brute/brute_key
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||||
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fpga/*
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!fpga/tests
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!fpga/fpga_lf.bit
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!fpga/fpga_hf.bit
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!fpga/*.v
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!fpga/Makefile
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||||
!fpga/fpga.ucf
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!fpga/xst_lf.scr
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!fpga/xst_hf.scr
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!fpga/go.bat
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!fpga/sim.tcl
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fpga/__build*
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# offcial dumps folder
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dumps/*
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||||
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@@ -103,9 +103,6 @@ endif
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# Generic standalone Mode injection of source code
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include Standalone/Makefile.inc
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#the FPGA bitstream files. Note: order matters!
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FPGA_BITSTREAMS = fpga_lf.bit fpga_hf.bit fpga_felica.bit fpga_hf_15.bit
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#the lz4 source files required for decompressing the fpga config at run time
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SRC_LZ4 = lz4.c
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#additional defines required to compile lz4
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+13
-7
@@ -404,16 +404,22 @@ static int bitparse_find_section(int bitstream_version, char section_name, uint3
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/* Four byte length field */
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current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
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current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
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numbytes += 2;
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default: /* Fall through, two byte length field */
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current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
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current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
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numbytes += 4;
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if (current_length > 300*1024) {
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/* section e should never exceed about 300KB, if the length is too big limit it but still send the bitstream just in case */
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current_length = 300*1024;
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}
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break;
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default: /* Two byte length field */
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current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
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current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
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numbytes += 2;
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}
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if (current_name != 'e' && current_length > 255) {
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/* Maybe a parse error */
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break;
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if (current_length > 64) {
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/* if text field is too long, keep it but truncate it */
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current_length = 64;
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}
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}
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if (current_name == section_name) {
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@@ -44,7 +44,7 @@ OBJDIR = obj
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INCLUDE = -I../include -I../common_arm -I../common_fpga -I../common -I.
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# Also search prerequisites in the common directory (for usb.c), the fpga directory (for fpga.bit), and the lz4 directory
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VPATH = . ../common_arm ../common ../common/crapto1 ../common/mbedtls ../common/lz4 ../fpga-$(PLATFORM_FPGA) ../armsrc/Standalone
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VPATH = . ../common_arm ../common ../common/crapto1 ../common/mbedtls ../common/lz4 ../fpga ../armsrc/Standalone
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INCLUDES = ../include/proxmark3_arm.h ../include/at91sam7s512.h ../include/config_gpio.h ../include/pm3_cmd.h
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@@ -92,18 +92,26 @@ PLTNAME = Unknown Platform
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PLATFORM_FPGA = fpga-undefined
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ifeq ($(PLATFORM),PM3RDV4)
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# FPGA bitstream files, the order matters!
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FPGA_BITSTREAMS = fpga_pm3_lf.bit fpga_pm3_hf.bit fpga_pm3_felica.bit fpga_pm3_hf_15.bit
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PLATFORM_DEFS = -DWITH_SMARTCARD -DWITH_FLASH -DRDV4
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PLTNAME = Proxmark3 RDV4
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PLATFORM_FPGA = xc2s30
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RDV4 = yes
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else ifeq ($(PLATFORM),PM3OTHER)
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$(warning PLATFORM=PM3OTHER is deprecated, please use PLATFORM=PM3GENERIC)
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# FPGA bitstream files, the order matters!
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FPGA_BITSTREAMS = fpga_pm3_lf.bit fpga_pm3_hf.bit fpga_pm3_felica.bit fpga_pm3_hf_15.bit
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PLTNAME = Proxmark3 generic target
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PLATFORM_FPGA = xc2s30
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else ifeq ($(PLATFORM),PM3GENERIC)
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# FPGA bitstream files, the order matters!
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FPGA_BITSTREAMS = fpga_pm3_lf.bit fpga_pm3_hf.bit fpga_pm3_felica.bit fpga_pm3_hf_15.bit
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PLTNAME = Proxmark3 generic target
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PLATFORM_FPGA = xc2s30
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else ifeq ($(PLATFORM),PM3ICOPYX)
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# FPGA bitstream files, the order matters - only hf has a bitstream, the other 3 files are 0 bytes
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FPGA_BITSTREAMS = fpga_icopyx_lf.bit fpga_icopyx_hf.bit fpga_icopyx_felica.bit fpga_icopyx_hf_15.bit
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PLATFORM_DEFS = -DWITH_FLASH -DICOPYX -DXC3
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PLTNAME = iCopy-X with XC3S100E
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PLATFORM_FPGA = xc3s100e
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@@ -246,6 +254,7 @@ export PLATFORM_DEFS
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export PLATFORM_DEFS_INFO
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export PLATFORM_DEFS_INFO_STANDALONE
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export PLATFORM_CHANGED
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export FPGA_BITSTREAMS
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$(info ===================================================================)
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$(info Version info: $(shell tools/mkversion.sh --short 2>/dev/null || ../tools/mkversion.sh --short 2>/dev/null))
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@@ -1,60 +0,0 @@
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#
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# FPGA Makefile
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#
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RMDIR = rm -rf
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# rmdir only if dir is empty, tolerate failure
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RMDIR_SOFT = -rmdir
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#
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all: fpga_lf.bit fpga_hf.bit fpga_felica.bit fpga_hf_15.bit
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clean:
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$(Q)$(RM) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp xst_felica.srp xst_hf_15.srp
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$(Q)$(RM) *.map *.ngc *.xrpt *.pcf *.rbt *.bld *.mrp *.ngm *.unroutes *_summary.xml netlist.lst
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$(Q)$(RMDIR) *_auto_* xst
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#fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader.v hi_iso14443a.v hi_sniffer.v hi_flite.v hi_get_trace.v
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||||
fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader.v hi_iso14443a.v hi_sniffer.v hi_get_trace.v
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||||
$(Q)$(RM) $@
|
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$(info [-] XST $@)
|
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$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf.scr
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||||
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fpga_felica.ngc: fpga_felica.v fpga.ucf xst_felica.scr util.v hi_simulate.v hi_reader.v hi_sniffer.v hi_flite.v hi_get_trace.v
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||||
$(Q)$(RM) $@
|
||||
$(info [-] XST $@)
|
||||
$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_felica.scr
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||||
|
||||
fpga_hf_15.ngc: fpga_hf_15.v fpga.ucf xst_hf_15.scr util.v hi_simulate.v hi_reader_15.v hi_sniffer.v hi_get_trace.v
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||||
$(Q)$(RM) $@
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||||
$(info [-] XST $@)
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$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf_15.scr
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||||
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fpga_lf.ngc: fpga_lf.v fpga.ucf xst_lf.scr util.v clk_divider.v lo_edge_detect.v lo_read.v lo_passthru.v lp20khz_1MSa_iir_filter.v min_max_tracker.v lf_edge_detect.v
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||||
$(Q)$(RM) $@
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||||
$(info [-] XST $@)
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$(Q)$(XILINX_TOOLS_PREFIX)xst -ifn xst_lf.scr
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||||
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||||
%.ngd: %.ngc
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||||
$(Q)$(RM) $@
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$(info [-] NGD $@)
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$(Q)$(XILINX_TOOLS_PREFIX)ngdbuild -aul -p xc2s30-5-vq100 -nt timestamp -uc fpga.ucf $< $@
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||||
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||||
%.ncd: %.ngd
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||||
$(Q)$(RM) $@
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||||
$(info [-] MAP $@)
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||||
$(Q)$(XILINX_TOOLS_PREFIX)map -p xc2s30-5-vq100 $<
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||||
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||||
%-placed.ncd: %.ncd
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||||
$(Q)$(RM) $@
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||||
$(info [-] PAR $@)
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$(Q)$(XILINX_TOOLS_PREFIX)par $< $@
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%.bit: %-placed.ncd
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$(Q)$(RM) $@ $*.drc $*.rbt
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$(info [=] BITGEN $@)
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$(Q)$(XILINX_TOOLS_PREFIX)bitgen $< $@
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||||
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.PHONY: all clean help
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help:
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@echo Possible targets:
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@echo + all - Make fpga.bit, the FPGA bitstream
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@echo + clean - Clean intermediate files, does not clean fpga.bit
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@@ -1,54 +0,0 @@
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# See the schematic for the pin assignment.
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NET "adc_d<0>" LOC = "P62" ;
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NET "adc_d<1>" LOC = "P60" ;
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NET "adc_d<2>" LOC = "P58" ;
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NET "adc_d<3>" LOC = "P57" ;
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||||
NET "adc_d<4>" LOC = "P56" ;
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NET "adc_d<5>" LOC = "P55" ;
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NET "adc_d<6>" LOC = "P54" ;
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NET "adc_d<7>" LOC = "P53" ;
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||||
#NET "cross_hi" LOC = "P88" ;
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||||
#NET "miso" LOC = "P40" ;
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||||
#PACE: Start of Constraints generated by PACE
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||||
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||||
#PACE: Start of PACE I/O Pin Assignments
|
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NET "adc_clk" LOC = "P46" ;
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NET "adc_noe" LOC = "P47" ;
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||||
NET "ck_1356meg" LOC = "P91" ;
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||||
NET "ck_1356megb" LOC = "P93" ;
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||||
NET "cross_lo" LOC = "P87" ;
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||||
NET "dbg" LOC = "P22" ;
|
||||
NET "mosi" LOC = "P43" ;
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||||
NET "ncs" LOC = "P44" ;
|
||||
NET "pck0" LOC = "P36" ;
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||||
NET "pwr_hi" LOC = "P80" ;
|
||||
NET "pwr_lo" LOC = "P81" ;
|
||||
NET "pwr_oe1" LOC = "P82" ;
|
||||
NET "pwr_oe2" LOC = "P83" ;
|
||||
NET "pwr_oe3" LOC = "P84" ;
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||||
NET "pwr_oe4" LOC = "P86" ;
|
||||
NET "spck" LOC = "P39" ;
|
||||
NET "ssp_clk" LOC = "P71" ;
|
||||
NET "ssp_din" LOC = "P32" ;
|
||||
NET "ssp_dout" LOC = "P34" ;
|
||||
NET "ssp_frame" LOC = "P31" ;
|
||||
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
|
||||
# definition of Clock nets:
|
||||
NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
|
||||
NET "ck_1356megb" TNM_NET = "clk_net_1356b" ;
|
||||
NET "pck0" TNM_NET = "clk_net_pck0" ;
|
||||
NET "spck" TNM_NET = "clk_net_spck" ;
|
||||
|
||||
# Timing specs of clock nets:
|
||||
TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
|
||||
TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
|
||||
TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
|
||||
TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;
|
||||
|
||||
Binary file not shown.
@@ -1,240 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// See LICENSE.txt for the text of the license.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
|
||||
// and the ARM. In the low-frequency modes it passes the data straight
|
||||
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
|
||||
// frequency modes, the FPGA might perform some demodulation first, to
|
||||
// reduce the amount of data that we must send to the ARM.
|
||||
//
|
||||
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
|
||||
// could be improved.
|
||||
//
|
||||
// Jonathan Westhues, March 2006
|
||||
//
|
||||
// Added ISO14443-A support
|
||||
//
|
||||
|
||||
|
||||
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
|
||||
// Note: the definitions here are without shifts
|
||||
|
||||
// Commands:
|
||||
`define FPGA_CMD_SET_CONFREG 1
|
||||
`define FPGA_CMD_TRACE_ENABLE 2
|
||||
|
||||
// Major modes:
|
||||
`define FPGA_MAJOR_MODE_HF_READER 0
|
||||
`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
|
||||
`define FPGA_MAJOR_MODE_HF_ISO14443A 2
|
||||
`define FPGA_MAJOR_MODE_HF_SNIFF 3
|
||||
`define FPGA_MAJOR_MODE_HF_ISO18092 4
|
||||
`define FPGA_MAJOR_MODE_HF_GET_TRACE 5
|
||||
`define FPGA_MAJOR_MODE_OFF 7
|
||||
|
||||
// Options for the generic HF reader
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
|
||||
`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
|
||||
`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
|
||||
`define FPGA_HF_READER_MODE_SNIFF_IQ 5
|
||||
`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
|
||||
`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
|
||||
`define FPGA_HF_READER_MODE_SEND_JAM 8
|
||||
|
||||
`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
|
||||
`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
|
||||
`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
|
||||
|
||||
// Options for the HF simulated tag, how to modulate
|
||||
`define FPGA_HF_SIMULATOR_NO_MODULATION 0
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_212K 2
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_424K 4
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
|
||||
|
||||
// Options for ISO14443A
|
||||
`define FPGA_HF_ISO14443A_SNIFFER 0
|
||||
`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
|
||||
`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
|
||||
`define FPGA_HF_ISO14443A_READER_LISTEN 3
|
||||
`define FPGA_HF_ISO14443A_READER_MOD 4
|
||||
|
||||
//options for ISO18092 / Felica
|
||||
`define FPGA_HF_ISO18092_FLAG_NOMOD 1 // 0001 disable modulation module
|
||||
`define FPGA_HF_ISO18092_FLAG_424K 2 // 0010 should enable 414k mode (untested). No autodetect
|
||||
`define FPGA_HF_ISO18092_FLAG_READER 4 // 0100 enables antenna power, to act as a reader instead of tag
|
||||
|
||||
`include "hi_reader.v"
|
||||
`include "hi_simulate.v"
|
||||
//`include "hi_iso14443a.v"
|
||||
`include "hi_sniffer.v"
|
||||
`include "util.v"
|
||||
`include "hi_flite.v"
|
||||
`include "hi_get_trace.v"
|
||||
|
||||
module fpga_felica(
|
||||
input spck, output miso, input mosi, input ncs,
|
||||
input pck0, input ck_1356meg, input ck_1356megb,
|
||||
output pwr_lo, output pwr_hi,
|
||||
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
|
||||
input [7:0] adc_d, output adc_clk, output adc_noe,
|
||||
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
|
||||
input cross_hi, input cross_lo,
|
||||
output dbg
|
||||
);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The SPI receiver. This sets up the configuration word, which the rest of
|
||||
// the logic looks at to determine how to connect the A/D and the coil
|
||||
// drivers (i.e., which section gets it). Also assign some symbolic names
|
||||
// to the configuration bits, for use below.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
Attempt to write up how its hooked up. Iceman 2020.
|
||||
|
||||
Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
|
||||
Send 16 bit command / data pair to FPGA
|
||||
The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
|
||||
where
|
||||
C is 4bit command
|
||||
D is 12bit data
|
||||
|
||||
shift_reg receive this 16bit frame
|
||||
|
||||
|
||||
-----+--------- frame layout --------------------
|
||||
bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
-----+-------------------------------------------
|
||||
cmd | x x x x
|
||||
major| x x x
|
||||
opt | x x x
|
||||
divi | x x x x x x x x
|
||||
thres| x x x x x x x x
|
||||
-----+-------------------------------------------
|
||||
*/
|
||||
|
||||
reg [15:0] shift_reg;
|
||||
reg [8:0] conf_word;
|
||||
reg trace_enable;
|
||||
|
||||
// We switch modes between transmitting to the 13.56 MHz tag and receiving
|
||||
// from it, which means that we must make sure that we can do so without
|
||||
// glitching, or else we will glitch the transmitted carrier.
|
||||
always @(posedge ncs)
|
||||
begin
|
||||
case(shift_reg[15:12])
|
||||
`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
|
||||
`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge spck)
|
||||
begin
|
||||
if(~ncs)
|
||||
begin
|
||||
shift_reg[15:1] <= shift_reg[14:0];
|
||||
shift_reg[0] <= mosi;
|
||||
end
|
||||
end
|
||||
|
||||
// select module (outputs) based on major mode
|
||||
wire [2:0] major_mode = conf_word[8:6];
|
||||
|
||||
// configuring the HF reader
|
||||
wire [1:0] subcarrier_frequency = conf_word[5:4];
|
||||
wire [3:0] minor_mode = conf_word[3:0];
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// And then we instantiate the modules corresponding to each of the FPGA's
|
||||
// major modes, and use muxes to connect the outputs of the active mode to
|
||||
// the output pins.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// 000 - HF reader
|
||||
hi_reader hr(
|
||||
ck_1356megb,
|
||||
hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
|
||||
adc_d, hr_adc_clk,
|
||||
hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
|
||||
hr_dbg,
|
||||
subcarrier_frequency, minor_mode
|
||||
);
|
||||
|
||||
// 001 - HF simulated tag
|
||||
hi_simulate hs(
|
||||
ck_1356meg,
|
||||
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
|
||||
adc_d, hs_adc_clk,
|
||||
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
|
||||
hs_dbg,
|
||||
minor_mode
|
||||
);
|
||||
|
||||
// 011 - HF sniff
|
||||
hi_sniffer he(
|
||||
ck_1356megb,
|
||||
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
|
||||
adc_d, he_adc_clk,
|
||||
he_ssp_frame, he_ssp_din, he_ssp_clk
|
||||
);
|
||||
|
||||
// 100 - HF ISO18092 FeliCa
|
||||
hi_flite hfl(
|
||||
ck_1356megb,
|
||||
hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
|
||||
adc_d, hfl_adc_clk,
|
||||
hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
|
||||
hfl_dbg,
|
||||
minor_mode
|
||||
);
|
||||
|
||||
// 101 - HF get trace
|
||||
hi_get_trace gt(
|
||||
ck_1356megb,
|
||||
adc_d, trace_enable, major_mode,
|
||||
gt_ssp_frame, gt_ssp_din, gt_ssp_clk
|
||||
);
|
||||
|
||||
// Major modes:
|
||||
// 000 -- HF reader; subcarrier frequency and modulation depth selectable
|
||||
// 001 -- HF simulated tag
|
||||
// 010 -- HF ISO14443-A - removed for space...
|
||||
// 011 -- HF sniff
|
||||
// 100 -- HF ISO18092 FeliCa
|
||||
// 101 -- HF get trace
|
||||
// 110 -- unused
|
||||
// 111 -- FPGA_MAJOR_MODE_OFF
|
||||
|
||||
// 000 001 010 011 100 101 110 111
|
||||
mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, 1'b0, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, 1'b0, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, 1'b0, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, 1'b0, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, 1'b0, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, 1'b0, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, 1'b0, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, 1'b0, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, 1'b0, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, 1'b0, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, 1'b0, he_dbg, hfl_dbg, 1'b0, 1'b0, 1'b0);
|
||||
|
||||
// In all modes, let the ADC's outputs be enabled.
|
||||
assign adc_noe = 1'b0;
|
||||
|
||||
endmodule
|
||||
Binary file not shown.
@@ -1,255 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// See LICENSE.txt for the text of the license.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
|
||||
// and the ARM. In the low-frequency modes it passes the data straight
|
||||
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
|
||||
// frequency modes, the FPGA might perform some demodulation first, to
|
||||
// reduce the amount of data that we must send to the ARM.
|
||||
//
|
||||
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
|
||||
// could be improved.
|
||||
//
|
||||
// Jonathan Westhues, March 2006
|
||||
//-----------------------------------------------------------------------------
|
||||
// Added ISO14443-A support
|
||||
//
|
||||
|
||||
|
||||
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
|
||||
// Note: the definitions here are without shifts
|
||||
|
||||
// Commands:
|
||||
`define FPGA_CMD_SET_CONFREG 1
|
||||
`define FPGA_CMD_TRACE_ENABLE 2
|
||||
|
||||
// Major modes:
|
||||
`define FPGA_MAJOR_MODE_HF_READER 0
|
||||
`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
|
||||
`define FPGA_MAJOR_MODE_HF_ISO14443A 2
|
||||
`define FPGA_MAJOR_MODE_HF_SNIFF 3
|
||||
`define FPGA_MAJOR_MODE_HF_ISO18092 4
|
||||
`define FPGA_MAJOR_MODE_HF_GET_TRACE 5
|
||||
`define FPGA_MAJOR_MODE_OFF 7
|
||||
|
||||
// Options for the generic HF reader
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
|
||||
`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
|
||||
`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
|
||||
`define FPGA_HF_READER_MODE_SNIFF_IQ 5
|
||||
`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
|
||||
`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
|
||||
`define FPGA_HF_READER_MODE_SEND_JAM 8
|
||||
|
||||
`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
|
||||
`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
|
||||
`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
|
||||
|
||||
// Options for the HF simulated tag, how to modulate
|
||||
`define FPGA_HF_SIMULATOR_NO_MODULATION 0
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_212K 2
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_424K 4
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
|
||||
|
||||
// Options for ISO14443A
|
||||
`define FPGA_HF_ISO14443A_SNIFFER 0
|
||||
`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
|
||||
`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
|
||||
`define FPGA_HF_ISO14443A_READER_LISTEN 3
|
||||
`define FPGA_HF_ISO14443A_READER_MOD 4
|
||||
|
||||
//options for ISO18092 / Felica
|
||||
`define FPGA_HF_ISO18092_FLAG_NOMOD 1 // 0001 disable modulation module
|
||||
`define FPGA_HF_ISO18092_FLAG_424K 2 // 0010 should enable 414k mode (untested). No autodetect
|
||||
`define FPGA_HF_ISO18092_FLAG_READER 4 // 0100 enables antenna power, to act as a reader instead of tag
|
||||
|
||||
`include "hi_reader.v"
|
||||
`include "hi_simulate.v"
|
||||
`include "hi_iso14443a.v"
|
||||
`include "hi_sniffer.v"
|
||||
`include "util.v"
|
||||
// `include "hi_flite.v"
|
||||
`include "hi_get_trace.v"
|
||||
|
||||
module fpga_hf(
|
||||
input spck, output miso, input mosi, input ncs,
|
||||
input pck0, input ck_1356meg, input ck_1356megb,
|
||||
output pwr_lo, output pwr_hi,
|
||||
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
|
||||
input [7:0] adc_d, output adc_clk, output adc_noe,
|
||||
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
|
||||
input cross_hi, input cross_lo,
|
||||
output dbg
|
||||
);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The SPI receiver. This sets up the configuration word, which the rest of
|
||||
// the logic looks at to determine how to connect the A/D and the coil
|
||||
// drivers (i.e., which section gets it). Also assign some symbolic names
|
||||
// to the configuration bits, for use below.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
Attempt to write up how its hooked up.
|
||||
/ Iceman, 2020
|
||||
|
||||
Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
|
||||
Send 16 bit command / data pair to FPGA
|
||||
The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
|
||||
where
|
||||
C is 4bit command
|
||||
D is 12bit data
|
||||
|
||||
shift_reg receive this 16bit frame
|
||||
|
||||
|
||||
-----+--------- frame layout --------------------
|
||||
bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
-----+-------------------------------------------
|
||||
cmd | x x x x
|
||||
major| x x x
|
||||
opt | x x x x
|
||||
sub | x x
|
||||
divi | x x x x x x x x
|
||||
thres| x x x x x x x x
|
||||
-----+-------------------------------------------
|
||||
*/
|
||||
|
||||
reg [15:0] shift_reg;
|
||||
reg [8:0] conf_word;
|
||||
reg trace_enable;
|
||||
|
||||
// We switch modes between transmitting to the 13.56 MHz tag and receiving
|
||||
// from it, which means that we must make sure that we can do so without
|
||||
// glitching, or else we will glitch the transmitted carrier.
|
||||
always @(posedge ncs)
|
||||
begin
|
||||
case(shift_reg[15:12])
|
||||
`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
|
||||
`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge spck)
|
||||
begin
|
||||
if(~ncs)
|
||||
begin
|
||||
shift_reg[15:1] <= shift_reg[14:0];
|
||||
shift_reg[0] <= mosi;
|
||||
end
|
||||
end
|
||||
|
||||
// select module (outputs) based on major mode
|
||||
wire [2:0] major_mode = conf_word[8:6];
|
||||
|
||||
// configuring the HF reader
|
||||
wire [1:0] subcarrier_frequency = conf_word[5:4];
|
||||
wire [3:0] minor_mode = conf_word[3:0];
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// And then we instantiate the modules corresponding to each of the FPGA's
|
||||
// major modes, and use muxes to connect the outputs of the active mode to
|
||||
// the output pins.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// 000 - HF reader
|
||||
hi_reader hr(
|
||||
ck_1356megb,
|
||||
hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
|
||||
adc_d, hr_adc_clk,
|
||||
hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
|
||||
hr_dbg,
|
||||
subcarrier_frequency, minor_mode
|
||||
);
|
||||
|
||||
// 001 - HF simulated tag
|
||||
hi_simulate hs(
|
||||
ck_1356meg,
|
||||
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
|
||||
adc_d, hs_adc_clk,
|
||||
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
|
||||
hs_dbg,
|
||||
minor_mode
|
||||
);
|
||||
|
||||
// 010 - HF ISO14443-A
|
||||
hi_iso14443a hisn(
|
||||
ck_1356meg,
|
||||
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
|
||||
adc_d, hisn_adc_clk,
|
||||
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
|
||||
hisn_dbg,
|
||||
minor_mode
|
||||
);
|
||||
|
||||
// 011 - HF sniff
|
||||
hi_sniffer he(
|
||||
ck_1356megb,
|
||||
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
|
||||
adc_d, he_adc_clk,
|
||||
he_ssp_frame, he_ssp_din, he_ssp_clk
|
||||
);
|
||||
|
||||
// 100 - HF ISO18092 FeliCa
|
||||
/*
|
||||
hi_flite hfl(
|
||||
ck_1356megb,
|
||||
hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
|
||||
adc_d, hfl_adc_clk,
|
||||
hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
|
||||
hfl_dbg,
|
||||
minor_mode
|
||||
);
|
||||
*/
|
||||
|
||||
// 101 - HF get trace
|
||||
hi_get_trace gt(
|
||||
ck_1356megb,
|
||||
adc_d, trace_enable, major_mode,
|
||||
gt_ssp_frame, gt_ssp_din, gt_ssp_clk
|
||||
);
|
||||
|
||||
// Major modes:
|
||||
// 000 -- HF reader; subcarrier frequency and modulation depth selectable
|
||||
// 001 -- HF simulated tag
|
||||
// 010 -- HF ISO14443-A
|
||||
// 011 -- HF sniff
|
||||
// 100 -- HF ISO18092 FeliCa
|
||||
// 101 -- HF get trace
|
||||
// 110 -- unused
|
||||
// 111 -- FPGA_MAJOR_MODE_OFF
|
||||
|
||||
// 000 001 010 011 100 101 110 111
|
||||
|
||||
mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, gt_ssp_clk, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, gt_ssp_din, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, gt_ssp_frame, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0, 1'b0);
|
||||
|
||||
// In all modes, let the ADC's outputs be enabled.
|
||||
assign adc_noe = 1'b0;
|
||||
|
||||
endmodule
|
||||
Binary file not shown.
@@ -1,233 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// See LICENSE.txt for the text of the license.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
|
||||
// and the ARM. In the low-frequency modes it passes the data straight
|
||||
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
|
||||
// frequency modes, the FPGA might perform some demodulation first, to
|
||||
// reduce the amount of data that we must send to the ARM.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
|
||||
// Note: the definitions here are without shifts
|
||||
|
||||
// Commands:
|
||||
`define FPGA_CMD_SET_CONFREG 1
|
||||
`define FPGA_CMD_TRACE_ENABLE 2
|
||||
|
||||
// Major modes:
|
||||
`define FPGA_MAJOR_MODE_HF_READER 0
|
||||
`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
|
||||
`define FPGA_MAJOR_MODE_HF_ISO14443A 2
|
||||
`define FPGA_MAJOR_MODE_HF_SNIFF 3
|
||||
`define FPGA_MAJOR_MODE_HF_ISO18092 4
|
||||
`define FPGA_MAJOR_MODE_HF_GET_TRACE 5
|
||||
`define FPGA_MAJOR_MODE_HF_FSK_READER 6
|
||||
`define FPGA_MAJOR_MODE_OFF 7
|
||||
|
||||
// Options for the generic HF reader
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
|
||||
`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
|
||||
`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
|
||||
`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
|
||||
`define FPGA_HF_READER_MODE_SNIFF_IQ 5
|
||||
`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
|
||||
`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
|
||||
`define FPGA_HF_READER_MODE_SEND_JAM 8
|
||||
|
||||
`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
|
||||
`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
|
||||
`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
|
||||
`define FPGA_HF_READER_2SUBCARRIERS_424_484_KHZ 3
|
||||
|
||||
`define FPGA_HF_FSK_READER_OUTPUT_1695_KHZ 0
|
||||
`define FPGA_HF_FSK_READER_OUTPUT_848_KHZ 1
|
||||
`define FPGA_HF_FSK_READER_OUTPUT_424_KHZ 2
|
||||
`define FPGA_HF_FSK_READER_OUTPUT_212_KHZ 3
|
||||
|
||||
`define FPGA_HF_FSK_READER_NOPOWER 0
|
||||
`define FPGA_HF_FSK_READER_WITHPOWER 1
|
||||
|
||||
// Options for the HF simulated tag, how to modulate
|
||||
`define FPGA_HF_SIMULATOR_NO_MODULATION 0
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_212K 2
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_424K 4
|
||||
`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
|
||||
|
||||
// Options for ISO14443A
|
||||
`define FPGA_HF_ISO14443A_SNIFFER 0
|
||||
`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
|
||||
`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
|
||||
`define FPGA_HF_ISO14443A_READER_LISTEN 3
|
||||
`define FPGA_HF_ISO14443A_READER_MOD 4
|
||||
|
||||
//options for ISO18092 / Felica
|
||||
`define FPGA_HF_ISO18092_FLAG_NOMOD 1 // 0001 disable modulation module
|
||||
`define FPGA_HF_ISO18092_FLAG_424K 2 // 0010 should enable 414k mode (untested). No autodetect
|
||||
`define FPGA_HF_ISO18092_FLAG_READER 4 // 0100 enables antenna power, to act as a reader instead of tag
|
||||
|
||||
`include "hi_reader_15.v"
|
||||
`include "hi_simulate.v"
|
||||
`include "hi_sniffer.v"
|
||||
`include "util.v"
|
||||
`include "hi_get_trace.v"
|
||||
|
||||
module fpga_hf_15(
|
||||
input spck, output miso, input mosi, input ncs,
|
||||
input pck0, input ck_1356meg, input ck_1356megb,
|
||||
output pwr_lo, output pwr_hi,
|
||||
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
|
||||
input [7:0] adc_d, output adc_clk, output adc_noe,
|
||||
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
|
||||
input cross_hi, input cross_lo,
|
||||
output dbg
|
||||
);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The SPI receiver. This sets up the configuration word, which the rest of
|
||||
// the logic looks at to determine how to connect the A/D and the coil
|
||||
// drivers (i.e., which section gets it). Also assign some symbolic names
|
||||
// to the configuration bits, for use below.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
Attempt to write up how its hooked up.
|
||||
/ Iceman, 2020
|
||||
|
||||
Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
|
||||
Send 16 bit command / data pair to FPGA
|
||||
The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
|
||||
where
|
||||
C is 4bit command
|
||||
D is 12bit data
|
||||
|
||||
shift_reg receive this 16bit frame
|
||||
|
||||
|
||||
-----+--------- frame layout --------------------
|
||||
bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
-----+-------------------------------------------
|
||||
cmd | x x x x
|
||||
major| x x x
|
||||
opt | x x x x
|
||||
sub | x x
|
||||
divi | x x x x x x x x
|
||||
thres| x x x x x x x x
|
||||
-----+-------------------------------------------
|
||||
*/
|
||||
|
||||
reg [15:0] shift_reg;
|
||||
reg [8:0] conf_word;
|
||||
reg trace_enable;
|
||||
|
||||
// We switch modes between transmitting to the 13.56 MHz tag and receiving
|
||||
// from it, which means that we must make sure that we can do so without
|
||||
// glitching, or else we will glitch the transmitted carrier.
|
||||
always @(posedge ncs)
|
||||
begin
|
||||
case(shift_reg[15:12])
|
||||
`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
|
||||
`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge spck)
|
||||
begin
|
||||
if(~ncs)
|
||||
begin
|
||||
shift_reg[15:1] <= shift_reg[14:0];
|
||||
shift_reg[0] <= mosi;
|
||||
end
|
||||
end
|
||||
|
||||
// select module (outputs) based on major mode
|
||||
wire [2:0] major_mode = conf_word[8:6];
|
||||
|
||||
// configuring the HF reader
|
||||
wire [1:0] subcarrier_frequency = conf_word[5:4];
|
||||
wire [3:0] minor_mode = conf_word[3:0];
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// And then we instantiate the modules corresponding to each of the FPGA's
|
||||
// major modes, and use muxes to connect the outputs of the active mode to
|
||||
// the output pins.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// 000 - HF 15 reader
|
||||
hi_15_reader hr(
|
||||
ck_1356megb,
|
||||
hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
|
||||
adc_d, hr_adc_clk,
|
||||
hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
|
||||
hr_dbg,
|
||||
subcarrier_frequency, minor_mode
|
||||
);
|
||||
|
||||
// 001 - HF simulated tag
|
||||
hi_simulate hs(
|
||||
ck_1356meg,
|
||||
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
|
||||
adc_d, hs_adc_clk,
|
||||
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
|
||||
hs_dbg,
|
||||
minor_mode
|
||||
);
|
||||
|
||||
// 011 - HF sniff
|
||||
hi_sniffer he(
|
||||
ck_1356megb,
|
||||
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
|
||||
adc_d, he_adc_clk,
|
||||
he_ssp_frame, he_ssp_din, he_ssp_clk
|
||||
);
|
||||
|
||||
// 101 - HF get trace
|
||||
hi_get_trace gt(
|
||||
ck_1356megb,
|
||||
adc_d, trace_enable, major_mode,
|
||||
gt_ssp_frame, gt_ssp_din, gt_ssp_clk
|
||||
);
|
||||
|
||||
// Major modes:
|
||||
// 000 -- HF 15 reader; subcarrier frequency and modulation depth selectable
|
||||
// 001 -- HF simulated tag
|
||||
// 010 --
|
||||
// 011 -- HF sniff
|
||||
// 100 --
|
||||
// 101 -- HF get trace
|
||||
// 110 -- unused
|
||||
// 111 -- FPGA_MAJOR_MODE_OFF
|
||||
|
||||
// 000 001 010 011 100 101 110 111
|
||||
mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, 1'b0, he_ssp_clk, 1'b0, gt_ssp_clk, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, 1'b0, he_ssp_din, 1'b0, gt_ssp_din, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, 1'b0, he_ssp_frame, 1'b0, gt_ssp_frame, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, 1'b0, he_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, 1'b0, he_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, 1'b0, he_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, 1'b0, he_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, 1'b0, he_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, 1'b0, he_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, 1'b0, he_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, 1'b0, he_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
|
||||
// In all modes, let the ADC's outputs be enabled.
|
||||
assign adc_noe = 1'b0;
|
||||
|
||||
endmodule
|
||||
Binary file not shown.
@@ -1,245 +0,0 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// See LICENSE.txt for the text of the license.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
|
||||
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
|
||||
// Note: the definitions here are without shifts
|
||||
|
||||
// Commands:
|
||||
`define FPGA_CMD_SET_CONFREG 1
|
||||
`define FPGA_CMD_SET_DIVISOR 2
|
||||
`define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD 3
|
||||
|
||||
// Major modes:
|
||||
`define FPGA_MAJOR_MODE_LF_READER 0
|
||||
`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
|
||||
`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
|
||||
`define FPGA_MAJOR_MODE_LF_ADC 3
|
||||
|
||||
// Options for LF_READER
|
||||
`define FPGA_LF_ADC_READER_FIELD 1
|
||||
|
||||
// Options for LF_EDGE_DETECT
|
||||
`define FPGA_LF_EDGE_DETECT_READER_FIELD 1
|
||||
`define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 2
|
||||
|
||||
`include "lo_read.v"
|
||||
`include "lo_passthru.v"
|
||||
`include "lo_edge_detect.v"
|
||||
`include "lo_adc.v"
|
||||
`include "util.v"
|
||||
`include "clk_divider.v"
|
||||
|
||||
module fpga_lf(
|
||||
input spck, output miso, input mosi, input ncs,
|
||||
input pck0, input ck_1356meg, input ck_1356megb,
|
||||
output pwr_lo, output pwr_hi,
|
||||
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
|
||||
input [7:0] adc_d, output adc_clk, output adc_noe,
|
||||
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
|
||||
input cross_hi, input cross_lo,
|
||||
output dbg
|
||||
);
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// The SPI receiver. This sets up the configuration word, which the rest of
|
||||
// the logic looks at to determine how to connect the A/D and the coil
|
||||
// drivers (i.e., which section gets it). Also assign some symbolic names
|
||||
// to the configuration bits, for use below.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
Attempt to write up how its hooked up. Iceman 2020.
|
||||
|
||||
Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
|
||||
Send 16 bit command / data pair to FPGA
|
||||
The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
|
||||
where
|
||||
C is 4bit command
|
||||
D is 12bit data
|
||||
|
||||
shift_reg receive this 16bit frame
|
||||
|
||||
LF command
|
||||
----------
|
||||
shift_reg[15:12] == 4bit command
|
||||
LF has three commands (FPGA_CMD_SET_CONFREG, FPGA_CMD_SET_DIVISOR, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD)
|
||||
Current commands uses only 2bits. We have room for up to 4bits of commands total (7).
|
||||
|
||||
LF data
|
||||
-------
|
||||
shift_reg[11:0] == 12bit data
|
||||
lf data is divided into MAJOR MODES and configuration values.
|
||||
|
||||
The major modes uses 3bits (0,1,2,3,7 | 000, 001, 010, 011, 111)
|
||||
000 FPGA_MAJOR_MODE_LF_READER = Act as LF reader (modulate)
|
||||
001 FPGA_MAJOR_MODE_LF_EDGE_DETECT = Simulate LF
|
||||
010 FPGA_MAJOR_MODE_LF_PASSTHRU = Passthrough mode, CROSS_LO line connected to SSP_DIN. SSP_DOUT logic level controls if we modulate / listening
|
||||
011 FPGA_MAJOR_MODE_LF_ADC = refactor hitag2, clear ADC sampling
|
||||
111 FPGA_MAJOR_MODE_OFF = turn off sampling.
|
||||
|
||||
Each one of this major modes can have options. Currently these two major modes uses options.
|
||||
- FPGA_MAJOR_MODE_LF_READER
|
||||
- FPGA_MAJOR_MODE_LF_EDGE_DETECT
|
||||
|
||||
FPGA_MAJOR_MODE_LF_READER
|
||||
-------------------------------------
|
||||
lf_field = 1bit (FPGA_LF_ADC_READER_FIELD)
|
||||
|
||||
You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at
|
||||
divisor = 8bits shift_reg[7:0]
|
||||
|
||||
FPGA_MAJOR_MODE_LF_EDGE_DETECT
|
||||
------------------------------------------
|
||||
lf_ed_toggle_mode = 1bits
|
||||
lf_ed_threshold = 8bits threshold defaults to 127
|
||||
|
||||
You can send FPGA_CMD_SET_EDGE_DETECT_THRESHOLD to set a custom threshold
|
||||
lf_ed_threshold = 8bits threshold value.
|
||||
|
||||
conf_word 12bits
|
||||
conf_word[8:6] = 3bit major mode.
|
||||
conf_word[0] = 1bit lf_field
|
||||
conf_word[1] = 1bit lf_ed_toggle_mode
|
||||
conf_word[7:0] = 8bit divisor
|
||||
conf_word[7:0] = 8bit threshold
|
||||
|
||||
-----+--------- frame layout --------------------
|
||||
bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
-----+-------------------------------------------
|
||||
cmd | x x x x
|
||||
major| x x x
|
||||
opt | x x
|
||||
divi | x x x x x x x x
|
||||
thres| x x x x x x x x
|
||||
-----+-------------------------------------------
|
||||
*/
|
||||
|
||||
reg [15:0] shift_reg;
|
||||
reg [7:0] divisor;
|
||||
reg [7:0] lf_ed_threshold;
|
||||
reg [11:0] conf_word;
|
||||
|
||||
wire [2:0] major_mode = conf_word[8:6];
|
||||
wire lf_field = conf_word[0];
|
||||
wire lf_ed_toggle_mode = conf_word[1];
|
||||
|
||||
// Handles cmd / data frame from ARM
|
||||
always @(posedge ncs)
|
||||
begin
|
||||
// 4 bit command
|
||||
case (shift_reg[15:12])
|
||||
`FPGA_CMD_SET_CONFREG:
|
||||
begin
|
||||
// 12 bit data
|
||||
conf_word <= shift_reg[11:0];
|
||||
if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
|
||||
begin
|
||||
lf_ed_threshold <= 127; // default threshold
|
||||
end
|
||||
end
|
||||
|
||||
`FPGA_CMD_SET_DIVISOR:
|
||||
divisor <= shift_reg[7:0]; // 8bits
|
||||
|
||||
`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
|
||||
lf_ed_threshold <= shift_reg[7:0]; // 8 bits
|
||||
endcase
|
||||
end
|
||||
|
||||
// Receive 16bits of data from ARM here.
|
||||
always @(posedge spck)
|
||||
begin
|
||||
if (~ncs)
|
||||
begin
|
||||
shift_reg[15:1] <= shift_reg[14:0];
|
||||
shift_reg[0] <= mosi;
|
||||
end
|
||||
end
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// And then we instantiate the modules corresponding to each of the FPGA's
|
||||
// major modes, and use muxes to connect the outputs of the active mode to
|
||||
// the output pins.
|
||||
//-----------------------------------------------------------------------------
|
||||
wire [7:0] pck_cnt;
|
||||
wire pck_divclk;
|
||||
clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
|
||||
|
||||
lo_read lr(
|
||||
pck0, pck_cnt, pck_divclk,
|
||||
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
|
||||
adc_d, lr_adc_clk,
|
||||
lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
|
||||
lr_dbg, lf_field
|
||||
);
|
||||
|
||||
lo_passthru lp(
|
||||
pck_divclk,
|
||||
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
|
||||
lp_adc_clk,
|
||||
lp_ssp_din, ssp_dout,
|
||||
cross_lo,
|
||||
lp_dbg
|
||||
);
|
||||
|
||||
lo_edge_detect le(
|
||||
pck0, pck_divclk,
|
||||
le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
|
||||
adc_d, le_adc_clk,
|
||||
le_ssp_frame, ssp_dout, le_ssp_clk,
|
||||
cross_lo,
|
||||
le_dbg,
|
||||
lf_field,
|
||||
lf_ed_toggle_mode, lf_ed_threshold
|
||||
);
|
||||
|
||||
lo_adc la(
|
||||
pck0,
|
||||
la_pwr_lo, la_pwr_hi, la_pwr_oe1, la_pwr_oe2, la_pwr_oe3, la_pwr_oe4,
|
||||
adc_d, la_adc_clk,
|
||||
la_ssp_frame, la_ssp_din, ssp_dout, la_ssp_clk,
|
||||
la_dbg, divisor,
|
||||
lf_field
|
||||
);
|
||||
|
||||
// Major modes:
|
||||
// 000 -- LF reader (generic)
|
||||
// 001 -- LF edge detect (generic)
|
||||
// 010 -- LF passthrough
|
||||
// 011 -- LF ADC (read/write)
|
||||
// 100 -- unused
|
||||
// 101 -- unused
|
||||
// 110 -- unused
|
||||
// 111 -- FPGA_MAJOR_MODE_OFF
|
||||
// 000 001 010 011 100 101 110 111
|
||||
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, la_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, la_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, la_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, la_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, la_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, la_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, la_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, la_pwr_lo, 1'b0, 1'b0, 1'b1, 1'b0);
|
||||
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, la_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, la_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, la_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
|
||||
|
||||
// In all modes, let the ADC's outputs be enabled.
|
||||
assign adc_noe = 1'b0;
|
||||
|
||||
endmodule
|
||||
@@ -1,68 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rmdir/s/q xst
|
||||
|
||||
del fpga_lf.ngc
|
||||
xst -ifn xst_lf.scr
|
||||
if errorlevel 0 goto ok1
|
||||
goto done
|
||||
:ok1
|
||||
|
||||
del fpga_lf.ngd
|
||||
ngdbuild -aul -p xc2s30-6vq100 -nt timestamp -uc fpga.ucf fpga_lf.ngc fpga_lf.ngd
|
||||
if errorlevel 0 goto ok2
|
||||
goto done
|
||||
:ok2
|
||||
|
||||
del fpga_lf.ncd
|
||||
map -p xc2s30-6vq100 fpga_lf.ngd
|
||||
if errorlevel 0 goto ok3
|
||||
goto done
|
||||
:ok3
|
||||
|
||||
del fpga_lf-placed.ncd
|
||||
par fpga_lf.ncd fpga_lf-placed.ncd
|
||||
if errorlevel 0 goto ok4
|
||||
goto done
|
||||
:ok4
|
||||
|
||||
del fpga_lf.bit fpga_lf.drc fpga_lf.rbt
|
||||
bitgen -b fpga_lf-placed.ncd fpga_lf.bit
|
||||
if errorlevel 0 goto ok5
|
||||
goto done
|
||||
:ok5
|
||||
|
||||
del fpga_hf.ngc
|
||||
xst -ifn xst_hf.scr
|
||||
if errorlevel 0 goto ok6
|
||||
goto done
|
||||
:ok6
|
||||
|
||||
del fpga_hf.ngd
|
||||
ngdbuild -aul -p xc2s30-6vq100 -nt timestamp -uc fpga.ucf fpga_hf.ngc fpga_hf.ngd
|
||||
if errorlevel 0 goto ok7
|
||||
goto done
|
||||
:ok7
|
||||
|
||||
del fpga_hf.ncd
|
||||
map -p xc2s30-6vq100 fpga_hf.ngd
|
||||
if errorlevel 0 goto ok8
|
||||
goto done
|
||||
:ok8
|
||||
|
||||
del fpga_hf-placed.ncd
|
||||
par fpga_hf.ncd fpga_hf-placed.ncd
|
||||
if errorlevel 0 goto ok9
|
||||
goto done
|
||||
:ok9
|
||||
|
||||
del fpga_hf.bit fpga_hf.drc fpga_hf.rbt
|
||||
bitgen -b fpga_hf-placed.ncd fpga_hf.bit
|
||||
if errorlevel 0 goto ok10
|
||||
goto done
|
||||
:ok10
|
||||
|
||||
echo okay
|
||||
perl ..\tools\rbt2c.pl fpga_lf.rbt > ..\armsrc\fpgaimg.c
|
||||
|
||||
:done
|
||||
@@ -1 +0,0 @@
|
||||
run -ifn fpga_felica.v -ifmt Verilog -ofn fpga_felica.ngc -ofmt NGC -p xc2s30-5-vq100 -top fpga_felica -opt_mode area -opt_level 2 -resource_sharing yes -fsm_style bram -fsm_encoding compact
|
||||
@@ -1 +0,0 @@
|
||||
run -ifn fpga_hf.v -ifmt Verilog -ofn fpga_hf.ngc -ofmt NGC -p xc2s30-5-vq100 -top fpga_hf -opt_mode area -opt_level 2 -resource_sharing yes -fsm_style bram -fsm_encoding compact
|
||||
@@ -1 +0,0 @@
|
||||
run -ifn fpga_hf_15.v -ifmt Verilog -ofn fpga_hf_15.ngc -ofmt NGC -p xc2s30-5-vq100 -top fpga_hf_15 -opt_mode area -opt_level 2 -resource_sharing yes -fsm_style bram -fsm_encoding compact
|
||||
@@ -1 +0,0 @@
|
||||
run -ifn fpga_lf.v -ifmt Verilog -ofn fpga_lf.ngc -ofmt NGC -p xc2s30-5-vq100 -top fpga_lf -opt_mode area -opt_level 2 -resource_sharing yes -fsm_style bram -fsm_encoding compact
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user