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IPL3 documentation; undefined_syms.txt finally deleted (#545)

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* yeet undefined_syms; IPL3 documentation; theoretical addition of checksum skip and initial DMA length/location change

* another comment about how to set dma len

* comment is now correct in ultratypes

* do the rename

* remove insinuations that ipl3 can be modified

---------

Co-authored-by: someone2639 <someone2639@gmail.com>
This commit is contained in:
someone2639
2023-06-26 13:35:52 -04:00
committed by GitHub
parent 1eba347c07
commit e2cf2d5119
5 changed files with 133 additions and 174 deletions
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8
Makefile
View File

@@ -589,7 +589,7 @@ patch: $(ROM)
$(FLIPS) --create --bps ./baserom.$(VERSION).z64 $(ROM) $(BUILD_DIR)/$(TARGET_STRING).bps
# Extra object file dependencies
$(BUILD_DIR)/asm/boot.o: $(IPL3_RAW_FILES)
$(BUILD_DIR)/asm/ipl3.o: $(IPL3_RAW_FILES)
$(BUILD_DIR)/src/game/crash_screen.o: $(CRASH_TEXTURE_C_FILES)
$(BUILD_DIR)/src/game/version.o: $(BUILD_DIR)/src/game/version_data.h
$(BUILD_DIR)/lib/aspMain.o: $(BUILD_DIR)/rsp/audio.bin
@@ -865,7 +865,7 @@ $(BUILD_DIR)/sm64_prelim.ld: sm64.ld $(O_FILES) $(YAY0_OBJ_FILES) $(SEG_FILES) $
$(BUILD_DIR)/sm64_prelim.elf: $(BUILD_DIR)/sm64_prelim.ld
@$(PRINT) "$(GREEN)Linking Preliminary ELF file: $(BLUE)$@ $(NO_COL)\n"
$(V)$(LD) --gc-sections -L $(BUILD_DIR) -T undefined_syms.txt -T $< -Map $(BUILD_DIR)/sm64_prelim.map --no-check-sections $(addprefix -R ,$(SEG_FILES)) -o $@ $(O_FILES) -L$(LIBS_DIR) -l$(ULTRALIB) -Llib $(LINK_LIBRARIES) -u sprintf -u osMapTLB -Llib/gcclib/$(LIBGCCDIR) -lgcc
$(V)$(LD) --gc-sections -L $(BUILD_DIR) -T $< -Map $(BUILD_DIR)/sm64_prelim.map --no-check-sections $(addprefix -R ,$(SEG_FILES)) -o $@ $(O_FILES) -L$(LIBS_DIR) -l$(ULTRALIB) -Llib $(LINK_LIBRARIES) -u sprintf -u osMapTLB -Llib/gcclib/$(LIBGCCDIR) -lgcc
$(BUILD_DIR)/goddard.txt: $(BUILD_DIR)/sm64_prelim.elf
$(call print,Getting Goddard size...)
@@ -877,9 +877,9 @@ $(BUILD_DIR)/asm/debug/map.o: asm/debug/map.s $(BUILD_DIR)/sm64_prelim.elf
$(V)$(CROSS)gcc -c $(ASMFLAGS) $(foreach i,$(INCLUDE_DIRS),-Wa,-I$(i)) -x assembler-with-cpp -MMD -MF $(BUILD_DIR)/$*.d -o $@ $<
# Link SM64 ELF file
$(ELF): $(BUILD_DIR)/sm64_prelim.elf $(BUILD_DIR)/asm/debug/map.o $(O_FILES) $(YAY0_OBJ_FILES) $(SEG_FILES) $(BUILD_DIR)/$(LD_SCRIPT) undefined_syms.txt $(BUILD_DIR)/libz.a $(BUILD_DIR)/libgoddard.a
$(ELF): $(BUILD_DIR)/sm64_prelim.elf $(BUILD_DIR)/asm/debug/map.o $(O_FILES) $(YAY0_OBJ_FILES) $(SEG_FILES) $(BUILD_DIR)/$(LD_SCRIPT) $(BUILD_DIR)/libz.a $(BUILD_DIR)/libgoddard.a
@$(PRINT) "$(GREEN)Linking ELF file: $(BLUE)$@ $(NO_COL)\n"
$(V)$(LD) --gc-sections -L $(BUILD_DIR) -T undefined_syms.txt -T $(BUILD_DIR)/$(LD_SCRIPT) -T goddard.txt -Map $(BUILD_DIR)/sm64.$(VERSION).map --no-check-sections $(addprefix -R ,$(SEG_FILES)) -o $@ $(O_FILES) -L$(LIBS_DIR) -l$(ULTRALIB) -Llib $(LINK_LIBRARIES) -u sprintf -u osMapTLB -Llib/gcclib/$(LIBGCCDIR) -lgcc -lrtc
$(V)$(LD) --gc-sections -L $(BUILD_DIR) -T $(BUILD_DIR)/$(LD_SCRIPT) -T goddard.txt -Map $(BUILD_DIR)/sm64.$(VERSION).map --no-check-sections $(addprefix -R ,$(SEG_FILES)) -o $@ $(O_FILES) -L$(LIBS_DIR) -l$(ULTRALIB) -Llib $(LINK_LIBRARIES) -u sprintf -u osMapTLB -Llib/gcclib/$(LIBGCCDIR) -lgcc -lrtc
# Build ROM
ifeq (n,$(findstring n,$(firstword -$(MAKEFLAGS))))

233
asm/boot.s → asm/ipl3.s
View File

@@ -4,24 +4,39 @@
.set gp=64
#include "macros.inc"
#undef _LANGUAGE_C
#include <PR/rcp.h>
#define PHYS_TO_CART(addr) ((addr) | 0xB0000000)
.set CART_ENTRYPOINT, 0x00000008
.set CART_CHECKSUM0, 0x00000010
.set CART_CHECKSUM1, 0x00000014
// initial DMEM state
.set SP_DMEM_UNK0, 0x040004C0
.set SP_DMEM_UNK1, 0x04000774
// Used for documentation; changing these can and will break your ROM!
.set INITIAL_DMA_LEN, 0x00100000
.set INITIAL_DMA_ROMPOS, 0x1000
// 0xA0000000-0xBFFFFFFF: KSEG1 direct map non-cache mirror of 0x00000000
// 0xA4000000-0xA4000FFF: RSP DMEM
// 0xA4000000-0xA400003F: ROM header
.section .text, "ax"
// 0xA4000040-0xA4000B6F: IPL3
// IPL3 entry point jumped to from IPL2
glabel ipl3_entry // 0xA4000040
mtc0 $zero, $13
mtc0 $zero, $9
mtc0 $zero, $11
lui $t0, %hi(RI_MODE_REG)
addiu $t0, %lo(RI_MODE_REG)
lw $t1, 0xc($t0)
.ent ipl3_entry
mtc0 $zero, C0_CAUSE
mtc0 $zero, C0_COUNT
mtc0 $zero, C0_COMPARE
lui $t0, %hi(PHYS_TO_K1(RI_BASE_REG))
addiu $t0, %lo(PHYS_TO_K1(RI_BASE_REG))
lw $t1, %lo(RI_SELECT_REG)($t0)
bnez $t1, .LA4000410
nop
addiu $sp, $sp, -0x18
@@ -30,24 +45,24 @@ glabel ipl3_entry // 0xA4000040
sw $s5, 8($sp)
sw $s6, 0xc($sp)
sw $s7, 0x10($sp)
lui $t0, %hi(RI_MODE_REG)
addiu $t0, %lo(RI_MODE_REG)
lui $t2, (0xa3f80000 >> 16)
lui $t3, (0xa3f00000 >> 16)
lui $t4, %hi(MI_MODE_REG)
addiu $t4, %lo(MI_MODE_REG)
lui $t0, %hi(PHYS_TO_K1(RI_BASE_REG))
addiu $t0, %lo(PHYS_TO_K1(RI_BASE_REG))
lui $t2, %hi(PHYS_TO_K1(RDRAM_BASE_REG + 0x80000))
lui $t3, %hi(PHYS_TO_K1(RDRAM_BASE_REG))
lui $t4, %hi(PHYS_TO_K1(MI_BASE_REG))
addiu $t4, %lo(PHYS_TO_K1(MI_BASE_REG))
ori $t1, $zero, 64
sw $t1, 4($t0)
sw $t1, %lo(MI_VERSION_REG)($t0)
li $s1, 8000
.LA400009C:
nop
addi $s1, $s1, -1
bnez $s1, .LA400009C
nop
sw $zero, 8($t0)
ori $t1, $zero, 20
sw $t1, 0xc($t0)
sw $zero, ($t0)
sw $zero, %lo(RI_CURRENT_LOAD_REG)($t0)
ori $t1, $zero, 0x14
sw $t1, %lo(RI_SELECT_REG)($t0)
sw $zero, %lo(RI_MODE_REG)($t0)
li $s1, 4
.LA40000C0:
nop
@@ -55,34 +70,34 @@ glabel ipl3_entry // 0xA4000040
bnez $s1, .LA40000C0
nop
ori $t1, $zero, 14
sw $t1, ($t0)
sw $t1, %lo(RI_MODE_REG)($t0)
li $s1, 32
.LA40000DC:
addi $s1, $s1, -1
bnez $s1, .LA40000DC
ori $t1, $zero, 271
sw $t1, ($t4)
ori $t1, $zero, (MI_SET_INIT | 0xF)
sw $t1, %lo(MI_MODE_REG)($t4)
lui $t1, (0x18082838 >> 16)
ori $t1, (0x18082838 & 0xFFFF)
sw $t1, 0x8($t2)
sw $zero, 0x14($t2)
sw $t1, %lo(RDRAM_DELAY_REG)($t2)
sw $zero, %lo(RDRAM_REF_ROW_REG)($t2)
lui $t1, 0x8000
sw $t1, 0x4($t2)
sw $t1, %lo(RDRAM_DEVICE_ID_REG)($t2)
move $t5, $zero
move $t6, $zero
lui $t7, (0xA3F00000 >> 16)
lui $t7, %hi(PHYS_TO_K1(RDRAM_BASE_REG))
move $t8, $zero
lui $t9, (0xA3F00000 >> 16)
lui $t9, %hi(PHYS_TO_K1(RDRAM_BASE_REG))
lui $s6, (0xA0000000 >> 16)
move $s7, $zero
lui $a2, (0xA3F00000 >> 16)
lui $a2, %hi(PHYS_TO_K1(RDRAM_BASE_REG))
lui $a3, (0xA0000000 >> 16)
move $s2, $zero
lui $s4, (0xA0000000 >> 16)
addiu $sp, $sp, -0x48
move $fp, $sp
lui $s0, %hi(MI_VERSION_REG)
lw $s0, %lo(MI_VERSION_REG)($s0)
lui $s0, %hi(PHYS_TO_K1(MI_VERSION_REG))
lw $s0, %lo(PHYS_TO_K1(MI_VERSION_REG))($s0)
lui $s1, (0x01010101 >> 16)
addiu $s1, (0x01010101 & 0xFFFF)
bne $s0, $s1, .LA4000160
@@ -103,14 +118,14 @@ glabel ipl3_entry // 0xA4000040
nop
sw $v0, ($sp)
li $t1, 8192
sw $t1, ($t4)
lw $t3, ($t7)
sw $t1, %lo(MI_MODE_REG)($t4)
lw $t3, %lo(RDRAM_CONFIG_REG)($t7)
lui $t0, 0xf0ff
and $t3, $t3, $t0
sw $t3, 4($sp)
addi $sp, $sp, 8
li $t1, 4096
sw $t1, ($t4)
sw $t1, %lo(MI_MODE_REG)($t4)
lui $t0, 0xb019
bne $t3, $t0, .LA40001E0
nop
@@ -130,11 +145,11 @@ glabel ipl3_entry // 0xA4000040
add $s4, $s4, $t0
.LA40001E8:
li $t0, 8192
sw $t0, ($t4)
lw $t1, 0x24($t7)
lw $k0, ($t7)
sw $t0, %lo(MI_MODE_REG)($t4)
lw $t1, %lo(RDRAM_DEVICE_MANUF_REG)($t7)
lw $k0, %lo(RDRAM_CONFIG_REG)($t7)
li $t0, 4096
sw $t0, ($t4)
sw $t0, %lo(MI_MODE_REG)($t4)
andi $t1, $t1, 0xffff
li $t0, 1280
bne $t1, $t0, .LA4000230
@@ -162,9 +177,9 @@ glabel ipl3_entry // 0xA4000040
nop
.LA400025C:
li $t0, 0xc4000000
sw $t0, 0xc($t2)
sw $t0, %lo(RDRAM_MODE_REG)($t2)
li $t0, 0x80000000
sw $t0, 0x4($t2)
sw $t0, %lo(RDRAM_DEVICE_ID_REG)($t2)
move $sp, $fp
move $v1, $zero
.LA4000274:
@@ -232,7 +247,7 @@ glabel ipl3_entry // 0xA4000040
slt $t0, $v1, $t5
bnez $t0, .LA4000274
nop
lui $t2, %hi(RI_REFRESH_REG)
lui $t2, %hi(PHYS_TO_K1(RI_BASE_REG))
sll $s2, $s2, 0x13
lui $t1, (0x00063634 >> 16)
ori $t1, (0x00063634 & 0xFFFF)
@@ -253,8 +268,8 @@ glabel ipl3_entry // 0xA4000040
lw $s6, 0xc($sp)
lw $s7, 0x10($sp)
addiu $sp, $sp, 0x18
lui $t0, %hi(EXCEPTION_TLB_MISS)
addiu $t0, $t0, %lo(EXCEPTION_TLB_MISS)
lui $t0, %hi(UT_VEC)
addiu $t0, $t0, %lo(UT_VEC)
addiu $t1, $t0, 0x4000
addiu $t1, $t1, -0x20
mtc0 $zero, $28
@@ -264,8 +279,8 @@ glabel ipl3_entry // 0xA4000040
sltu $at, $t0, $t1
bnez $at, .LA40003D8
addiu $t0, $t0, 0x20
lui $t0, %hi(EXCEPTION_TLB_MISS)
addiu $t0, %lo(EXCEPTION_TLB_MISS)
lui $t0, %hi(UT_VEC)
addiu $t0, %lo(UT_VEC)
addiu $t1, $t0, 0x2000
addiu $t1, $t1, -0x10
.LA40003F8:
@@ -276,8 +291,8 @@ glabel ipl3_entry // 0xA4000040
b .LA4000458
nop
.LA4000410:
lui $t0, %hi(EXCEPTION_TLB_MISS)
addiu $t0, %lo(EXCEPTION_TLB_MISS)
lui $t0, %hi(UT_VEC)
addiu $t0, %lo(UT_VEC)
addiu $t1, $t0, 0x4000
addiu $t1, $t1, -0x20
mtc0 $zero, $28
@@ -287,8 +302,8 @@ glabel ipl3_entry // 0xA4000040
sltu $at, $t0, $t1
bnez $at, .LA4000428
addiu $t0, $t0, 0x20
lui $t0, %hi(EXCEPTION_TLB_MISS)
addiu $t0, %lo(EXCEPTION_TLB_MISS)
lui $t0, %hi(UT_VEC)
addiu $t0, %lo(UT_VEC)
addiu $t1, $t0, 0x2000
addiu $t1, $t1, -0x10
.LA4000448:
@@ -297,16 +312,16 @@ glabel ipl3_entry // 0xA4000040
bnez $at, .LA4000448
addiu $t0, $t0, 0x10
.LA4000458:
lui $t2, %hi(SP_DMEM)
addiu $t2, $t2, %lo(SP_DMEM)
lui $t2, %hi(PHYS_TO_K1(SP_DMEM_START))
addiu $t2, $t2, %lo(PHYS_TO_K1(SP_DMEM_START))
lui $t3, 0xfff0
lui $t1, 0x0010
and $t2, $t2, $t3
lui $t0, %hi(SP_DMEM_UNK0)
lui $t0, %hi(PHYS_TO_K1(SP_DMEM_UNK0))
addiu $t1, -1
lui $t3, %hi(SP_DMEM_UNK1)
addiu $t0, %lo(SP_DMEM_UNK0)
addiu $t3, %lo(SP_DMEM_UNK1)
lui $t3, %hi(PHYS_TO_K1(SP_DMEM_UNK1))
addiu $t0, %lo(PHYS_TO_K1(SP_DMEM_UNK0))
addiu $t3, %lo(PHYS_TO_K1(SP_DMEM_UNK1))
and $t0, $t0, $t1
and $t3, $t3, $t1
lui $t1, 0xa000
@@ -320,32 +335,32 @@ glabel ipl3_entry // 0xA4000040
addiu $t1, $t1, 4
bnez $at, .LA4000498
sw $t5, -4($t1)
lui $t4, %hi(EXCEPTION_TLB_MISS)
addiu $t4, %lo(EXCEPTION_TLB_MISS)
lui $t4, %hi(UT_VEC)
addiu $t4, %lo(UT_VEC)
jr $t4
nop
lui $t3, %hi(D_B0000008)
lw $t1, %lo(D_B0000008)($t3)
lui $t3, %hi(PHYS_TO_CART(CART_ENTRYPOINT))
lw $t1, %lo(PHYS_TO_CART(CART_ENTRYPOINT))($t3)
lui $t2, (0x1FFFFFFF >> 16)
ori $t2, (0x1FFFFFFF & 0xFFFF)
lui $at, %hi(PI_DRAM_ADDR_REG)
lui $at, %hi(PHYS_TO_K1(PI_DRAM_ADDR_REG))
and $t1, $t1, $t2
sw $t1, %lo(PI_DRAM_ADDR_REG)($at)
lui $t0, %hi(PI_STATUS_REG)
sw $t1, %lo(PHYS_TO_K1(PI_DRAM_ADDR_REG))($at)
lui $t0, %hi(PHYS_TO_K1(PI_STATUS_REG))
.LA40004D0:
lw $t0, %lo(PI_STATUS_REG)($t0)
andi $t0, $t0, 2
lw $t0, %lo(PHYS_TO_K1(PI_STATUS_REG))($t0)
andi $t0, $t0, PI_STATUS_IO_BUSY
bnezl $t0, .LA40004D0
lui $t0, %hi(PI_STATUS_REG)
li $t0, 0x1000
lui $t0, %hi(PHYS_TO_K1(PI_STATUS_REG))
li $t0, INITIAL_DMA_ROMPOS
add $t0, $t0, $t3
and $t0, $t0, $t2
lui $at, %hi(PI_CART_ADDR_REG)
sw $t0, %lo(PI_CART_ADDR_REG)($at)
lui $t2, 0x0010
addiu $t2, 0xFFFF
lui $at, %hi(PI_WR_LEN_REG)
sw $t2, %lo(PI_WR_LEN_REG)($at)
lui $at, %hi(PHYS_TO_K1(PI_CART_ADDR_REG))
sw $t0, %lo(PHYS_TO_K1(PI_CART_ADDR_REG))($at)
li $t2, INITIAL_DMA_LEN
addiu $t2, -1
lui $at, %hi(PHYS_TO_K1(PI_WR_LEN_REG))
sw $t2, %lo(PHYS_TO_K1(PI_WR_LEN_REG))($at)
.LA4000514:
nop
@@ -376,13 +391,13 @@ glabel ipl3_entry // 0xA4000040
nop
nop
nop
lui $t3, %hi(PI_STATUS_REG)
lw $t3, %lo(PI_STATUS_REG)($t3)
lui $t3, %hi(PHYS_TO_K1(PI_STATUS_REG))
lw $t3, %lo(PHYS_TO_K1(PI_STATUS_REG))($t3)
andi $t3, $t3, 0x1
bnez $t3, .LA4000514
nop
lui $t3, %hi(D_B0000008)
lw $a0, %lo(D_B0000008)($t3)
lui $t3, %hi(PHYS_TO_CART(CART_ENTRYPOINT))
lw $a0, %lo(PHYS_TO_CART(CART_ENTRYPOINT))($t3)
move $a1, $s6
lui $at, (0x5D588B65 >> 16)
ori $at, (0x5D588B65 & 0xFFFF)
@@ -436,52 +451,54 @@ glabel ipl3_entry // 0xA4000040
xor $a3, $t6, $t3
xor $t8, $s0, $a2
xor $s0, $t8, $t4
lui $t3, %hi(D_B0000010)
lw $t0, %lo(D_B0000010)($t3)
// verifies checksum
lui $t3, %hi(PHYS_TO_CART(CART_CHECKSUM0))
lw $t0, %lo(PHYS_TO_CART(CART_CHECKSUM0))($t3)
bne $a3, $t0, halt
nop
lw $t0, %lo(D_B0000014)($t3)
lw $t0, %lo(PHYS_TO_CART(CART_CHECKSUM1))($t3)
bne $s0, $t0, halt
nop
bal func_A4000690
nop
// In a permanent loop that cannot be exited.
halt:
bal halt
nop
func_A4000690:
lui $t1, %hi(SP_PC)
lw $t1, %lo(SP_PC)($t1)
lui $t1, %hi(PHYS_TO_K1(SP_PC_REG))
lw $t1, %lo(PHYS_TO_K1(SP_PC_REG))($t1)
lw $s0, 0x14($sp)
lw $ra, 0x1c($sp)
beqz $t1, .LA40006BC
addiu $sp, $sp, 0x20
li $t2, 65
lui $at, %hi(SP_STATUS_REG)
sw $t2, %lo(SP_STATUS_REG)($at)
lui $at, %hi(SP_PC)
sw $zero, %lo(SP_PC)($at)
lui $at, %hi(PHYS_TO_K1(SP_STATUS_REG))
sw $t2, %lo(PHYS_TO_K1(SP_STATUS_REG))($at)
lui $at, %hi(PHYS_TO_K1(SP_PC_REG))
sw $zero, %lo(PHYS_TO_K1(SP_PC_REG))($at)
.LA40006BC:
lui $t3, (0x00AAAAAE >> 16)
ori $t3, (0x00AAAAAE & 0xFFFF)
lui $at, %hi(SP_STATUS_REG)
sw $t3, %lo(SP_STATUS_REG)($at)
lui $at, %hi(MI_INTR_MASK_REG)
lui $at, %hi(PHYS_TO_K1(SP_STATUS_REG))
sw $t3, %lo(PHYS_TO_K1(SP_STATUS_REG))($at)
lui $at, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
li $t0, 1365
sw $t0, %lo(MI_INTR_MASK_REG)($at)
lui $at, %hi(SI_STATUS_REG)
sw $zero, %lo(SI_STATUS_REG)($at)
lui $at, %hi(AI_STATUS_REG)
sw $zero, %lo(AI_STATUS_REG)($at)
lui $at, %hi(MI_MODE_REG)
sw $t0, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($at)
lui $at, %hi(PHYS_TO_K1(SI_STATUS_REG))
sw $zero, %lo(PHYS_TO_K1(SI_STATUS_REG))($at)
lui $at, %hi(PHYS_TO_K1(AI_STATUS_REG))
sw $zero, %lo(PHYS_TO_K1(AI_STATUS_REG))($at)
lui $at, %hi(PHYS_TO_K1(MI_BASE_REG))
li $t1, 2048
sw $t1, %lo(MI_MODE_REG)($at)
sw $t1, %lo(PHYS_TO_K1(MI_BASE_REG))($at)
li $t1, 2
lui $at, %hi(PI_STATUS_REG)
lui $at, %hi(PHYS_TO_K1(PI_STATUS_REG))
lui $t0, (0xA0000300 >> 16)
ori $t0, (0xA0000300 & 0xFFFF)
sw $t1, %lo(PI_STATUS_REG)($at)
sw $t1, %lo(PHYS_TO_K1(PI_STATUS_REG))($at)
sw $s7, 0x14($t0)
sw $s5, 0xc($t0)
sw $s3, 0x4($t0)
@@ -495,22 +512,22 @@ func_A4000690:
addiu $t1, $t1, 0
.LA4000730:
sw $t1, 0x8($t0)
lui $t0, %hi(SP_DMEM)
addiu $t0, %lo(SP_DMEM)
lui $t0, %hi(PHYS_TO_K1(SP_DMEM_START))
addiu $t0, %lo(PHYS_TO_K1(SP_DMEM_START))
addi $t1, $t0, 0x1000
.LA4000740:
addiu $t0, $t0, 4
bne $t0, $t1, .LA4000740
sw $zero, -4($t0)
lui $t0, %hi(SP_IMEM)
addiu $t0, %lo(SP_IMEM)
lui $t0, %hi(PHYS_TO_K1(SP_IMEM_START))
addiu $t0, %lo(PHYS_TO_K1(SP_IMEM_START))
addi $t1, $t0, 0x1000
.LA4000758:
addiu $t0, $t0, 4
bne $t0, $t1, .LA4000758
sw $zero, -4($t0)
lui $t3, %hi(D_B0000008)
lw $t1, %lo(D_B0000008)($t3)
lui $t3, %hi(PHYS_TO_CART(CART_ENTRYPOINT))
lw $t1, %lo(PHYS_TO_CART(CART_ENTRYPOINT))($t3)
jr $t1
nop
nop
@@ -747,8 +764,8 @@ func_A4000A40:
li $k1, 1
bne $a1, $k1, .LA4000AC0
sw $t7, ($s5)
lui $k0, %hi(MI_MODE_REG)
sw $zero, %lo(MI_MODE_REG)($k0)
lui $k0, %hi(PHYS_TO_K1(MI_BASE_REG))
sw $zero, %lo(PHYS_TO_K1(MI_BASE_REG))($k0)
.LA4000AC0:
lw $ra, 0x1c($sp)
addiu $sp, $sp, 0x28
@@ -759,12 +776,12 @@ func_A4000AD0:
addiu $sp, $sp, -0x28
sw $ra, 0x1c($sp)
li $k0, 0x2000
lui $k1, %hi(MI_MODE_REG)
sw $k0, %lo(MI_MODE_REG)($k1)
lui $k1, %hi(PHYS_TO_K1(MI_BASE_REG))
sw $k0, %lo(PHYS_TO_K1(MI_BASE_REG))($k1)
move $fp, $zero
lw $fp, ($s5)
li $k0, 0x1000
sw $k0, %lo(MI_MODE_REG)($k1)
sw $k0, %lo(PHYS_TO_K1(MI_BASE_REG))($k1)
li $k1, 0x40
and $k1, $k1, $fp
srl $k1, $k1, 6
@@ -797,6 +814,8 @@ func_A4000AD0:
nop
nop
.end ipl3_entry
// 0xA4000B70-0xA4000FFF: IPL3 Font
glabel ipl3_font
.incbin "textures/ipl3_raw/ipl3_font_00.ia1"

3
include/n64/PR/ultratypes.h
View File

@@ -33,6 +33,7 @@
* General data types for R4300
*/
#ifndef _LANGUAGE_ASSEMBLY
typedef signed char s8;
typedef unsigned char u8;
typedef signed short int s16;
@@ -76,7 +77,7 @@ typedef volatile s8 vs8;
typedef volatile s16 vs16;
typedef volatile s32 vs32;
typedef volatile s64 vs64;
#endif // _LANGUAGE_ASSEMBLY
/*************************************************************************
* Common definitions

2
sm64.ld
View File

@@ -97,7 +97,7 @@ SECTIONS
BEGIN_SEG(boot, 0x04000000)
{
KEEP(BUILD_DIR/asm/rom_header.o(.text*));
KEEP(BUILD_DIR/asm/boot.o(.text*));
KEEP(BUILD_DIR/asm/ipl3.o(.text*));
}
END_SEG(boot)

61
undefined_syms.txt
View File

@@ -1,61 +0,0 @@
/* libultra OS symbols */
/* boot and osException symbols */
/* most of these should be in hardware.h */
/* exceptions */
EXCEPTION_TLB_MISS = 0x80000000;
/* SP */
SP_DMEM = 0xA4000000;
SP_DMEM_UNK0 = 0xA40004C0;
SP_DMEM_UNK1 = 0xA4000774;
SP_IMEM = 0xA4001000;
SP_STATUS_REG = 0xA4040010;
SP_PC = 0xA4080000;
/* MI */
MI_MODE_REG = 0xA4300000;
MI_VERSION_REG = 0xA4300004;
MI_INTR_REG = 0xA4300008;
MI_INTR_MASK_REG = 0xA430000C;
/* VI */
VI_CURRENT_REG = 0xA4400010;
/* AI */
AI_STATUS_REG = 0xA450000C;
/* PI */
PI_DRAM_ADDR_REG = 0xA4600000;
PI_CART_ADDR_REG = 0xA4600004;
PI_WR_LEN_REG = 0xA460000C;
PI_STATUS_REG = 0xA4600010;
PI_BSD_DOM1_LAT_REG = 0xA4600014;
PI_BSD_DOM1_PWD_REG = 0xA4600018;
PI_BSD_DOM1_PGS_REG = 0xA460001C;
PI_BSD_DOM1_RLS_REG = 0xA4600020;
/* RI */
RI_MODE_REG = 0xA4700000;
RI_REFRESH_REG = 0xA4700010;
/* SI */
SI_STATUS_REG = 0xA4800018;
/* Unknown */
D_B0000008 = 0xB0000008;
D_B0000010 = 0xB0000010;
D_B0000014 = 0xB0000014;
D_C0000000 = 0xC0000000;
D_C0000008 = 0xC0000008;
D_C000000C = 0xC000000C;