print_n_panic/Microtransactions64
0
0
Fork 0
mirror of https://github.com/Print-and-Panic/Microtransactions64.git synced 2026-01-21 10:17:19 -08:00
Code Issues Packages Projects Releases Wiki Activity

Antialiasing Changes

Browse Source
This commit is contained in:
Fazana
2021-08-15 17:26:38 +01:00
parent 78ebe1c617
commit 20ffa3de16
2 changed files with 81 additions and 120 deletions
Download Patch File Download Diff File Expand all files Collapse all files

152
include/n64/PR/gbi.h
View File

@@ -76,13 +76,13 @@
*
* IMPLEMENTATION NOTE:
* There is another group of RDP commands that includes the triangle commands
* generated by the RSP code. These are the raw commands the rasterizer
* hardware chews on, with slope info, etc. They will follow the RDP
* generated by the RSP code. These are the raw commands the rasterizer
* hardware chews on, with slope info, etc. They will follow the RDP
* ordering...
*
* IMPLEMENTATION NOTE:
* The RDP hardware has some of these bit patterns wired up. If the hardware
* changes, we must adjust this table, likewise we can't change/add things
* The RDP hardware has some of these bit patterns wired up. If the hardware
* changes, we must adjust this table, likewise we can't change/add things
* once the hardware is frozen. (actually, the RDP hardware only looks at
* the lower 6 bits of the command byte)
*
@@ -206,7 +206,7 @@
#define G_TEXRECT 0xe4 /* -28 */
/*
/*
* The following commands are the "generated" RDP commands; the user
* never sees them, the RSP microcode generates them.
*
@@ -326,7 +326,7 @@
*
* DO NOT USE THE LOW 8 BITS OF GEOMETRYMODE:
* The weird bit-ordering is for the micro-code: the lower byte
* can be OR'd in with G_TRI_SHADE (11001100) to construct
* can be OR'd in with G_TRI_SHADE (11001100) to construct
* the triangle command directly. Don't break it...
*
* DO NOT USE THE HIGH 8 BITS OF GEOMETRYMODE:
@@ -340,7 +340,7 @@
* appropriately and use primcolor to see anything.
*
* G_SHADING_SMOOTH enabled means use all 3 colors of the triangle.
* If it is not set, then do 'flat shading', where only one vertex color
* If it is not set, then do 'flat shading', where only one vertex color
* is used (and all 3 vertices are set to that same color by the ucode)
* See the man page for gSP1Triangle().
*
@@ -718,154 +718,162 @@
#define G_BL_1 2
#define G_BL_0 3
#ifdef DISABLE_AA
#define AA_DEF
#define RD_DEF
#else
#define AA_DEF AA_EN |
#define RD_DEF IM_RD |
#endif
#define GBL_c1(m1a, m1b, m2a, m2b) \
(m1a) << 30 | (m1b) << 26 | (m2a) << 22 | (m2b) << 18
#define GBL_c2(m1a, m1b, m2a, m2b) \
(m1a) << 28 | (m1b) << 24 | (m2a) << 20 | (m2b) << 16
#define RM_AA_ZB_OPA_SURF(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | RD_DEF CVG_DST_CLAMP | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_RA_ZB_OPA_SURF(clk) \
AA_EN | Z_CMP | Z_UPD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | CVG_DST_CLAMP | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_ZB_XLU_SURF(clk) \
AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | \
AA_DEF Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | \
FORCE_BL | ZMODE_XLU | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_OPA_DECAL(clk) \
AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | ALPHA_CVG_SEL | \
AA_DEF Z_CMP | RD_DEF CVG_DST_WRAP | ALPHA_CVG_SEL | \
ZMODE_DEC | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_RA_ZB_OPA_DECAL(clk) \
AA_EN | Z_CMP | CVG_DST_WRAP | ALPHA_CVG_SEL | \
AA_DEF Z_CMP | CVG_DST_WRAP | ALPHA_CVG_SEL | \
ZMODE_DEC | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_ZB_XLU_DECAL(clk) \
AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | \
AA_DEF Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | \
FORCE_BL | ZMODE_DEC | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_OPA_INTER(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | RD_DEF CVG_DST_CLAMP | \
ALPHA_CVG_SEL | ZMODE_INTER | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_RA_ZB_OPA_INTER(clk) \
AA_EN | Z_CMP | Z_UPD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | CVG_DST_CLAMP | \
ALPHA_CVG_SEL | ZMODE_INTER | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_ZB_XLU_INTER(clk) \
AA_EN | Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | \
AA_DEF Z_CMP | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | \
FORCE_BL | ZMODE_INTER | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_XLU_LINE(clk) \
AA_EN | Z_CMP | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | \
AA_DEF Z_CMP | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | \
ALPHA_CVG_SEL | FORCE_BL | ZMODE_XLU | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_DEC_LINE(clk) \
AA_EN | Z_CMP | IM_RD | CVG_DST_SAVE | CVG_X_ALPHA | \
AA_DEF Z_CMP | IM_RD | CVG_DST_SAVE | CVG_X_ALPHA | \
ALPHA_CVG_SEL | FORCE_BL | ZMODE_DEC | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_TEX_EDGE(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
AA_EN | Z_CMP | Z_UPD | RD_DEF CVG_DST_CLAMP | \
CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_ZB_TEX_INTER(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | RD_DEF CVG_DST_CLAMP | \
CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_INTER | TEX_EDGE | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_ZB_SUB_SURF(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_FULL | \
AA_DEF Z_CMP | Z_UPD | IM_RD | CVG_DST_FULL | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_ZB_PCL_SURF(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
ZMODE_OPA | G_AC_DITHER | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_OPA_TERR(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | RD_DEF CVG_DST_CLAMP | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_TEX_TERR(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_CLAMP | \
AA_DEF Z_CMP | Z_UPD | RD_DEF CVG_DST_CLAMP | \
CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_ZB_SUB_TERR(clk) \
AA_EN | Z_CMP | Z_UPD | IM_RD | CVG_DST_FULL | \
AA_DEF Z_CMP | Z_UPD | IM_RD | CVG_DST_FULL | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_OPA_SURF(clk) \
AA_EN | IM_RD | CVG_DST_CLAMP | \
AA_DEF RD_DEF CVG_DST_CLAMP | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_RA_OPA_SURF(clk) \
AA_EN | CVG_DST_CLAMP | \
AA_DEF CVG_DST_CLAMP | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_XLU_SURF(clk) \
AA_EN | IM_RD | CVG_DST_WRAP | CLR_ON_CVG | FORCE_BL | \
AA_DEF IM_RD | CVG_DST_WRAP | CLR_ON_CVG | FORCE_BL | \
ZMODE_OPA | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_XLU_LINE(clk) \
AA_EN | IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | \
AA_DEF IM_RD | CVG_DST_CLAMP | CVG_X_ALPHA | \
ALPHA_CVG_SEL | FORCE_BL | ZMODE_OPA | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_DEC_LINE(clk) \
AA_EN | IM_RD | CVG_DST_FULL | CVG_X_ALPHA | \
AA_DEF IM_RD | CVG_DST_FULL | CVG_X_ALPHA | \
ALPHA_CVG_SEL | FORCE_BL | ZMODE_OPA | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_TEX_EDGE(clk) \
AA_EN | IM_RD | CVG_DST_CLAMP | \
AA_EN | RD_DEF CVG_DST_CLAMP | \
CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_SUB_SURF(clk) \
AA_EN | IM_RD | CVG_DST_FULL | \
AA_DEF IM_RD | CVG_DST_FULL | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_AA_PCL_SURF(clk) \
AA_EN | IM_RD | CVG_DST_CLAMP | \
AA_DEF IM_RD | CVG_DST_CLAMP | \
ZMODE_OPA | G_AC_DITHER | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_OPA_TERR(clk) \
AA_EN | IM_RD | CVG_DST_CLAMP | \
AA_DEF RD_DEF CVG_DST_CLAMP | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_TEX_TERR(clk) \
AA_EN | IM_RD | CVG_DST_CLAMP | \
AA_DEF RD_DEF CVG_DST_CLAMP | \
CVG_X_ALPHA | ALPHA_CVG_SEL | ZMODE_OPA | TEX_EDGE | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_AA_SUB_TERR(clk) \
AA_EN | IM_RD | CVG_DST_FULL | \
AA_DEF IM_RD | CVG_DST_FULL | \
ZMODE_OPA | ALPHA_CVG_SEL | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
@@ -874,27 +882,27 @@
Z_CMP | Z_UPD | CVG_DST_FULL | ALPHA_CVG_SEL | \
ZMODE_OPA | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_ZB_XLU_SURF(clk) \
Z_CMP | IM_RD | CVG_DST_FULL | FORCE_BL | ZMODE_XLU | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_ZB_OPA_DECAL(clk) \
Z_CMP | CVG_DST_FULL | ALPHA_CVG_SEL | ZMODE_DEC | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_A_MEM)
#define RM_ZB_XLU_DECAL(clk) \
Z_CMP | IM_RD | CVG_DST_FULL | FORCE_BL | ZMODE_DEC | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_ZB_CLD_SURF(clk) \
Z_CMP | IM_RD | CVG_DST_SAVE | FORCE_BL | ZMODE_XLU | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_ZB_OVL_SURF(clk) \
Z_CMP | IM_RD | CVG_DST_SAVE | FORCE_BL | ZMODE_DEC | \
GBL_c##clk(G_BL_CLR_IN, G_BL_A_IN, G_BL_CLR_MEM, G_BL_1MA)
#define RM_ZB_PCL_SURF(clk) \
Z_CMP | Z_UPD | CVG_DST_FULL | ZMODE_OPA | \
G_AC_DITHER | \
@@ -1151,7 +1159,7 @@
* element, we can't depend on the C compiler to align things
* properly.
*
* 64-bit structure alignment is enforced by wrapping structures with
* 64-bit structure alignment is enforced by wrapping structures with
* unions that contain a dummy "long long int". Why this works is
* explained in the ANSI C Spec, or on page 186 of the second edition
* of K&R, "The C Programming Language".
@@ -1223,14 +1231,14 @@ typedef struct {
/* 20 bytes for above */
/* padding to bring structure size to 64 bit allignment */
char dummy[4];
char dummy[4];
} uSprite_t;
typedef union {
typedef union {
uSprite_t s;
/* Need to make sure this is 64 bit aligned */
/* Need to make sure this is 64 bit aligned */
long long int force_structure_allignment[3];
} uSprite;
@@ -1315,7 +1323,7 @@ typedef union {
*/
#ifdef F3DEX_GBI_2
/* 0,4 are reserved by G_MTX */
# define G_MV_MMTX 2
# define G_MV_MMTX 2
# define G_MV_PMTX 6
# define G_MV_VIEWPORT 8
# define G_MV_LIGHT 10
@@ -1373,7 +1381,7 @@ typedef union {
/*
* These are offsets from the address in the dmem table
*/
*/
#define G_MWO_NUMLIGHT 0x00
#define G_MWO_CLIP_RNX 0x04
#define G_MWO_CLIP_RNY 0x0c
@@ -1455,7 +1463,7 @@ typedef union {
*
* Note: only directional (infinite) lights are currently supported.
*
* Note: the weird order is for the DMEM alignment benefit of
* Note: the weird order is for the DMEM alignment benefit of
* the microcode.
*
*/
@@ -1775,7 +1783,7 @@ typedef struct {
/*
* Textured rectangles are 128 bits not 64 bits
*/
*/
typedef struct {
unsigned long w0;
unsigned long w1;
@@ -1933,7 +1941,7 @@ typedef union {
gsDma1p(G_VTX, v, sizeof(Vtx)*(n), ((n)-1)<<4|(v0))
#endif
#ifdef F3DEX_GBI_2
# define gSPViewport(pkt, v) \
gDma2p((pkt), G_MOVEMEM, (v), sizeof(Vp), G_MV_VIEWPORT, 0)
@@ -2192,7 +2200,7 @@ typedef union {
/***
*** 1 Triangle
***/
***/
#define gSP1Triangle(pkt, v0, v1, v2, flag) \
{ \
Gfx *_g = (Gfx *)(pkt); \
@@ -2368,7 +2376,7 @@ typedef union {
* Insert values into Matrix
*
* where = element of matrix (byte offset)
* num = new element (32 bit value replacing 2 int or 2 frac matrix
* num = new element (32 bit value replacing 2 int or 2 frac matrix
* componants
*/
#ifdef F3DEX_GBI_2
@@ -2396,7 +2404,7 @@ typedef union {
#define gsSPForceMatrix(mptr) \
gsDma2p(G_MOVEMEM,(mptr),sizeof(Mtx),G_MV_MATRIX,0), \
gsMoveWd(G_MW_FORCEMTX,0,0x00010000)
#else /* F3DEX_GBI_2 */
#define gSPForceMatrix(pkt, mptr) \
{ \
@@ -2444,7 +2452,7 @@ typedef union {
/*
* gSPBranchLessZ Branch DL if (vtx.z) less than or equal (zval).
*
* dl = DL branch to
* dl = DL branch to
* vtx = Vertex
* zval = Screen depth
* near = Near plane
@@ -2491,7 +2499,7 @@ typedef union {
/*
* gSPBranchLessZraw Branch DL if (vtx.z) less than or equal (raw zval).
*
* dl = DL branch to
* dl = DL branch to
* vtx = Vertex
* zval = Raw value of screen depth
*/
@@ -2592,7 +2600,7 @@ typedef union {
#define NUMLIGHTS_7 7
/*
* n should be one of: NUMLIGHTS_0, NUMLIGHTS_1, ..., NUMLIGHTS_7
* NOTE: in addition to the number of directional lights specified,
* NOTE: in addition to the number of directional lights specified,
* there is always 1 ambient light
*/
#define gSPNumLights(pkt, n) \
@@ -2604,7 +2612,7 @@ typedef union {
#define LIGHT_2 2
#define LIGHT_3 3
#define LIGHT_4 4
#define LIGHT_5 5
#define LIGHT_5 5
#define LIGHT_6 6
#define LIGHT_7 7
#define LIGHT_8 8
@@ -2829,7 +2837,7 @@ typedef union {
* min, max: range 0 to 1000: 0=nearplane, 1000=farplane
* min is where fog begins (usually less than max and often 0)
* max is where fog is thickest (usually 1000)
*
*
*/
#define gSPFogFactor(pkt, fm, fo) \
gMoveWd(pkt, G_MW_FOG, G_MWO_FOG, \
@@ -2869,7 +2877,7 @@ typedef union {
_SHIFTL((level),11,3) | _SHIFTL((tile),8,3) | _SHIFTL((on),1,7)),\
(_SHIFTL((s),16,16) | _SHIFTL((t),0,16)) \
}}
/*
/*
* Different version of SPTexture macro, has an additional parameter
* which is currently reserved in the microcode.
*/
@@ -2908,7 +2916,7 @@ typedef union {
_SHIFTL((level),11,3)|_SHIFTL((tile),8,3)|_SHIFTL((on),0,8)), \
(_SHIFTL((s),16,16)|_SHIFTL((t),0,16)) \
}}
/*
/*
* Different version of SPTexture macro, has an additional parameter
* which is currently reserved in the microcode.
*/
@@ -3135,7 +3143,7 @@ typedef union {
gsSPSetOtherMode(G_SETOTHERMODE_H, G_MDSFT_ALPHADITHER, 2, mode)
#endif
/* 'blendmask' is not supported anymore.
/* 'blendmask' is not supported anymore.
* The bits are reserved for future use.
* Fri May 26 13:45:55 PDT 1995
*/
@@ -3341,7 +3349,7 @@ typedef union {
*
* This command makes all othermode parameters set.
* Do not use this command in the same DL with another g*SPSetOtherMode DLs.
*
*
* [Usage]
* gDPSetOtherMode(pkt, modeA, modeB)
*
@@ -3594,9 +3602,9 @@ typedef union {
((height)-1) << G_TEXTURE_IMAGE_FRAC) \
}
/*
/*
* Allow tmem address and render tile to be specified.
* The S at the end means odd lines are already word Swapped
* The S at the end means odd lines are already word Swapped
*/
#define gDPLoadMultiBlockS(pkt, timg, tmem, rtile, fmt, siz, width, \
height, pal, cms, cmt, masks, maskt, shifts, shiftt) \
@@ -3812,13 +3820,13 @@ typedef union {
((width)-1) << G_TEXTURE_IMAGE_FRAC, \
((height)-1) << G_TEXTURE_IMAGE_FRAC)
/*
/*
* Allows tmem and render tile to be specified. Useful when loading
* several tiles at a time.
*
* Here is the static form of the pre-swapped texture block loading
* See gDPLoadTextureBlockS() for reference. Basically, just don't
* calculate DxT, use 0
* calculate DxT, use 0
*/
#define gsDPLoadMultiBlockS(timg, tmem, rtile, fmt, siz, width, height, \
@@ -3902,7 +3910,7 @@ typedef union {
}
/*
* 4-bit load block. Allows tmem and render tile to be specified. Useful when
* 4-bit load block. Allows tmem and render tile to be specified. Useful when
* loading multiple tiles. The S means odd lines are already word swapped.
*/
#define gDPLoadMultiBlock_4bS(pkt, timg, tmem, rtile, fmt, width, height,\
@@ -4337,7 +4345,7 @@ typedef union {
G_IM_FMT_RGBA, G_IM_SIZ_16b, 4*16, 1, \
pal, 0, 0, 0, 0, 0, 0)
#endif /* _HW_VERSION_1 */
#endif /* _HW_VERSION_1 */
/*
* Load a 256-entry palette (for 8-bit CI textures)
@@ -4379,7 +4387,7 @@ typedef union {
gsDPLoadSync(), \
gsDPLoadTLUTCmd(G_TX_LOADTILE, 255), \
gsDPPipeSync()
#else /* **** WORKAROUND hardware 1 load_tlut bug ****** */
#define gsDPLoadTLUT_pal256(dram) \
@@ -4434,7 +4442,7 @@ typedef union {
G_IM_FMT_RGBA, G_IM_SIZ_16b, 4, count, \
0, 0, 0, 0, 0, 0, 0)
#endif /* _HW_VERSION_1 */
#endif /* _HW_VERSION_1 */
#define gDPSetScissor(pkt, mode, ulx, uly, lrx, lry) \
{ \
@@ -4611,7 +4619,7 @@ typedef union {
}}
/* Notice that textured rectangles are 128-bit commands, therefore
* gsDPTextureRectangle() should not be used in display lists
* gsDPTextureRectangle() should not be used in display lists
* under normal circumstances (use gsSPTextureRectangle()).
* That is also why there is no gDPTextureRectangle() macros.
*/

49
src/game/rendering_graph_node.c
View File

@@ -78,52 +78,6 @@ struct RenderModeContainer {
};
/* Rendermode settings for cycle 1 for all 8 layers. */
#ifdef DISABLE_AA
struct RenderModeContainer renderModeTable_1Cycle[2] = { { {
G_RM_OPA_SURF,
G_RM_AA_OPA_SURF,
G_RM_AA_OPA_SURF,
G_RM_AA_OPA_SURF,
G_RM_AA_TEX_EDGE,
G_RM_AA_XLU_SURF,
G_RM_AA_XLU_SURF,
G_RM_AA_XLU_SURF,
} },
{ {
/* z-buffered */
G_RM_ZB_OPA_SURF,
G_RM_ZB_OPA_SURF,
G_RM_ZB_OPA_DECAL,
G_RM_AA_ZB_OPA_INTER,
G_RM_AA_ZB_TEX_EDGE,
G_RM_ZB_XLU_SURF,
G_RM_ZB_XLU_DECAL,
G_RM_AA_ZB_XLU_INTER,
} } };
/* Rendermode settings for cycle 2 for all 8 layers. */
struct RenderModeContainer renderModeTable_2Cycle[2] = { { {
G_RM_OPA_SURF2,
G_RM_AA_OPA_SURF2,
G_RM_AA_OPA_SURF2,
G_RM_AA_OPA_SURF2,
G_RM_AA_TEX_EDGE2,
G_RM_AA_XLU_SURF2,
G_RM_AA_XLU_SURF2,
G_RM_AA_XLU_SURF2,
} },
{ {
/* z-buffered */
G_RM_ZB_OPA_SURF2,
G_RM_ZB_OPA_SURF2,
G_RM_ZB_OPA_DECAL2,
G_RM_AA_ZB_OPA_INTER2,
G_RM_AA_ZB_TEX_EDGE2,
G_RM_ZB_XLU_SURF2,
G_RM_ZB_XLU_DECAL2,
G_RM_AA_ZB_XLU_INTER2,
} } };
#else
struct RenderModeContainer renderModeTable_1Cycle[2] = { { {
G_RM_OPA_SURF,
G_RM_AA_OPA_SURF,
@@ -168,7 +122,6 @@ struct RenderModeContainer renderModeTable_2Cycle[2] = { { {
G_RM_AA_ZB_XLU_DECAL2,
G_RM_AA_ZB_XLU_INTER2,
} } };
#endif
struct GraphNodeRoot *gCurGraphNodeRoot = NULL;
struct GraphNodeMasterList *gCurGraphNodeMasterList = NULL;
@@ -333,7 +286,7 @@ static void geo_process_level_of_detail(struct GraphNodeLevelOfDetail *node) {
#else
distanceFromCam = -gMatStack[gMatStackIndex][3][2];
#endif
if ((f32)node->minDistance <= distanceFromCam && distanceFromCam < (f32)node->maxDistance) {
if (node->node.children != 0) {
geo_process_node_and_siblings(node->node.children);