The engine is built for 32-bit constants which is wrong since Ballistic
is an ARM64 recompiler. Instructions like MOVZ with LSR #32 or LSR #48
would fail.
Signed-off-by: Ronald Caesar <github43132@proton.me>
An instruction is suppose to have 17-bit operands but it was actually
18-bit. So I reduce the bitfields by one bit and give the remaining bits
to opcode. An opcode is now 13 bits.
Signed-off-by: Ronald Caesar <github43132@proton.me>
Having 18-bit opcodes means a block has at most 131,072 instructions
which is simply too big. All of these instructions cannot fit into the
L1 cache, which results in cache thrashing.
Signed-off-by: Ronald Caesar <github43132@proton.me>
We have enough bits in the opcode bitfield in instruction_t
to encode register classes (ADD_INT, ADD_FLOAT, ADD_VECTOR). However,
encoding the bit width (ADD_INT8, ADD_INT32) will massively increase the
amount of opcodes needed. So we replace `type` in ssa_version_t with
`bit_width`.
Signed-off-by: Ronald Caesar <github43132@proton.me>
Rule 4.2 states: "If a basic block is deemed cold, it should move to a
separate buffer." This violates Rule 3.1 Implicit Indexing. If v100 is
located at instructions[100] and we move it to a cold buffer, it id no
longer at index 100. If we keep the index 100 but store the data
elsewhere, you break the linear memory array performance benefits.
Hot-cols splitting will be done during code generation.
Signed-off-by: Ronald Caesar <github43132@proton.me>
- Replace value-returning IFs with Void IFs and explicit OPCODE_MERGE.
- Move SSA definitions to block exits to eliminate backpatching.
- Formalize Control Scope Stack for tracking yields and arity.
- Update loop peeling logic to respect new merge semantics.
Signed-off-by: Ronald Caesar <github43132@proton.me>
Ronald Caesar
smiRaphi