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nvproxy: add ioctls required for Nvidia H100

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Co-authored-by: Malte Poll <mp@edgeless.systems>
This commit is contained in:
Otto Bittner
2024-02-16 16:19:21 +01:00
co-authored by Malte Poll
parent 568434b397
commit de23b3e85f
6 changed files with 52 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
pkg/abi/nvgpu/classes.go
+2
View File
@@ -43,9 +43,11 @@ const (
AMPERE_DMA_COPY_B = 0x0000c7b5
AMPERE_COMPUTE_B = 0x0000c7c0
HOPPER_DMA_COPY_A = 0x0000c8b5
HOPPER_CHANNEL_GPFIFO_A = 0x0000c86f
ADA_COMPUTE_A = 0x0000c9c0
NV_CONFIDENTIAL_COMPUTE = 0x0000cb33
HOPPER_COMPUTE_A = 0x0000cbc0
HOPPER_SEC2_WORK_LAUNCH_A = 0x0000cba2
)
// NV0005_ALLOC_PARAMETERS is the alloc params type for NV01_EVENT_OS_EVENT,
pkg/abi/nvgpu/ctrl.go
+14 -1
View File
@@ -132,6 +132,7 @@ const (
NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = 0x20801803
NV2080_CTRL_CMD_BUS_GET_INFO_V2 = 0x20801823
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = 0x2080182a
NV2080_CTRL_CMD_BUS_GET_C2C_INFO = 0x2080182b
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h:
@@ -151,6 +152,11 @@ const (
NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = 64
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h:
const (
NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = 0x20803125
)
// +marshal
type NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS struct {
BDisable uint8
@@ -257,6 +263,11 @@ const (
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = 0xc36f0108
)
// From src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h:
const (
NVC56F_CTRL_CMD_GET_KMB = 0xc56f010b
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl906f.h:
const (
NV906F_CTRL_CMD_RESET_CHANNEL = 0x906f0102
@@ -281,5 +292,7 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h:
const (
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = 0xcb330104
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = 0xcb33010b
)
pkg/abi/nvgpu/nvgpu.go
+5
View File
@@ -68,3 +68,8 @@ type RS_SHARE_POLICY struct {
Action uint8
Pad [1]byte
}
// NvUuid is defined in src/common/inc/nvCpuUuid.h.
//
// +marshal
type NvUuid [16]uint8
pkg/abi/nvgpu/uvm.go
+18 -8
View File
@@ -40,6 +40,7 @@ const (
UVM_REGISTER_GPU = 37
UVM_UNREGISTER_GPU = 38
UVM_PAGEABLE_MEM_ACCESS = 39
UVM_SET_PREFERRED_LOCATION = 42
UVM_DISABLE_READ_DUPLICATION = 45
UVM_MAP_DYNAMIC_PARALLELISM_REGION = 65
UVM_ALLOC_SEMAPHORE_POOL = 68
@@ -76,7 +77,7 @@ type UVM_DESTROY_RANGE_GROUP_PARAMS struct {
// +marshal
type UVM_REGISTER_GPU_VASPACE_PARAMS struct {
GPUUUID [16]uint8
GPUUUID NvUuid
RMCtrlFD int32
HClient Handle
HVASpace Handle
@@ -93,13 +94,13 @@ func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetRMCtrlFD(fd int32) {
// +marshal
type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct {
GPUUUID [16]uint8
GPUUUID NvUuid
RMStatus uint32
}
// +marshal
type UVM_REGISTER_CHANNEL_PARAMS struct {
GPUUUID [16]uint8
GPUUUID NvUuid
RMCtrlFD int32
HClient Handle
HChannel Handle
@@ -120,7 +121,7 @@ func (p *UVM_REGISTER_CHANNEL_PARAMS) SetRMCtrlFD(fd int32) {
// +marshal
type UVM_UNREGISTER_CHANNEL_PARAMS struct {
GPUUUID [16]uint8
GPUUUID NvUuid
HClient Handle
HChannel Handle
RMStatus uint32
@@ -157,7 +158,7 @@ type UVM_FREE_PARAMS struct {
// +marshal
type UVM_REGISTER_GPU_PARAMS struct {
GPUUUID [16]uint8
GPUUUID NvUuid
NumaEnabled uint8
Pad [3]byte
NumaNodeID int32
@@ -177,7 +178,7 @@ func (p *UVM_REGISTER_GPU_PARAMS) SetRMCtrlFD(fd int32) {
// +marshal
type UVM_UNREGISTER_GPU_PARAMS struct {
GPUUUID [16]uint8
GPUUUID NvUuid
RMStatus uint32
}
@@ -188,6 +189,15 @@ type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct {
RMStatus uint32
}
// +marshal
type UVM_SET_PREFERRED_LOCATION_PARAMS struct {
RequestedBase uint64
Length uint64
NvProcessorUUID NvUuid
RMStatus uint32
Pad0 [4]byte
}
// +marshal
type UVM_DISABLE_READ_DUPLICATION_PARAMS struct {
RequestedBase uint64
@@ -200,7 +210,7 @@ type UVM_DISABLE_READ_DUPLICATION_PARAMS struct {
type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct {
Base uint64
Length uint64
GPUUUID [16]uint8
GPUUUID NvUuid
RMStatus uint32
Pad0 [4]byte
}
@@ -243,7 +253,7 @@ const UVM_MAX_GPUS = NV_MAX_DEVICES
// +marshal
type UvmGpuMappingAttributes struct {
GPUUUID [16]byte
GPUUUID NvUuid
GPUMappingType uint32
GPUCachingType uint32
GPUFormatType uint32
pkg/sentry/devices/nvproxy/seccomp_filters.go
+4
View File
@@ -156,6 +156,10 @@ func Filters() seccomp.SyscallRules {
seccomp.NonNegativeFD{},
seccomp.EqualTo(nvgpu.UVM_PAGEABLE_MEM_ACCESS),
},
seccomp.PerArg{
seccomp.NonNegativeFD{},
seccomp.EqualTo(nvgpu.UVM_SET_PREFERRED_LOCATION),
},
seccomp.PerArg{
seccomp.NonNegativeFD{},
seccomp.EqualTo(nvgpu.UVM_DISABLE_READ_DUPLICATION),
pkg/sentry/devices/nvproxy/version.go
+9
View File
@@ -190,6 +190,7 @@ func Init() {
nvgpu.UVM_REGISTER_GPU: uvmIoctlHasRMCtrlFD[nvgpu.UVM_REGISTER_GPU_PARAMS],
nvgpu.UVM_UNREGISTER_GPU: uvmIoctlSimple[nvgpu.UVM_UNREGISTER_GPU_PARAMS],
nvgpu.UVM_PAGEABLE_MEM_ACCESS: uvmIoctlSimple[nvgpu.UVM_PAGEABLE_MEM_ACCESS_PARAMS],
nvgpu.UVM_SET_PREFERRED_LOCATION: uvmIoctlSimple[nvgpu.UVM_SET_PREFERRED_LOCATION_PARAMS],
nvgpu.UVM_DISABLE_READ_DUPLICATION: uvmIoctlSimple[nvgpu.UVM_DISABLE_READ_DUPLICATION_PARAMS],
nvgpu.UVM_MAP_DYNAMIC_PARALLELISM_REGION: uvmIoctlSimple[nvgpu.UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS],
nvgpu.UVM_ALLOC_SEMAPHORE_POOL: uvmIoctlSimple[nvgpu.UVM_ALLOC_SEMAPHORE_POOL_PARAMS],
@@ -223,9 +224,11 @@ func Init() {
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_BUS_GET_INFO_V2: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_BUS_GET_C2C_INFO: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_CE_GET_ALL_CAPS: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_FB_GET_INFO_V2: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFO_V2: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_GPU_GET_NAME_STRING: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING: rmControlSimple,
nvgpu.NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO: rmControlSimple,
@@ -292,6 +295,7 @@ func Init() {
nvgpu.KEPLER_CHANNEL_GROUP_A: rmAllocSimple[nvgpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS],
nvgpu.TURING_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS],
nvgpu.AMPERE_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS],
nvgpu.HOPPER_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS],
nvgpu.TURING_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS],
nvgpu.AMPERE_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS],
nvgpu.AMPERE_DMA_COPY_B: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS],
@@ -324,9 +328,13 @@ func Init() {
abi := v525_89_02()
abi.useRmAllocParamsV535 = true
abi.controlCmd[nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES] = rmControlSimple
abi.controlCmd[nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE] = rmControlSimple
abi.controlCmd[nvgpu.NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS] = rmControlSimple
abi.controlCmd[nvgpu.NVC56F_CTRL_CMD_GET_KMB] = rmControlSimple
abi.allocationClass[nvgpu.NV_CONFIDENTIAL_COMPUTE] = rmAllocSimple[nvgpu.NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS]
abi.allocationClass[nvgpu.NV50_P2P] = rmAllocSimple[nvgpu.NV503B_ALLOC_PARAMETERS_V535]
abi.allocationClass[nvgpu.NV_MEMORY_FABRIC] = rmAllocSimple[nvgpu.NV00F8_ALLOCATION_PARAMETERS_V535]
abi.allocationClass[nvgpu.HOPPER_SEC2_WORK_LAUNCH_A] = rmAllocNoParams
abi.uvmIoctl[nvgpu.UVM_MM_INITIALIZE] = uvmMMInitialize
return abi
}
@@ -338,6 +346,7 @@ func Init() {
abi := v535_54_03()
abi.allocationClass[nvgpu.TURING_CHANNEL_GPFIFO_A] = rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS_V535]
abi.allocationClass[nvgpu.AMPERE_CHANNEL_GPFIFO_A] = rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS_V535]
abi.allocationClass[nvgpu.HOPPER_CHANNEL_GPFIFO_A] = rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS_V535]
return abi
}
v535_104_05Checksum := "2f9d609d1da770beee757636635c46e7ed8253ade887b87c7a5482e33fcbedc9"