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Record driver struct names within nvproxy.

Browse Source 
This is a necessary addition to enable our Nvidia driver differ tool, and
in general to make it easier to keep nvproxy up to date with driver changes.

The current maps have been partially validated by the test in cl/655637570.

PiperOrigin-RevId: 657705274
This commit is contained in:
Anthony Cui
2024-07-30 13:16:27 -07:00
committed by gVisor bot
parent 03ec7d26e4
commit ced5d60576
6 changed files with 446 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files
pkg/abi/nvgpu/classes.go
+26 -26
View File
@@ -77,7 +77,7 @@ const (
//
// +marshal
type NV2081_ALLOC_PARAMETERS struct {
Reserved uint32
Reserved uint32 `nvproxy:"same"`
}
// NV0005_ALLOC_PARAMETERS is the alloc params type for NV01_EVENT_OS_EVENT,
@@ -85,7 +85,7 @@ type NV2081_ALLOC_PARAMETERS struct {
//
// +marshal
type NV0005_ALLOC_PARAMETERS struct {
HParentClient Handle
HParentClient Handle `nvproxy:"same"`
HSrcResource Handle
HClass uint32
NotifyIndex uint32
@@ -97,7 +97,7 @@ type NV0005_ALLOC_PARAMETERS struct {
//
// +marshal
type NV0080_ALLOC_PARAMETERS struct {
DeviceID uint32
DeviceID uint32 `nvproxy:"same"`
HClientShare Handle
HTargetClient Handle
HTargetDevice Handle
@@ -115,7 +115,7 @@ type NV0080_ALLOC_PARAMETERS struct {
//
// +marshal
type NV2080_ALLOC_PARAMETERS struct {
SubDeviceID uint32
SubDeviceID uint32 `nvproxy:"same"`
}
// NV_MEMORY_ALLOCATION_PARAMS is the alloc params type for various NV*_MEMORY*
@@ -123,7 +123,7 @@ type NV2080_ALLOC_PARAMETERS struct {
//
// +marshal
type NV_MEMORY_ALLOCATION_PARAMS struct {
Owner uint32
Owner uint32 `nvproxy:"same"`
Type uint32
Flags uint32
Width uint32
@@ -153,16 +153,16 @@ type NV_MEMORY_ALLOCATION_PARAMS struct {
//
// +marshal
type NV_MEMORY_ALLOCATION_PARAMS_V545 struct {
NV_MEMORY_ALLOCATION_PARAMS
NumaNode int32
_ uint32
NV_MEMORY_ALLOCATION_PARAMS `nvproxy:"NV_MEMORY_ALLOCATION_PARAMS"`
NumaNode int32
_ uint32
}
// NV503B_BAR1_P2P_DMA_INFO from src/common/sdk/nvidia/inc/class/cl503b.h.
//
// +marshal
type NV503B_BAR1_P2P_DMA_INFO struct {
DmaAddress uint64
DmaAddress uint64 `nvproxy:"same"`
DmaSize uint64
}
@@ -171,7 +171,7 @@ type NV503B_BAR1_P2P_DMA_INFO struct {
//
// +marshal
type NV503B_ALLOC_PARAMETERS struct {
HSubDevice Handle
HSubDevice Handle `nvproxy:"same"`
HPeerSubDevice Handle
SubDevicePeerIDMask uint32
PeerSubDevicePeerIDMask uint32
@@ -189,7 +189,7 @@ type NV503B_ALLOC_PARAMETERS struct {
//
// +marshal
type NV503C_ALLOC_PARAMETERS struct {
Flags uint32
Flags uint32 `nvproxy:"same"`
}
// NV83DE_ALLOC_PARAMETERS is the alloc params type for GT200_DEBUGGER,
@@ -197,7 +197,7 @@ type NV503C_ALLOC_PARAMETERS struct {
//
// +marshal
type NV83DE_ALLOC_PARAMETERS struct {
HDebuggerClient_Obsolete Handle
HDebuggerClient_Obsolete Handle `nvproxy:"same"`
HAppClient Handle
HClass3DObject Handle
}
@@ -207,7 +207,7 @@ type NV83DE_ALLOC_PARAMETERS struct {
//
// +marshal
type NV_CTXSHARE_ALLOCATION_PARAMETERS struct {
HVASpace Handle
HVASpace Handle `nvproxy:"same"`
Flags uint32
SubctxID uint32
}
@@ -217,7 +217,7 @@ type NV_CTXSHARE_ALLOCATION_PARAMETERS struct {
//
// +marshal
type NV_VASPACE_ALLOCATION_PARAMETERS struct {
Index uint32
Index uint32 `nvproxy:"same"`
Flags uint32
VASize uint64
VAStartInternal uint64
@@ -232,7 +232,7 @@ type NV_VASPACE_ALLOCATION_PARAMETERS struct {
//
// +marshal
type NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS struct {
HObjectError Handle
HObjectError Handle `nvproxy:"same"`
HObjectECCError Handle
HVASpace Handle
EngineType uint32
@@ -245,7 +245,7 @@ type NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS struct {
//
// +marshal
type NV_MEMORY_DESC_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Size uint64
AddressSpace uint32
CacheAttrib uint32
@@ -257,7 +257,7 @@ type NV_MEMORY_DESC_PARAMS struct {
//
// +marshal
type NV_CHANNEL_ALLOC_PARAMS struct {
HObjectError Handle
HObjectError Handle `nvproxy:"same"`
HObjectBuffer Handle
GPFIFOOffset uint64
GPFIFOEntries uint32
@@ -291,7 +291,7 @@ type NV_CHANNEL_ALLOC_PARAMS struct {
//
// +marshal
type NVB0B5_ALLOCATION_PARAMETERS struct {
Version uint32
Version uint32 `nvproxy:"same"`
EngineType uint32
}
@@ -300,7 +300,7 @@ type NVB0B5_ALLOCATION_PARAMETERS struct {
//
// +marshal
type NV_GR_ALLOCATION_PARAMETERS struct {
Version uint32
Version uint32 `nvproxy:"same"`
Flags uint32
Size uint32
Caps uint32
@@ -311,7 +311,7 @@ type NV_GR_ALLOCATION_PARAMETERS struct {
//
// +marshal
type NV_HOPPER_USERMODE_A_PARAMS struct {
Bar1Mapping uint8
Bar1Mapping uint8 `nvproxy:"same"`
Priv uint8
}
@@ -320,7 +320,7 @@ type NV_HOPPER_USERMODE_A_PARAMS struct {
//
// +marshal
type NV00DE_ALLOC_PARAMETERS struct {
Reserved uint32
Reserved uint32 `nvproxy:"same"`
}
// NV00DE_ALLOC_PARAMETERS_V545 is the updated version of
@@ -328,7 +328,7 @@ type NV00DE_ALLOC_PARAMETERS struct {
//
// +marshal
type NV00DE_ALLOC_PARAMETERS_V545 struct {
PolledDataMask uint64
PolledDataMask uint64 `nvproxy:"NV00DE_ALLOC_PARAMETERS"`
}
// +marshal
@@ -343,7 +343,7 @@ type nv00f8Map struct {
//
// +marshal
type NV00F8_ALLOCATION_PARAMETERS struct {
Alignment uint64
Alignment uint64 `nvproxy:"same"`
AllocSize uint64
PageSize uint64
AllocFlags uint32
@@ -370,7 +370,7 @@ type NV_EXPORT_MEM_PACKET struct {
//
// +marshal
type NV00FD_ALLOCATION_PARAMETERS struct {
Alignment uint64
Alignment uint64 `nvproxy:"same"`
AllocSize uint64
PageSize uint32
AllocFlags uint32
@@ -384,7 +384,7 @@ type NV00FD_ALLOCATION_PARAMETERS struct {
//
// +marshal
type NV00FD_ALLOCATION_PARAMETERS_V545 struct {
ExpPacket NV_EXPORT_MEM_PACKET
ExpPacket NV_EXPORT_MEM_PACKET `nvproxy:"NV00FD_ALLOCATION_PARAMETERS"`
Index uint16
_ [6]byte
NV00FD_ALLOCATION_PARAMETERS
@@ -395,6 +395,6 @@ type NV00FD_ALLOCATION_PARAMETERS_V545 struct {
//
// +marshal
type NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS struct {
Handle Handle
Handle Handle `nvproxy:"same"`
_ uint32
}
pkg/abi/nvgpu/ctrl.go
+14 -14
View File
@@ -97,7 +97,7 @@ const (
// +marshal
type NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS struct {
FD int32
FD int32 `nvproxy:"same"`
DeviceInstance uint32
MaxObjects uint16
Pad [2]byte
@@ -116,7 +116,7 @@ func (p *NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS) SetFrontendFD(fd int
// +marshal
type NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_V545 struct {
FD int32
FD int32 `nvproxy:"NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS"`
DeviceInstance uint32
GpuInstanceID uint32
MaxObjects uint16
@@ -145,7 +145,7 @@ type NV0000_CTRL_OS_UNIX_EXPORT_OBJECT struct {
// +marshal
type NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS struct {
Object NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
Object NV0000_CTRL_OS_UNIX_EXPORT_OBJECT `nvproxy:"same"`
FD int32
Flags uint32
}
@@ -162,7 +162,7 @@ func (p *NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS) SetFrontendFD(fd int32)
// +marshal
type NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS struct {
FD int32
FD int32 `nvproxy:"same"`
Object NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
}
@@ -178,7 +178,7 @@ func (p *NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS) SetFrontendFD(fd int3
// +marshal
type NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS struct {
SizeOfStrings uint32
SizeOfStrings uint32 `nvproxy:"same"`
Pad [4]byte
PDriverVersionBuffer P64
PVersionBuffer P64
@@ -194,7 +194,7 @@ const (
// +marshal
type NV0041_CTRL_GET_SURFACE_INFO_PARAMS struct {
SurfaceInfoListSize uint32
SurfaceInfoListSize uint32 `nvproxy:"same"`
Pad [4]byte
SurfaceInfoList P64
}
@@ -226,7 +226,7 @@ const (
// +marshal
type NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS struct {
NumChannels uint32
NumChannels uint32 `nvproxy:"same"`
Pad [4]byte
PChannelHandleList P64
PChannelList P64
@@ -243,7 +243,7 @@ const (
// +marshal
type NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS struct {
NumClasses uint32
NumClasses uint32 `nvproxy:"same"`
Pad [4]byte
ClassList P64
}
@@ -252,7 +252,7 @@ type NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS struct {
// +marshal
type NV0080_CTRL_GR_ROUTE_INFO struct {
Flags uint32
Flags uint32 `nvproxy:"same"`
Pad [4]byte
Route uint64
}
@@ -282,7 +282,7 @@ const (
// +marshal
type NV00FD_CTRL_ATTACH_GPU_PARAMS struct {
HSubDevice Handle
HSubDevice Handle `nvproxy:"same"`
Flags uint32
DevDescriptor uint64
}
@@ -294,7 +294,7 @@ const (
// +marshal
type NV2080_CTRL_BIOS_GET_INFO_PARAMS struct {
BiosInfoListSize uint32
BiosInfoListSize uint32 `nvproxy:"same"`
Pad [4]byte
BiosInfoList P64
}
@@ -352,7 +352,7 @@ const (
// +marshal
type NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS struct {
BDisable uint8
BDisable uint8 `nvproxy:"same"`
Pad1 [3]byte
NumChannels uint32
BOnlyDisableScheduling uint8
@@ -411,7 +411,7 @@ const (
// +marshal
type NV2080_CTRL_GR_GET_INFO_PARAMS struct {
GRInfoListSize uint32 // in elements
GRInfoListSize uint32 `nvproxy:"same"` // in elements
Pad [4]byte
GRInfoList P64
GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO
@@ -471,7 +471,7 @@ const (
// +marshal
type NV503C_CTRL_REGISTER_VA_SPACE_PARAMS struct {
HVASpace Handle
HVASpace Handle `nvproxy:"same"`
Pad [4]byte
VASpaceToken uint64
}
pkg/abi/nvgpu/frontend.go
+37 -54
View File
@@ -55,20 +55,18 @@ const (
// Frontend ioctl parameter structs, from src/common/sdk/nvidia/inc/nvos.h or
// kernel-open/common/inc/nv-ioctl.h.
// IoctlRegisterFD is nv_ioctl_register_fd_t, the parameter type for
// NV_ESC_REGISTER_FD.
// IoctlRegisterFD is the parameter type for NV_ESC_REGISTER_FD.
//
// +marshal
type IoctlRegisterFD struct {
CtlFD int32
CtlFD int32 `nvproxy:"nv_ioctl_register_fd_t"`
}
// IoctlAllocOSEvent is nv_ioctl_alloc_os_event_t, the parameter type for
// NV_ESC_ALLOC_OS_EVENT.
// IoctlAllocOSEvent is the parameter type for NV_ESC_ALLOC_OS_EVENT.
//
// +marshal
type IoctlAllocOSEvent struct {
HClient Handle
HClient Handle `nvproxy:"nv_ioctl_alloc_os_event_t"`
HDevice Handle
FD uint32
Status uint32
@@ -84,12 +82,11 @@ func (p *IoctlAllocOSEvent) SetFrontendFD(fd int32) {
p.FD = uint32(fd)
}
// IoctlFreeOSEvent is nv_ioctl_free_os_event_t, the parameter type for
// NV_ESC_FREE_OS_EVENT.
// IoctlFreeOSEvent is the parameter type for NV_ESC_FREE_OS_EVENT.
//
// +marshal
type IoctlFreeOSEvent struct {
HClient Handle
HClient Handle `nvproxy:"nv_ioctl_free_os_event_t"`
HDevice Handle
FD uint32
Status uint32
@@ -105,46 +102,42 @@ func (p *IoctlFreeOSEvent) SetFrontendFD(fd int32) {
p.FD = uint32(fd)
}
// RMAPIVersion is nv_rm_api_version_t, the parameter type for
// NV_ESC_CHECK_VERSION_STR.
// RMAPIVersion is the parameter type for NV_ESC_CHECK_VERSION_STR.
//
// +marshal
type RMAPIVersion struct {
Cmd uint32
Cmd uint32 `nvproxy:"nv_ioctl_rm_api_version_t"`
Reply uint32
VersionString [64]byte
}
// IoctlSysParams is nv_ioctl_sys_params_t, the parameter type for
// NV_ESC_SYS_PARAMS.
// IoctlSysParams is the parameter type for NV_ESC_SYS_PARAMS.
//
// +marshal
type IoctlSysParams struct {
MemblockSize uint64
MemblockSize uint64 `nvproxy:"nv_ioctl_sys_params_t"`
}
// IoctlWaitOpenComplete is nv_ioctl_wait_open_complete_t, the parameter type
// for NV_ESC_WAIT_OPEN_COMPLETE.
// IoctlWaitOpenComplete is the parameter type for NV_ESC_WAIT_OPEN_COMPLETE.
//
// +marshal
type IoctlWaitOpenComplete struct {
Rc int32
Rc int32 `nvproxy:"nv_ioctl_wait_open_complete_t"`
AdapterStatus uint32
}
// IoctlNVOS02ParametersWithFD is nv_ioctl_nvos2_parameters_with_fd, the
// parameter type for NV_ESC_RM_ALLOC_MEMORY.
// IoctlNVOS02ParametersWithFD is the parameter type for NV_ESC_RM_ALLOC_MEMORY.
//
// +marshal
type IoctlNVOS02ParametersWithFD struct {
Params NVOS02Parameters
Params NVOS02Parameters `nvproxy:"nv_ioctl_nvos02_parameters_with_fd"`
FD int32
Pad0 [4]byte
}
// +marshal
type NVOS02Parameters struct {
HRoot Handle
HRoot Handle `nvproxy:"NVOS02_PARAMETERS"`
HObjectParent Handle
HObjectNew Handle
HClass ClassID
@@ -156,12 +149,11 @@ type NVOS02Parameters struct {
Pad1 [4]byte
}
// NVOS00Parameters is NVOS00_PARAMETERS, the parameter type for
// NV_ESC_RM_FREE.
// NVOS00Parameters is the parameter type for NV_ESC_RM_FREE.
//
// +marshal
type NVOS00Parameters struct {
HRoot Handle
HRoot Handle `nvproxy:"NVOS00_PARAMETERS"`
HObjectParent Handle
HObjectOld Handle
Status uint32
@@ -190,12 +182,11 @@ func GetRmAllocParamObj(isNVOS64 bool) RmAllocParamType {
return &NVOS21Parameters{}
}
// NVOS21Parameters is NVOS21_PARAMETERS, one possible parameter type for
// NV_ESC_RM_ALLOC.
// NVOS21Parameters is one possible parameter type for NV_ESC_RM_ALLOC.
//
// +marshal
type NVOS21Parameters struct {
HRoot Handle
HRoot Handle `nvproxy:"NVOS21_PARAMETERS"`
HObjectParent Handle
HObjectNew Handle
HClass ClassID
@@ -251,12 +242,11 @@ func (n *NVOS21Parameters) ToOS64() NVOS64Parameters {
}
}
// NVOS55Parameters is NVOS55_PARAMETERS, the parameter type for
// NV_ESC_RM_DUP_OBJECT.
// NVOS55Parameters is the parameter type for NV_ESC_RM_DUP_OBJECT.
//
// +marshal
type NVOS55Parameters struct {
HClient Handle
HClient Handle `nvproxy:"NVOS55_PARAMETERS"`
HParent Handle
HObject Handle
HClientSrc Handle
@@ -265,23 +255,21 @@ type NVOS55Parameters struct {
Status uint32
}
// NVOS57Parameters is NVOS57_PARAMETERS, the parameter type for
// NV_ESC_RM_SHARE.
// NVOS57Parameters is the parameter type for NV_ESC_RM_SHARE.
//
// +marshal
type NVOS57Parameters struct {
HClient Handle
HClient Handle `nvproxy:"NVOS57_PARAMETERS"`
HObject Handle
SharePolicy RS_SHARE_POLICY
Status uint32
}
// NVOS32Parameters is NVOS32_PARAMETERS, the parameter type for
// NV_ESC_RM_VID_HEAP_CONTROL.
// NVOS32Parameters is the parameter type for NV_ESC_RM_VID_HEAP_CONTROL.
//
// +marshal
type NVOS32Parameters struct {
HRoot Handle
HRoot Handle `nvproxy:"NVOS32_PARAMETERS"`
HObjectParent Handle
Function uint32
HVASpace Handle
@@ -324,20 +312,19 @@ type NVOS32AllocSize struct {
CtagOffset uint32
}
// IoctlNVOS33ParametersWithFD is nv_ioctl_nvos33_parameters_with_fd, the
// parameter type for NV_ESC_RM_MAP_MEMORY, from
// src/nvidia/arch/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h.
// IoctlNVOS33ParametersWithFD is the parameter type for NV_ESC_RM_MAP_MEMORY,
// from src/nvidia/arch/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h.
//
// +marshal
type IoctlNVOS33ParametersWithFD struct {
Params NVOS33Parameters
Params NVOS33Parameters `nvproxy:"nv_ioctl_nvos33_parameters_with_fd"`
FD int32
Pad0 [4]byte
}
// +marshal
type NVOS33Parameters struct {
HClient Handle
HClient Handle `nvproxy:"NVOS33_PARAMETERS"`
HDevice Handle
HMemory Handle
Pad0 [4]byte
@@ -348,12 +335,11 @@ type NVOS33Parameters struct {
Flags uint32
}
// NVOS34Parameters is NVOS34_PARAMETERS, the parameter type for
// NV_ESC_RM_UNMAP_MEMORY.
// NVOS34Parameters is the parameter type for NV_ESC_RM_UNMAP_MEMORY.
//
// +marshal
type NVOS34Parameters struct {
HClient Handle
HClient Handle `nvproxy:"NVOS34_PARAMETERS"`
HDevice Handle
HMemory Handle
Pad0 [4]byte
@@ -362,12 +348,11 @@ type NVOS34Parameters struct {
Flags uint32
}
// NVOS54Parameters is NVOS54_PARAMETERS, the parameter type for
// NV_ESC_RM_CONTROL.
// NVOS54Parameters is the parameter type for NV_ESC_RM_CONTROL.
//
// +marshal
type NVOS54Parameters struct {
HClient Handle
HClient Handle `nvproxy:"NVOS54_PARAMETERS"`
HObject Handle
Cmd uint32
Flags uint32
@@ -376,12 +361,11 @@ type NVOS54Parameters struct {
Status uint32
}
// NVOS56Parameters is NVOS56_PARAMETERS, the parameter type for
// NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO.
// NVOS56Parameters is the parameter type for NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO.
//
// +marshal
type NVOS56Parameters struct {
HClient Handle
HClient Handle `nvproxy:"NVOS56_PARAMETERS"`
HDevice Handle
HMemory Handle
Pad0 [4]byte
@@ -391,13 +375,12 @@ type NVOS56Parameters struct {
Pad1 [4]byte
}
// NVOS64Parameters is NVOS64_PARAMETERS, one possible parameter type for
// NV_ESC_RM_ALLOC.
// NVOS64Parameters is one possible parameter type for NV_ESC_RM_ALLOC.
//
// +marshal
// +stateify savable
type NVOS64Parameters struct {
HRoot Handle
HRoot Handle `nvproxy:"NVOS64_PARAMETERS"`
HObjectParent Handle
HObjectNew Handle
HClass ClassID
pkg/abi/nvgpu/nvgpu.go
+1 -1
View File
@@ -32,7 +32,7 @@ const (
// +marshal
// +stateify savable
type Handle struct {
Val uint32
Val uint32 `nvproxy:"NvHandle"`
}
// String implements fmt.Stringer.String.
pkg/abi/nvgpu/uvm.go
+29 -29
View File
@@ -50,7 +50,7 @@ const (
// +marshal
type UVM_INITIALIZE_PARAMS struct {
Flags uint64
Flags uint64 `nvproxy:"same"`
RMStatus uint32
Pad0 [4]byte
}
@@ -62,21 +62,21 @@ const (
// +marshal
type UVM_CREATE_RANGE_GROUP_PARAMS struct {
RangeGroupID uint64
RangeGroupID uint64 `nvproxy:"same"`
RMStatus uint32
Pad0 [4]byte
}
// +marshal
type UVM_DESTROY_RANGE_GROUP_PARAMS struct {
RangeGroupID uint64
RangeGroupID uint64 `nvproxy:"same"`
RMStatus uint32
Pad0 [4]byte
}
// +marshal
type UVM_REGISTER_GPU_VASPACE_PARAMS struct {
GPUUUID NvUUID
GPUUUID NvUUID `nvproxy:"same"`
RMCtrlFD int32
HClient Handle
HVASpace Handle
@@ -95,13 +95,13 @@ func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetFrontendFD(fd int32) {
// +marshal
type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct {
GPUUUID NvUUID
GPUUUID NvUUID `nvproxy:"same"`
RMStatus uint32
}
// +marshal
type UVM_REGISTER_CHANNEL_PARAMS struct {
GPUUUID NvUUID
GPUUUID NvUUID `nvproxy:"same"`
RMCtrlFD int32
HClient Handle
HChannel Handle
@@ -124,7 +124,7 @@ func (p *UVM_REGISTER_CHANNEL_PARAMS) SetFrontendFD(fd int32) {
// +marshal
type UVM_UNREGISTER_CHANNEL_PARAMS struct {
GPUUUID NvUUID
GPUUUID NvUUID `nvproxy:"same"`
HClient Handle
HChannel Handle
RMStatus uint32
@@ -132,21 +132,21 @@ type UVM_UNREGISTER_CHANNEL_PARAMS struct {
// +marshal
type UVM_ENABLE_PEER_ACCESS_PARAMS struct {
GPUUUIDA NvUUID
GPUUUIDA NvUUID `nvproxy:"same"`
GPUUUIDB NvUUID
RMStatus uint32
}
// +marshal
type UVM_DISABLE_PEER_ACCESS_PARAMS struct {
GPUUUIDA NvUUID
GPUUUIDA NvUUID `nvproxy:"same"`
GPUUUIDB NvUUID
RMStatus uint32
}
// +marshal
type UVM_SET_RANGE_GROUP_PARAMS struct {
RangeGroupID uint64
RangeGroupID uint64 `nvproxy:"same"`
RequestedBase uint64
Length uint64
RMStatus uint32
@@ -155,7 +155,7 @@ type UVM_SET_RANGE_GROUP_PARAMS struct {
// +marshal
type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Length uint64
Offset uint64
PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes
@@ -178,7 +178,7 @@ func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) SetFrontendFD(fd int32) {
// +marshal
type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550 struct {
Base uint64
Base uint64 `nvproxy:"UVM_MAP_EXTERNAL_ALLOCATION_PARAMS"`
Length uint64
Offset uint64
PerGPUAttributes [UVM_MAX_GPUS_V2]UvmGpuMappingAttributes
@@ -201,7 +201,7 @@ func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550) SetFrontendFD(fd int32) {
// +marshal
type UVM_FREE_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Length uint64
RMStatus uint32
Pad0 [4]byte
@@ -209,7 +209,7 @@ type UVM_FREE_PARAMS struct {
// +marshal
type UVM_REGISTER_GPU_PARAMS struct {
GPUUUID NvUUID
GPUUUID NvUUID `nvproxy:"same"`
NumaEnabled uint8
Pad [3]byte
NumaNodeID int32
@@ -231,20 +231,20 @@ func (p *UVM_REGISTER_GPU_PARAMS) SetFrontendFD(fd int32) {
// +marshal
type UVM_UNREGISTER_GPU_PARAMS struct {
GPUUUID NvUUID
GPUUUID NvUUID `nvproxy:"same"`
RMStatus uint32
}
// +marshal
type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct {
PageableMemAccess uint8
PageableMemAccess uint8 `nvproxy:"same"`
Pad [3]byte
RMStatus uint32
}
// +marshal
type UVM_SET_PREFERRED_LOCATION_PARAMS struct {
RequestedBase uint64
RequestedBase uint64 `nvproxy:"same"`
Length uint64
PreferredLocation NvUUID
RMStatus uint32
@@ -253,7 +253,7 @@ type UVM_SET_PREFERRED_LOCATION_PARAMS struct {
// +marshal
type UVM_SET_PREFERRED_LOCATION_PARAMS_V550 struct {
RequestedBase uint64
RequestedBase uint64 `nvproxy:"UVM_SET_PREFERRED_LOCATION_PARAMS"`
Length uint64
PreferredLocation NvUUID
PreferredCPUNumaNode int32
@@ -262,7 +262,7 @@ type UVM_SET_PREFERRED_LOCATION_PARAMS_V550 struct {
// +marshal
type UVM_DISABLE_READ_DUPLICATION_PARAMS struct {
RequestedBase uint64
RequestedBase uint64 `nvproxy:"same"`
Length uint64
RMStatus uint32
Pad0 [4]byte
@@ -270,7 +270,7 @@ type UVM_DISABLE_READ_DUPLICATION_PARAMS struct {
// +marshal
type UVM_MIGRATE_RANGE_GROUP_PARAMS struct {
RangeGroupID uint64
RangeGroupID uint64 `nvproxy:"same"`
DestinationUUID NvUUID
RMStatus uint32
Pad0 [4]byte
@@ -278,7 +278,7 @@ type UVM_MIGRATE_RANGE_GROUP_PARAMS struct {
// +marshal
type UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS struct {
Buffer uint64
Buffer uint64 `nvproxy:"same"`
Size uint64
TargetVA uint64
BytesRead uint64
@@ -288,7 +288,7 @@ type UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS struct {
// +marshal
type UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS struct {
Buffer uint64
Buffer uint64 `nvproxy:"same"`
Size uint64
TargetVA uint64
BytesWritten uint64
@@ -298,7 +298,7 @@ type UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS struct {
// +marshal
type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Length uint64
GPUUUID NvUUID
RMStatus uint32
@@ -307,7 +307,7 @@ type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct {
// +marshal
type UVM_UNMAP_EXTERNAL_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Length uint64
GPUUUID NvUUID
RMStatus uint32
@@ -316,7 +316,7 @@ type UVM_UNMAP_EXTERNAL_PARAMS struct {
// +marshal
type UVM_ALLOC_SEMAPHORE_POOL_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Length uint64
PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes
GPUAttributesCount uint64
@@ -326,7 +326,7 @@ type UVM_ALLOC_SEMAPHORE_POOL_PARAMS struct {
// +marshal
type UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550 struct {
Base uint64
Base uint64 `nvproxy:"UVM_ALLOC_SEMAPHORE_POOL_PARAMS"`
Length uint64
PerGPUAttributes [UVM_MAX_GPUS_V2]UvmGpuMappingAttributes
GPUAttributesCount uint64
@@ -336,7 +336,7 @@ type UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550 struct {
// +marshal
type UVM_VALIDATE_VA_RANGE_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Length uint64
RMStatus uint32
Pad0 [4]byte
@@ -344,7 +344,7 @@ type UVM_VALIDATE_VA_RANGE_PARAMS struct {
// +marshal
type UVM_CREATE_EXTERNAL_RANGE_PARAMS struct {
Base uint64
Base uint64 `nvproxy:"same"`
Length uint64
RMStatus uint32
Pad0 [4]byte
@@ -352,7 +352,7 @@ type UVM_CREATE_EXTERNAL_RANGE_PARAMS struct {
// +marshal
type UVM_MM_INITIALIZE_PARAMS struct {
UvmFD int32
UvmFD int32 `nvproxy:"same"`
Status uint32
}
pkg/sentry/devices/nvproxy/version.go
+339 -2
View File
@@ -16,6 +16,7 @@ package nvproxy
import (
"fmt"
"reflect"
"strconv"
"strings"
@@ -102,6 +103,10 @@ type uvmIoctlHandler func(ui *uvmIoctlState) (uintptr, error)
// This indirection exists to avoid memory usage from unused driver ABIs.
type driverABIFunc func() *driverABI
// driverStructNamesFunc returns a mapping of struct names used by an ABI version.
// This indirection exists to avoid the memory usage from struct name maps if they are not used.
type driverStructNamesFunc func() *driverStructNames
// abiConAndChecksum couples the driver's abiConstructor to the SHA256 checksum of its linux .run
// driver installer file from NVIDIA.
type abiConAndChecksum struct {
@@ -126,8 +131,23 @@ type driverABI struct {
uvmIoctl map[uint32]uvmIoctlHandler
controlCmd map[uint32]controlCmdHandler
allocationClass map[nvgpu.ClassID]allocationClassHandler
getStructNames driverStructNamesFunc
}
// To help with verifying and supporting new driver versions, we want to keep
// track of all the driver structs that we currently support. We do so by mapping ioctl
// numbers to a list of struct names used by that ioctl.
type driverStructNames struct {
frontendNames map[uint32][]DriverStructName
uvmNames map[uint32][]DriverStructName
controlNames map[uint32][]DriverStructName
allocationNames map[nvgpu.ClassID][]DriverStructName
}
// DriverStructName is the name of a struct used by the Nvidia driver.
type DriverStructName = string
// abis is a global map containing all supported Nvidia driver ABIs. This is
// initialized on Init() and is immutable henceforth.
var abis map[DriverVersion]abiConAndChecksum
@@ -345,6 +365,202 @@ func Init() {
nvgpu.TURING_USERMODE_A: rmAllocNoParams,
nvgpu.HOPPER_SEC2_WORK_LAUNCH_A: rmAllocNoParams,
},
getStructNames: func() *driverStructNames {
return &driverStructNames{
frontendNames: map[uint32][]DriverStructName{
nvgpu.NV_ESC_CARD_INFO: simpleIoctl("nv_ioctl_card_info_t"),
nvgpu.NV_ESC_CHECK_VERSION_STR: getStructName(nvgpu.RMAPIVersion{}),
nvgpu.NV_ESC_ATTACH_GPUS_TO_FD: nil, // NvU32 array containing GPU IDs
nvgpu.NV_ESC_SYS_PARAMS: getStructName(nvgpu.IoctlSysParams{}),
nvgpu.NV_ESC_RM_DUP_OBJECT: getStructName(nvgpu.NVOS55Parameters{}),
nvgpu.NV_ESC_RM_SHARE: getStructName(nvgpu.NVOS57Parameters{}),
nvgpu.NV_ESC_RM_UNMAP_MEMORY: getStructName(nvgpu.NVOS34Parameters{}),
nvgpu.NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO: getStructName(nvgpu.NVOS56Parameters{}),
nvgpu.NV_ESC_REGISTER_FD: getStructName(nvgpu.IoctlRegisterFD{}),
nvgpu.NV_ESC_ALLOC_OS_EVENT: getStructName(nvgpu.IoctlAllocOSEvent{}),
nvgpu.NV_ESC_FREE_OS_EVENT: getStructName(nvgpu.IoctlFreeOSEvent{}),
nvgpu.NV_ESC_NUMA_INFO: nil, // nvproxy ignores this ioctl
nvgpu.NV_ESC_RM_ALLOC_MEMORY: getStructName(nvgpu.IoctlNVOS02ParametersWithFD{}),
nvgpu.NV_ESC_RM_FREE: getStructName(nvgpu.NVOS00Parameters{}),
nvgpu.NV_ESC_RM_CONTROL: getStructName(nvgpu.NVOS54Parameters{}),
nvgpu.NV_ESC_RM_ALLOC: append(getStructName(nvgpu.NVOS21Parameters{}), getStructName(nvgpu.NVOS64Parameters{})...),
nvgpu.NV_ESC_RM_VID_HEAP_CONTROL: getStructName(nvgpu.NVOS32Parameters{}),
nvgpu.NV_ESC_RM_MAP_MEMORY: getStructName(nvgpu.IoctlNVOS33ParametersWithFD{}),
},
uvmNames: map[uint32][]DriverStructName{
nvgpu.UVM_INITIALIZE: getStructName(nvgpu.UVM_INITIALIZE_PARAMS{}),
nvgpu.UVM_DEINITIALIZE: nil, // Doesn't have any params
nvgpu.UVM_CREATE_RANGE_GROUP: getStructName(nvgpu.UVM_CREATE_RANGE_GROUP_PARAMS{}),
nvgpu.UVM_DESTROY_RANGE_GROUP: getStructName(nvgpu.UVM_DESTROY_RANGE_GROUP_PARAMS{}),
nvgpu.UVM_REGISTER_GPU_VASPACE: getStructName(nvgpu.UVM_REGISTER_GPU_VASPACE_PARAMS{}),
nvgpu.UVM_UNREGISTER_GPU_VASPACE: getStructName(nvgpu.UVM_UNREGISTER_GPU_VASPACE_PARAMS{}),
nvgpu.UVM_REGISTER_CHANNEL: getStructName(nvgpu.UVM_REGISTER_CHANNEL_PARAMS{}),
nvgpu.UVM_UNREGISTER_CHANNEL: getStructName(nvgpu.UVM_UNREGISTER_CHANNEL_PARAMS{}),
nvgpu.UVM_ENABLE_PEER_ACCESS: getStructName(nvgpu.UVM_ENABLE_PEER_ACCESS_PARAMS{}),
nvgpu.UVM_DISABLE_PEER_ACCESS: getStructName(nvgpu.UVM_DISABLE_PEER_ACCESS_PARAMS{}),
nvgpu.UVM_SET_RANGE_GROUP: getStructName(nvgpu.UVM_SET_RANGE_GROUP_PARAMS{}),
nvgpu.UVM_MAP_EXTERNAL_ALLOCATION: getStructName(nvgpu.UVM_MAP_EXTERNAL_ALLOCATION_PARAMS{}),
nvgpu.UVM_FREE: getStructName(nvgpu.UVM_FREE_PARAMS{}),
nvgpu.UVM_REGISTER_GPU: getStructName(nvgpu.UVM_REGISTER_GPU_PARAMS{}),
nvgpu.UVM_UNREGISTER_GPU: getStructName(nvgpu.UVM_UNREGISTER_GPU_PARAMS{}),
nvgpu.UVM_PAGEABLE_MEM_ACCESS: getStructName(nvgpu.UVM_PAGEABLE_MEM_ACCESS_PARAMS{}),
nvgpu.UVM_SET_PREFERRED_LOCATION: getStructName(nvgpu.UVM_SET_PREFERRED_LOCATION_PARAMS{}),
nvgpu.UVM_DISABLE_READ_DUPLICATION: getStructName(nvgpu.UVM_DISABLE_READ_DUPLICATION_PARAMS{}),
nvgpu.UVM_MIGRATE_RANGE_GROUP: getStructName(nvgpu.UVM_MIGRATE_RANGE_GROUP_PARAMS{}),
nvgpu.UVM_MAP_DYNAMIC_PARALLELISM_REGION: getStructName(nvgpu.UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS{}),
nvgpu.UVM_UNMAP_EXTERNAL: getStructName(nvgpu.UVM_UNMAP_EXTERNAL_PARAMS{}),
nvgpu.UVM_ALLOC_SEMAPHORE_POOL: getStructName(nvgpu.UVM_ALLOC_SEMAPHORE_POOL_PARAMS{}),
nvgpu.UVM_VALIDATE_VA_RANGE: getStructName(nvgpu.UVM_VALIDATE_VA_RANGE_PARAMS{}),
nvgpu.UVM_CREATE_EXTERNAL_RANGE: getStructName(nvgpu.UVM_CREATE_EXTERNAL_RANGE_PARAMS{}),
nvgpu.UVM_MM_INITIALIZE: getStructName(nvgpu.UVM_MM_INITIALIZE_PARAMS{}),
},
controlNames: map[uint32][]DriverStructName{
nvgpu.NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE: simpleIoctl("NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS"),
nvgpu.NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY: simpleIoctl("NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS: simpleIoctl("NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO: simpleIoctl("NV0000_CTRL_GPU_GET_ID_INFO_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2: simpleIoctl("NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_PROBED_IDS: simpleIoctl("NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_ATTACH_IDS: simpleIoctl("NV0000_CTRL_GPU_ATTACH_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_DETACH_IDS: simpleIoctl("NV0000_CTRL_GPU_DETACH_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_PCI_INFO: simpleIoctl("NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE: simpleIoctl("NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE: simpleIoctl("NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO: simpleIoctl("NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS: simpleIoctl("NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2: simpleIoctl("NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS: simpleIoctl("NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX: simpleIoctl("NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_FEATURES: simpleIoctl("NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS"),
nvgpu.NV0080_CTRL_CMD_FB_GET_CAPS_V2: simpleIoctl("NV0080_CTRL_FB_GET_CAPS_V2_PARAMS"),
nvgpu.NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES: simpleIoctl("NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS"),
nvgpu.NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE: simpleIoctl("NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS"),
nvgpu.NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE: simpleIoctl("NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS"),
0x80028b: nil, // unknown, paramsSize == 1
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2: simpleIoctl("NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS"),
nvgpu.NV0080_CTRL_CMD_HOST_GET_CAPS_V2: simpleIoctl("NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS"),
nvgpu.NV00FD_CTRL_CMD_GET_INFO: simpleIoctl("NV00FD_CTRL_GET_INFO_PARAMS"),
nvgpu.NV00FD_CTRL_CMD_ATTACH_MEM: simpleIoctl("NV00FD_CTRL_ATTACH_MEM_PARAMS"),
nvgpu.NV00FD_CTRL_CMD_DETACH_MEM: simpleIoctl("NV00FD_CTRL_DETACH_MEM_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCI_INFO: simpleIoctl("NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO: simpleIoctl("NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BUS_GET_INFO_V2: simpleIoctl("NV2080_CTRL_BUS_GET_INFO_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS: simpleIoctl("NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BUS_GET_C2C_INFO: simpleIoctl("NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_CE_GET_ALL_CAPS: simpleIoctl("NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION: simpleIoctl("NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FB_GET_INFO_V2: simpleIoctl("NV2080_CTRL_FB_GET_INFO_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFO_V2: simpleIoctl("NV2080_CTRL_GPU_GET_INFO_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE: simpleIoctl("NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_NAME_STRING: simpleIoctl("NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING: simpleIoctl("NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS: simpleIoctl("NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES: simpleIoctl("NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION: simpleIoctl("NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION: nil, // undocumented; paramSize == 0
nvgpu.NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION: nil, // undocumented; paramSize == 0
nvgpu.NV2080_CTRL_CMD_GPU_GET_GID_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_GID_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION: simpleIoctl("NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION: simpleIoctl("NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT: nil, // No params.
nvgpu.NV2080_CTRL_CMD_GPU_GET_ENGINES_V2: simpleIoctl("NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS: simpleIoctl("NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_PIDS: simpleIoctl("NV2080_CTRL_GPU_GET_PIDS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_PID_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_PID_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG: simpleIoctl("NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO: simpleIoctl("NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE: simpleIoctl("NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE: simpleIoctl("NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER: simpleIoctl("NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_CAPS_V2: simpleIoctl("NV2080_CTRL_GR_GET_CAPS_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_GPC_MASK: simpleIoctl("NV2080_CTRL_GR_GET_GPC_MASK_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_TPC_MASK: simpleIoctl("NV2080_CTRL_GR_GET_TPC_MASK_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER: simpleIoctl("NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO: simpleIoctl("NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GSP_GET_FEATURES: simpleIoctl("NV2080_CTRL_GSP_GET_FEATURES_PARAMS"),
nvgpu.NV2080_CTRL_CMD_MC_GET_ARCH_INFO: simpleIoctl("NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS: simpleIoctl("NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS: simpleIoctl("NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS: simpleIoctl("NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_PERF_BOOST: simpleIoctl("NV2080_CTRL_PERF_BOOST_PARAMS"),
nvgpu.NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO: simpleIoctl("NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS: nil, // No params.
nvgpu.NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG: nil, // No params.
nvgpu.NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO: simpleIoctl("NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS"),
nvgpu.NV503C_CTRL_CMD_REGISTER_VIDMEM: simpleIoctl("NV503C_CTRL_REGISTER_VIDMEM_PARAMS"),
nvgpu.NV503C_CTRL_CMD_UNREGISTER_VIDMEM: simpleIoctl("NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS"),
nvgpu.NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK: simpleIoctl("NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS"),
nvgpu.NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES: simpleIoctl("NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS"),
nvgpu.NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES: simpleIoctl("NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS"),
nvgpu.NV906F_CTRL_GET_CLASS_ENGINEID: simpleIoctl("NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS"),
nvgpu.NV906F_CTRL_CMD_RESET_CHANNEL: simpleIoctl("NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS"),
nvgpu.NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK: simpleIoctl("NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS"),
nvgpu.NVC36F_CTRL_GET_CLASS_ENGINEID: simpleIoctl("NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS"),
nvgpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: simpleIoctl("NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS"),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES: simpleIoctl("NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS"),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE: simpleIoctl("NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS"),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS: simpleIoctl("NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS"),
nvgpu.NVA06C_CTRL_CMD_GPFIFO_SCHEDULE: simpleIoctl("NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS"),
nvgpu.NVA06C_CTRL_CMD_SET_TIMESLICE: simpleIoctl("NVA06C_CTRL_SET_TIMESLICE_PARAMS"),
nvgpu.NVA06C_CTRL_CMD_PREEMPT: simpleIoctl("NVA06C_CTRL_PREEMPT_PARAMS"),
nvgpu.NVA06F_CTRL_CMD_GPFIFO_SCHEDULE: simpleIoctl("NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS"),
nvgpu.NVC56F_CTRL_CMD_GET_KMB: simpleIoctl("NVC56F_CTRL_CMD_GET_KMB_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION: getStructName(nvgpu.NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS{}),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD: getStructName(nvgpu.NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS{}),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD: getStructName(nvgpu.NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS{}),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO: getStructName(nvgpu.NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS{}),
nvgpu.NV0041_CTRL_CMD_GET_SURFACE_INFO: getStructName(nvgpu.NV0041_CTRL_GET_SURFACE_INFO_PARAMS{}),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST: getStructName(nvgpu.NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS{}),
nvgpu.NV00FD_CTRL_CMD_ATTACH_GPU: getStructName(nvgpu.NV00FD_CTRL_ATTACH_GPU_PARAMS{}),
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: getStructName(nvgpu.NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS{}),
nvgpu.NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS: getStructName(nvgpu.NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS{}),
nvgpu.NV2080_CTRL_CMD_BIOS_GET_INFO: getStructName(nvgpu.NV2080_CTRL_BIOS_GET_INFO_PARAMS{}),
nvgpu.NV2080_CTRL_CMD_GR_GET_INFO: getStructName(nvgpu.NV2080_CTRL_GR_GET_INFO_PARAMS{}),
nvgpu.NV503C_CTRL_CMD_REGISTER_VA_SPACE: getStructName(nvgpu.NV503C_CTRL_REGISTER_VA_SPACE_PARAMS{}),
},
allocationNames: map[nvgpu.ClassID][]DriverStructName{
nvgpu.NV01_ROOT: getStructName(nvgpu.Handle{}),
nvgpu.NV01_ROOT_NON_PRIV: getStructName(nvgpu.Handle{}),
nvgpu.NV01_MEMORY_SYSTEM: getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS{}),
nvgpu.NV01_MEMORY_LOCAL_USER: getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS{}),
nvgpu.NV01_ROOT_CLIENT: getStructName(nvgpu.Handle{}),
nvgpu.NV01_EVENT_OS_EVENT: getStructName(nvgpu.NV0005_ALLOC_PARAMETERS{}),
nvgpu.NV2081_BINAPI: getStructName(nvgpu.NV2081_ALLOC_PARAMETERS{}),
nvgpu.NV01_DEVICE_0: getStructName(nvgpu.NV0080_ALLOC_PARAMETERS{}),
nvgpu.RM_USER_SHARED_DATA: getStructName(nvgpu.NV00DE_ALLOC_PARAMETERS{}),
nvgpu.NV_MEMORY_FABRIC: getStructName(nvgpu.NV00F8_ALLOCATION_PARAMETERS{}),
nvgpu.NV_MEMORY_MULTICAST_FABRIC: getStructName(nvgpu.NV00FD_ALLOCATION_PARAMETERS{}),
nvgpu.NV20_SUBDEVICE_0: getStructName(nvgpu.NV2080_ALLOC_PARAMETERS{}),
nvgpu.NV50_MEMORY_VIRTUAL: getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS{}),
nvgpu.NV50_P2P: getStructName(nvgpu.NV503B_ALLOC_PARAMETERS{}),
nvgpu.NV50_THIRD_PARTY_P2P: getStructName(nvgpu.NV503C_ALLOC_PARAMETERS{}),
nvgpu.GT200_DEBUGGER: getStructName(nvgpu.NV83DE_ALLOC_PARAMETERS{}),
nvgpu.FERMI_CONTEXT_SHARE_A: getStructName(nvgpu.NV_CTXSHARE_ALLOCATION_PARAMETERS{}),
nvgpu.FERMI_VASPACE_A: getStructName(nvgpu.NV_VASPACE_ALLOCATION_PARAMETERS{}),
nvgpu.KEPLER_CHANNEL_GROUP_A: getStructName(nvgpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS{}),
nvgpu.TURING_CHANNEL_GPFIFO_A: getStructName(nvgpu.NV_CHANNEL_ALLOC_PARAMS{}),
nvgpu.AMPERE_CHANNEL_GPFIFO_A: getStructName(nvgpu.NV_CHANNEL_ALLOC_PARAMS{}),
nvgpu.HOPPER_CHANNEL_GPFIFO_A: getStructName(nvgpu.NV_CHANNEL_ALLOC_PARAMS{}),
nvgpu.TURING_DMA_COPY_A: getStructName(nvgpu.NVB0B5_ALLOCATION_PARAMETERS{}),
nvgpu.AMPERE_DMA_COPY_A: getStructName(nvgpu.NVB0B5_ALLOCATION_PARAMETERS{}),
nvgpu.AMPERE_DMA_COPY_B: getStructName(nvgpu.NVB0B5_ALLOCATION_PARAMETERS{}),
nvgpu.HOPPER_DMA_COPY_A: getStructName(nvgpu.NVB0B5_ALLOCATION_PARAMETERS{}),
nvgpu.TURING_COMPUTE_A: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.AMPERE_COMPUTE_A: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.AMPERE_COMPUTE_B: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.ADA_COMPUTE_A: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.NV_CONFIDENTIAL_COMPUTE: getStructName(nvgpu.NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS{}),
nvgpu.HOPPER_COMPUTE_A: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.HOPPER_USERMODE_A: getStructName(nvgpu.NV_HOPPER_USERMODE_A_PARAMS{}),
nvgpu.GF100_SUBDEVICE_MASTER: nil, // No params
nvgpu.TURING_USERMODE_A: nil, // No params
nvgpu.HOPPER_SEC2_WORK_LAUNCH_A: nil, // No params
},
}
},
}
}
@@ -370,6 +586,20 @@ func Init() {
abi.allocationClass[nvgpu.NV01_MEMORY_SYSTEM] = rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS_V545]
abi.allocationClass[nvgpu.NV01_MEMORY_LOCAL_USER] = rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS_V545]
abi.allocationClass[nvgpu.NV50_MEMORY_VIRTUAL] = rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS_V545]
prevNames := abi.getStructNames
abi.getStructNames = func() *driverStructNames {
names := prevNames()
names.controlNames[nvgpu.NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO] = getStructName(nvgpu.NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_V545{})
names.allocationNames[nvgpu.RM_USER_SHARED_DATA] = getStructName(nvgpu.NV00DE_ALLOC_PARAMETERS_V545{})
names.allocationNames[nvgpu.NV_MEMORY_MULTICAST_FABRIC] = getStructName(nvgpu.NV00FD_ALLOCATION_PARAMETERS_V545{})
names.allocationNames[nvgpu.NV01_MEMORY_SYSTEM] = getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS_V545{})
names.allocationNames[nvgpu.NV01_MEMORY_LOCAL_USER] = getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS_V545{})
names.allocationNames[nvgpu.NV50_MEMORY_VIRTUAL] = getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS_V545{})
return names
}
return abi
}
@@ -385,20 +615,92 @@ func Init() {
// src/nvidia/src/kernel/rmapi/binary_api.c:binapiControl_IMPL().
abi.controlCmd[(nvgpu.NV2081_BINAPI<<16)|0x0108] = rmControlSimple
abi.uvmIoctl[nvgpu.UVM_SET_PREFERRED_LOCATION] = uvmIoctlSimple[nvgpu.UVM_SET_PREFERRED_LOCATION_PARAMS_V550]
prevNames := abi.getStructNames
abi.getStructNames = func() *driverStructNames {
names := prevNames()
names.frontendNames[nvgpu.NV_ESC_WAIT_OPEN_COMPLETE] = simpleIoctl("nv_ioctl_wait_open_complete_t")
names.controlNames[nvgpu.NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID] = simpleIoctl("NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS")
names.controlNames[nvgpu.NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID] = simpleIoctl("NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS")
names.controlNames[nvgpu.NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL] = simpleIoctl("NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS")
names.controlNames[nvgpu.NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE] = simpleIoctl("NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS")
// NV2081_BINAPI forwards all control commands to the GSP in
// src/nvidia/src/kernel/rmapi/binary_api.c:binapiControl_IMPL().
// As such, there are no structs defined in the driver for this.
names.controlNames[(nvgpu.NV2081_BINAPI<<16)|0x0108] = nil
names.uvmNames[nvgpu.UVM_SET_PREFERRED_LOCATION] = getStructName(nvgpu.UVM_SET_PREFERRED_LOCATION_PARAMS_V550{})
return names
}
return abi
}
v550_54_14 := addDriverABI(550, 54, 14, "8c497ff1cfc7c310fb875149bc30faa4fd26d2237b2cba6cd2e8b0780157cfe3", func() *driverABI {
v550_54_14 := func() *driverABI {
abi := v550_40_07()
abi.uvmIoctl[nvgpu.UVM_ALLOC_SEMAPHORE_POOL] = uvmIoctlSimple[nvgpu.UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550]
abi.uvmIoctl[nvgpu.UVM_MAP_EXTERNAL_ALLOCATION] = uvmIoctlHasFrontendFD[nvgpu.UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550]
prevNames := abi.getStructNames
abi.getStructNames = func() *driverStructNames {
names := prevNames()
names.uvmNames[nvgpu.UVM_ALLOC_SEMAPHORE_POOL] = getStructName(nvgpu.UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550{})
names.uvmNames[nvgpu.UVM_MAP_EXTERNAL_ALLOCATION] = getStructName(nvgpu.UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550{})
return names
}
return abi
})
}
_ = addDriverABI(550, 54, 14, "8c497ff1cfc7c310fb875149bc30faa4fd26d2237b2cba6cd2e8b0780157cfe3", v550_54_14)
v550_54_15 := addDriverABI(550, 54, 15, "2e859ae5f912a9a47aaa9b2d40a94a14f6f486b5d3b67c0ddf8b72c1c9650385", v550_54_14)
_ = addDriverABI(550, 90, 07, "51acf579d5a9884f573a1d3f522e7fafa5e7841e22a9cec0b4bbeae31b0b9733", v550_54_15)
})
}
// simpleIoctl simply returns a slice containing structName. This is used for ioctls that don't
// have a struct defined in nvproxy, but we know the driver struct name.
func simpleIoctl(structName string) []DriverStructName {
return []DriverStructName{structName}
}
// getStructName takes an instance of an nvproxy struct and reads the `nvproxy` tag to determine the
// struct name. If the tag is empty, then it returns nil.
func getStructName(params any) []DriverStructName {
paramType := reflect.TypeOf(params)
// Right now, we only expect parameter structs
if paramType.Kind() != reflect.Struct {
panic(fmt.Sprintf("expected struct, got %v", paramType.Kind()))
}
// Look through each field for the tag, panicking if there are not exactly one.
driverName, found := "", false
for i := 0; i < paramType.NumField(); i++ {
field := paramType.Field(i)
if name, ok := field.Tag.Lookup("nvproxy"); ok {
if found {
panic(fmt.Sprintf("multiple nvproxy tags for %v", paramType.Name()))
}
driverName = name
found = true
}
}
if !found {
panic(fmt.Sprintf("missing nvproxy tag for %v", paramType.Name()))
}
switch driverName {
case "":
return nil
case "same":
return []DriverStructName{paramType.Name()}
default:
return []DriverStructName{driverName}
}
}
// ForEachSupportDriver calls f on all supported drivers.
// Precondition: Init() must have been called.
func ForEachSupportDriver(f func(version DriverVersion, checksum string)) {
@@ -455,3 +757,38 @@ func SupportedIoctls(version DriverVersion) (frontendIoctls map[uint32]struct{},
}
return
}
// SupportedStructNames returns the list of struct names supported by the given driver version.
// It merges the frontend, uvm, control, and allocation names into one slice.
func SupportedStructNames(version DriverVersion) ([]DriverStructName, bool) {
namesCons, ok := abis[version]
if !ok {
return nil, false
}
abi := namesCons.cons()
names := abi.getStructNames()
var allNames []DriverStructName
for _, names := range names.frontendNames {
if names != nil {
allNames = append(allNames, names...)
}
}
for _, names := range names.uvmNames {
if names != nil {
allNames = append(allNames, names...)
}
}
for _, names := range names.controlNames {
if names != nil {
allNames = append(allNames, names...)
}
}
for _, names := range names.allocationNames {
if names != nil {
allNames = append(allNames, names...)
}
}
return allNames, true
}