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https://github.com/netbirdio/gvisor.git
synced 2026-05-22 17:12:49 -07:00
supporting sError injection step 2 on Arm64
I disabled DAIF(DEBUG, sError, IRQ, FIQ) in guest kernel mode, and enabled them in guest user mode. So, I can make sure all DAIF-s come from guest user mode, and then the case 'TestBounceStress' can passed on Arm64. Test steps: 1, cd pkg/sentry/platform/kvm 2, bazel test kvm_test --strip=never --test_output=streamed Signed-off-by: Bin Lu <bin.lu@arm.com>
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@@ -49,7 +49,7 @@ func bluepillArchEnter(context *arch.SignalContext64) (c *vCPU) {
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regs.Sp = context.Sp
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regs.Pc = context.Pc
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regs.Pstate = context.Pstate
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regs.Pstate &^= uint64(ring0.KernelFlagsClear)
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regs.Pstate &^= uint64(ring0.PsrFlagsClear)
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regs.Pstate |= ring0.KernelFlagsSet
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return
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}
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@@ -63,7 +63,7 @@ func bluepillArchExit(c *vCPU, context *arch.SignalContext64) {
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context.Sp = regs.Sp
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context.Pc = regs.Pc
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context.Pstate = regs.Pstate
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context.Pstate &^= uint64(ring0.UserFlagsClear)
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context.Pstate &^= uint64(ring0.PsrFlagsClear)
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context.Pstate |= ring0.UserFlagsSet
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lazyVfp := c.GetLazyVFP()
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@@ -41,7 +41,7 @@ func fpsimdPtr(addr *byte) *arch.FpsimdContext {
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func dieArchSetup(c *vCPU, context *arch.SignalContext64, guestRegs *userRegs) {
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// If the vCPU is in user mode, we set the stack to the stored stack
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// value in the vCPU itself. We don't want to unwind the user stack.
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if guestRegs.Regs.Pstate&ring0.PSR_MODE_MASK == ring0.PSR_MODE_EL0t {
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if guestRegs.Regs.Pstate&ring0.PsrModeMask == ring0.UserFlagsSet {
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regs := c.CPU.Registers()
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context.Regs[0] = regs.Regs[0]
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context.Sp = regs.Sp
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@@ -151,12 +151,6 @@ func (c *vCPU) initArchState() error {
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// the MMIO address base.
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arm64HypercallMMIOBase = toLocation
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data = ring0.PsrDefaultSet | ring0.KernelFlagsSet
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reg.id = _KVM_ARM64_REGS_PSTATE
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if err := c.setOneRegister(®); err != nil {
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return err
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}
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// Initialize the PCID database.
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if hasGuestPCID {
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// Note that NewPCIDs may return a nil table here, in which
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@@ -26,30 +26,31 @@ const (
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_PMD_PGT_SIZE = 0x4000
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_PTE_PGT_BASE = 0x7000
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_PTE_PGT_SIZE = 0x1000
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_PSR_D_BIT = 0x00000200
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_PSR_A_BIT = 0x00000100
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_PSR_I_BIT = 0x00000080
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_PSR_F_BIT = 0x00000040
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)
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const (
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// PSR bits
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PSR_MODE_EL0t = 0x00000000
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PSR_MODE_EL1t = 0x00000004
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PSR_MODE_EL1h = 0x00000005
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PSR_MODE_MASK = 0x0000000f
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// DAIF bits:debug, sError, IRQ, FIQ.
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_PSR_D_BIT = 0x00000200
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_PSR_A_BIT = 0x00000100
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_PSR_I_BIT = 0x00000080
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_PSR_F_BIT = 0x00000040
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_PSR_DAIF_SHIFT = 6
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_PSR_DAIF_MASK = 0xf << _PSR_DAIF_SHIFT
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// PSR bits.
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_PSR_MODE_EL0t = 0x00000000
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_PSR_MODE_EL1t = 0x00000004
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_PSR_MODE_EL1h = 0x00000005
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_PSR_MODE_MASK = 0x0000000f
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PsrFlagsClear = _PSR_MODE_MASK | _PSR_DAIF_MASK
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PsrModeMask = _PSR_MODE_MASK
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// KernelFlagsSet should always be set in the kernel.
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KernelFlagsSet = PSR_MODE_EL1h
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KernelFlagsSet = _PSR_MODE_EL1h | _PSR_D_BIT | _PSR_A_BIT | _PSR_I_BIT | _PSR_F_BIT
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// UserFlagsSet are always set in userspace.
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UserFlagsSet = PSR_MODE_EL0t
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KernelFlagsClear = PSR_MODE_MASK
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UserFlagsClear = PSR_MODE_MASK
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PsrDefaultSet = _PSR_D_BIT | _PSR_A_BIT | _PSR_I_BIT | _PSR_F_BIT
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UserFlagsSet = _PSR_MODE_EL0t
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)
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// Vector is an exception vector.
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@@ -312,12 +312,6 @@
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ISB $15; \
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DSB $15;
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#define IRQ_ENABLE \
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MSR $2, DAIFSet;
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#define IRQ_DISABLE \
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MSR $2, DAIFClr;
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#define VFP_ENABLE \
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MOVD $FPEN_ENABLE, R0; \
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WORD $0xd5181040; \ //MSR R0, CPACR_EL1
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@@ -509,8 +503,6 @@ TEXT ·kernelExitToEl1(SB),NOSPLIT,$0
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// Start is the CPU entrypoint.
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TEXT ·Start(SB),NOSPLIT,$0
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IRQ_DISABLE
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// Init.
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MOVD $SCTLR_EL1_DEFAULT, R1
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MSR R1, SCTLR_EL1
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@@ -56,7 +56,7 @@ func (c *CPU) SwitchToUser(switchOpts SwitchOpts) (vector Vector) {
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// Sanitize registers.
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regs := switchOpts.Registers
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regs.Pstate &= ^uint64(UserFlagsClear)
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regs.Pstate &= ^uint64(PsrFlagsClear)
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regs.Pstate |= UserFlagsSet
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SetTLS(regs.TPIDR_EL0)
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