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Merge pull request #1460 from lubinszARM:pr_clean_code1

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PiperOrigin-RevId: 287221280
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gVisor bot
2019-12-26 13:42:39 -08:00
parent 87e4d03fdf 7b83d21856
commit 7b5a59d503
2 changed files with 9 additions and 2 deletions
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pkg/sentry/platform/ring0/entry_arm64.s
+4
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@@ -554,6 +554,10 @@ TEXT ·Vectors(SB),NOSPLIT,$0
B ·El0_error_invalid(SB)
nop31Instructions()
// The exception-vector-table is required to be 11-bits aligned.
// Please see Linux source code as reference: arch/arm64/kernel/entry.s.
// For gvisor, I defined it as 4K in length, filled the 2nd 2K part with NOPs.
// So that, I can safely move the 1st 2K part into the address with 11-bits alignment.
WORD $0xd503201f //nop
nop31Instructions()
WORD $0xd503201f
pkg/sentry/platform/ring0/lib_arm64.s
+5 -2
View File
@@ -12,12 +12,15 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include "funcdata.h"
#include "textflag.h"
TEXT ·CPACREL1(SB),NOSPLIT,$0-8
WORD $0xd5381041 // MRS CPACR_EL1, R1
MOVD R1, ret+0(FP)
RET
TEXT ·FPCR(SB),NOSPLIT,$0-8
TEXT ·GetFPCR(SB),NOSPLIT,$0-8
WORD $0xd53b4201 // MRS NZCV, R1
MOVD R1, ret+0(FP)
RET
@@ -27,7 +30,7 @@ TEXT ·GetFPSR(SB),NOSPLIT,$0-8
MOVD R1, ret+0(FP)
RET
TEXT ·FPCR(SB),NOSPLIT,$0-8
TEXT ·SetFPCR(SB),NOSPLIT,$0-8
MOVD addr+0(FP), R1
WORD $0xd51b4201 // MSR R1, NZCV
RET