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Merge pull request #4040 from lemin9538:lemin_arm64

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PiperOrigin-RevId: 336362818
This commit is contained in:
gVisor bot
2020-10-09 14:14:03 -07:00
parent 6bbf662271 190cf30e41
commit 6df400dfb6
3 changed files with 18 additions and 10 deletions
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pkg/sentry/platform/kvm/kvm_const_arm64.go
+14 -7
View File
@@ -101,13 +101,20 @@ const (
// Arm64: Memory Attribute Indirection Register EL1.
const (
_MT_DEVICE_nGnRnE = 0
_MT_DEVICE_nGnRE = 1
_MT_DEVICE_GRE = 2
_MT_NORMAL_NC = 3
_MT_NORMAL = 4
_MT_NORMAL_WT = 5
_MT_EL1_INIT = (0 << _MT_DEVICE_nGnRnE) | (0x4 << _MT_DEVICE_nGnRE * 8) | (0xc << _MT_DEVICE_GRE * 8) | (0x44 << _MT_NORMAL_NC * 8) | (0xff << _MT_NORMAL * 8) | (0xbb << _MT_NORMAL_WT * 8)
_MT_DEVICE_nGnRnE = 0
_MT_DEVICE_nGnRE = 1
_MT_DEVICE_GRE = 2
_MT_NORMAL_NC = 3
_MT_NORMAL = 4
_MT_NORMAL_WT = 5
_MT_ATTR_DEVICE_nGnRnE = 0x00
_MT_ATTR_DEVICE_nGnRE = 0x04
_MT_ATTR_DEVICE_GRE = 0x0c
_MT_ATTR_NORMAL_NC = 0x44
_MT_ATTR_NORMAL_WT = 0xbb
_MT_ATTR_NORMAL = 0xff
_MT_ATTR_MASK = 0xff
_MT_EL1_INIT = (_MT_ATTR_DEVICE_nGnRnE << (_MT_DEVICE_nGnRnE * 8)) | (_MT_ATTR_DEVICE_nGnRE << (_MT_DEVICE_nGnRE * 8)) | (_MT_ATTR_DEVICE_GRE << (_MT_DEVICE_GRE * 8)) | (_MT_ATTR_NORMAL_NC << (_MT_NORMAL_NC * 8)) | (_MT_ATTR_NORMAL << (_MT_NORMAL * 8)) | (_MT_ATTR_NORMAL_WT << (_MT_NORMAL_WT * 8))
)
const (
pkg/sentry/platform/ring0/entry_arm64.s
+2 -1
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@@ -47,8 +47,9 @@
#define SCTLR_C 1 << 2
#define SCTLR_I 1 << 12
#define SCTLR_UCT 1 << 15
#define SCTLR_UCI 1 << 26
#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT)
#define SCTLR_EL1_DEFAULT (SCTLR_M | SCTLR_C | SCTLR_I | SCTLR_UCT | SCTLR_UCI)
// cntkctl_el1: counter-timer kernel control register el1.
#define CNTKCTL_EL0PCTEN 1 << 0
pkg/sentry/platform/ring0/pagetables/pagetables_aarch64.go
+2 -2
View File
@@ -78,7 +78,7 @@ const (
const (
executeDisable = xn
optionMask = 0xfff | 0xfff<<48
optionMask = 0xfff | 0xffff<<48
protDefault = accessed | shared
)
@@ -188,7 +188,7 @@ func (p *PTE) Set(addr uintptr, opts MapOpts) {
v |= mtNormal
} else {
v = v &^ user
v |= mtDevicenGnRE // Strong order for the addresses with ring0.KernelStartAddress.
v |= mtNormal
}
atomic.StoreUintptr((*uintptr)(p), v)
}