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arm64:place an SB sequence following an ERET instruction

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Some CPUs(eg: ampere-emag) can speculate past an ERET instruction and potentially perform
speculative accesses to memory before processing the exception return.
Since the register state is often controlled by a lower privilege level
at the point of an ERET, this could potentially be used as part of a
side-channel attack.

Signed-off-by: Bin Lu <bin.lu@arm.com>
This commit is contained in:
Bin Lu
2020-09-10 02:47:13 -04:00
parent 1ab097b08f
commit 6d68834779
1 changed files with 3 additions and 1 deletions
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pkg/sentry/platform/ring0/entry_arm64.s
+3 -1
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@@ -27,7 +27,9 @@
// ERET returns using the ELR and SPSR for the current exception level.
#define ERET() \
WORD $0xd69f03e0
WORD $0xd69f03e0; \
DSB $7; \
ISB $15;
// RSV_REG is a register that holds el1 information temporarily.
#define RSV_REG R18_PLATFORM