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https://github.com/netbirdio/gvisor.git
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Merge pull request #8001 from avagin:go118-vs-kvm
PiperOrigin-RevId: 475584583
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@@ -47,12 +47,14 @@ func El0_irq_invalid()
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func El0_fiq_invalid()
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func El0_error_invalid()
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func Vectors()
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func vectors()
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func AddrOfVectors() uintptr
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// Start is the CPU entrypoint.
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// start is the CPU entrypoint.
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//
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// The CPU state will be set to c.Registers().
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func Start()
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func start()
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func AddrOfStart() uintptr
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func kernelExitToEl1()
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func kernelExitToEl0()
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+16
-4
@@ -611,8 +611,8 @@ TEXT ·kernelExitToEl1(SB),NOSPLIT,$0
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ERET()
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// Start is the CPU entrypoint.
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TEXT ·Start(SB),NOSPLIT,$0
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// start is the CPU entrypoint.
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TEXT ·start(SB),NOSPLIT,$0
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// Init.
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WORD $0xd508871f // __tlbi(vmalle1)
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DSB $7 // dsb(nsh)
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@@ -646,6 +646,12 @@ TEXT ·Start(SB),NOSPLIT,$0
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B ·kernelExitToEl1(SB)
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// func AddrOfStart() uintptr
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TEXT ·AddrOfStart(SB), $0-8
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MOVD $·start(SB), R0
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MOVD R0, ret+0(FP)
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RET
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// El1_sync_invalid is the handler for an invalid EL1_sync.
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TEXT ·El1_sync_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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@@ -839,12 +845,12 @@ TEXT ·El0_fiq_invalid(SB),NOSPLIT,$0
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TEXT ·El0_error_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// Vectors implements exception vector table.
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// vectors implements exception vector table.
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// The start address of exception vector table should be 11-bits aligned.
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// For detail, please refer to arm developer document:
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// https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table
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// Also can refer to the code in linux kernel: arch/arm64/kernel/entry.S
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TEXT ·Vectors(SB),NOSPLIT,$0
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TEXT ·vectors(SB),NOSPLIT,$0
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PCALIGN $2048
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B ·El1_sync_invalid(SB)
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PCALIGN $128
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@@ -880,3 +886,9 @@ TEXT ·Vectors(SB),NOSPLIT,$0
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B ·El0_fiq_invalid(SB)
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PCALIGN $128
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B ·El0_error_invalid(SB)
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// func AddrOfVectors() uintptr
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TEXT ·AddrOfVectors(SB), $0-8
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MOVD $·vectors(SB), R0
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MOVD R0, ret+0(FP)
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RET
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@@ -122,7 +122,7 @@ func (c *vCPU) initArchState() error {
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// pc
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reg.id = _KVM_ARM64_REGS_PC
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data = uint64(reflect.ValueOf(ring0.Start).Pointer())
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data = uint64(ring0.AddrOfStart())
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if err := c.setOneRegister(®); err != nil {
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return err
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}
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@@ -136,7 +136,7 @@ func (c *vCPU) initArchState() error {
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// vbar_el1
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reg.id = _KVM_ARM64_REGS_VBAR_EL1
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vectorLocation := reflect.ValueOf(ring0.Vectors).Pointer()
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vectorLocation := ring0.AddrOfVectors()
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data = uint64(ring0.KernelStartAddress | vectorLocation)
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if err := c.setOneRegister(®); err != nil {
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return err
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@@ -33,7 +33,7 @@ TEXT ·AddrOfGetpid(SB),NOSPLIT,$0-8
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MOVD R0, ret+0(FP)
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RET
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TEXT ·Touch(SB),NOSPLIT,$0
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TEXT ·touch(SB),NOSPLIT,$0
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start:
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MOVD 0(R8), R1
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MOVD $SYS_GETPID, R8 // getpid
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@@ -41,37 +41,37 @@ start:
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B start
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TEXT ·AddrOfTouch(SB),NOSPLIT,$0-8
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MOVD $·Touch(SB), R0
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MOVD $·touch(SB), R0
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MOVD R0, ret+0(FP)
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RET
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TEXT ·HaltLoop(SB),NOSPLIT,$0
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TEXT ·haltLoop(SB),NOSPLIT,$0
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start:
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HLT
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B start
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TEXT ·AddOfHaltLoop(SB),NOSPLIT,$0-8
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MOVD $·HaltLoop(SB), R0
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MOVD $·haltLoop(SB), R0
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MOVD R0, ret+0(FP)
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RET
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// This function simulates a loop of syscall.
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TEXT ·SyscallLoop(SB),NOSPLIT,$0
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TEXT ·syscallLoop(SB),NOSPLIT,$0
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start:
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SVC
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B start
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TEXT ·AddrOfSyscallLoop(SB),NOSPLIT,$0-8
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MOVD $·SyscallLoop(SB), R0
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MOVD $·syscallLoop(SB), R0
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MOVD R0, ret+0(FP)
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RET
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TEXT ·SpinLoop(SB),NOSPLIT,$0
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TEXT ·spinLoop(SB),NOSPLIT,$0
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start:
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B start
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TEXT ·AddrOfSpinLoop(SB),NOSPLIT,$0-8
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MOVD $·SpinLoop(SB), R0
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MOVD $·spinLoop(SB), R0
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MOVD R0, ret+0(FP)
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RET
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@@ -143,7 +143,7 @@ isNaN:
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MVN R29, R29; \
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MVN R30, R30;
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TEXT ·TwiddleRegsSyscall(SB),NOSPLIT,$0
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TEXT ·twiddleRegsSyscall(SB),NOSPLIT,$0
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TWIDDLE_REGS()
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MSR R10, TPIDR_EL0
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// Trapped in el0_svc.
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@@ -151,11 +151,11 @@ TEXT ·TwiddleRegsSyscall(SB),NOSPLIT,$0
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RET // never reached
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TEXT ·AddrOfTwiddleRegsSyscall(SB),NOSPLIT,$0-8
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MOVD $·TwiddleRegsSyscall(SB), R0
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MOVD $·twiddleRegsSyscall(SB), R0
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MOVD R0, ret+0(FP)
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RET
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TEXT ·TwiddleRegsFault(SB),NOSPLIT,$0
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TEXT ·twiddleRegsFault(SB),NOSPLIT,$0
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TWIDDLE_REGS()
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MSR R10, TPIDR_EL0
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// Trapped in el0_ia.
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@@ -164,6 +164,6 @@ TEXT ·TwiddleRegsFault(SB),NOSPLIT,$0
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RET // never reached
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TEXT ·AddrOfTwiddleRegsFault(SB),NOSPLIT,$0-8
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MOVD $·TwiddleRegsFault(SB), R0
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MOVD $·twiddleRegsFault(SB), R0
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MOVD R0, ret+0(FP)
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RET
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