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cad/verilator: Fix run-time by adding missing include

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PR:		286973
Reported by:	Joel Bodenmann
This commit is contained in:
Yuri Victorovich
2025-05-21 08:20:53 -07:00
parent cb3c7e9eae
commit f2a3aae778
2 changed files with 7 additions and 1 deletions
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cad/verilator/Makefile
+4
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@@ -1,8 +1,12 @@
PORTNAME= verilator
DISTVERSIONPREFIX= v
DISTVERSION= 5.036
PORTREVISION= 1
CATEGORIES= cad
PATCH_SITES= https://github.com/${GH_ACCOUNT}/${PORTNAME}/commit/
PATCHFILES= d94ed785888614cd53379b9faf58dfbde8f06b6f.patch:-p1 # https://github.com/verilator/verilator/pull/6028
MAINTAINER= yuri@FreeBSD.org
COMMENT= Synthesizable Verilog to C++ compiler
WWW= https://www.veripool.org/verilator/ \
cad/verilator/distinfo
+3 -1
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@@ -1,3 +1,5 @@
TIMESTAMP = 1745827619
TIMESTAMP = 1747840694
SHA256 (verilator-verilator-v5.036_GH0.tar.gz) = 4199964882d56cf6a19ce80c6a297ebe3b0c35ea81106cd4f722342594337c47
SIZE (verilator-verilator-v5.036_GH0.tar.gz) = 35527368
SHA256 (d94ed785888614cd53379b9faf58dfbde8f06b6f.patch) = 6b4c604ff4b08ad76431fb0cf11858c0313db04cd6e539db9a3fbad5a03f2784
SIZE (d94ed785888614cd53379b9faf58dfbde8f06b6f.patch) = 972