27 Commits
Author SHA1 Message Date
LePresidente df9323a47f Fixes required by python3. 2019-04-20 14:00:14 +02:00
Sebastian Graf ef3129004a Update ud_opcode.py to also support Python 3.x
Hit this on Arch, which uses Python 3 as default interpreter. The scripts should either call `/usr/bin/python2` instead of just `/usr/bin/python` or this script must be updated. The proposed change(s) in particular:

    * `dict.iteritems()` has been replaced by `dict.items()`, which returns a lazy view instead. `itemslist()` resolves this.
2014-02-03 01:46:32 +01:00
Vivek Thampi c98c3ecc29 Disable logging in ud_opcode.py 2013-11-14 03:33:35 -08:00
Vivek Thampi 431bbb8718 Fix incorrect parsing of cpuid in optable.xml
This fixes issue #65, and also included are minor updates to some
test operand cases.
2013-11-14 02:18:04 -08:00
Vivek Thampi 6b7484bc74 Clean up AVX definitions
AVX definitions should no longer include the "c4" or "c5" opcode
bytes.
2013-08-31 11:32:43 -07:00
Vivek Thampi 88bb68bb46 Add all remaining avx instructions 2013-07-07 01:56:50 -07:00
Vivek Thampi e22ec01cd9 Add support for avx instructions "vm" 2013-07-06 22:03:06 -07:00
Vivek Thampi ba284d1921 Add support for new operand types and sizes in opcode table generator 2013-07-06 12:43:56 -07:00
Vivek Thampi cb356500db Add support for 3rd source operand in avx insns 2013-06-29 14:46:32 -07:00
Vivek Thampi 571b3540d0 Fix decoding of YMM registers 2013-06-05 01:30:36 -07:00
Vivek Thampi 6b0319eab8 Rename class to cpuid in optable 2013-06-02 14:36:25 -07:00
Vivek Thampi de825118f5 Optimize /sse=none entries for space 2013-06-01 19:33:48 -07:00
Vivek Thampi 009056b570 Remove ud_optable.py 2013-06-01 18:28:54 -07:00
Vivek Thampi 0770fe6652 Remove table/insn ids 2013-06-01 17:53:53 -07:00
Vivek Thampi 120401e728 Minor cleanup of ud_opcode.py 2013-06-01 17:05:51 -07:00
Vivek Thampi 46241034b4 Minor fix 2013-06-01 13:46:57 -07:00
Vivek Thampi 4492592e95 stash avx changes 2013-05-08 01:29:35 +05:30
Vivek Thampi 9e85b89fd4 Merge branch 'master' into avx 2013-05-03 00:03:36 +05:30
Vivek Thampi 71ccf8ab4a Use standard notation for sse opcode extension (/sse=66,f3,f2) 2013-04-20 19:59:50 +05:30
Vivek Thampi ccd8d3b46b Python 3.0 compatibility changes 2013-02-10 14:38:38 -08:00
Vivek Thampi bc843d6793 Opcode encoding for inv64 2013-02-09 17:41:13 -08:00
Vivek Thampi c60e7fe262 Skip intel specific isntruction in testing for now 2013-02-04 00:16:05 -08:00
Vivek Thampi 28dc6be94c Make sse prefixes opcode extensions
This change makes sse prefixes (that disambiguate 2+ opcode bytes
instructions) act like rest of the opcode extensions. Importantly,
see prefix tables are now created towards the lower part of the
opcode tree.

However, note that SSE prefixes *must* be evaluated before the
operand size based disambiguation. This is because one the sse
prefix is consumed, it is discarded. So, in the case of the 66
prefix, which doubles as operand size override, it must be
consumed before operand size disambiguation.
2012-05-29 01:36:50 -07:00
Vivek Thampi db56ebd4de Cleanup opcode table layout
Refactor the opcode lookup mechanism, plus some minor fixes along
the way.
2012-05-29 01:35:48 -07:00
Vivek Thampi eae139047f Hand-merge patch from Jose Fonseca, that,
- Fixes: documentation
    - Adds: support for pextrb

    Additionally,

    - Add support for new operand type MbRv, since
      in pextrb, if the target operand is a register
      the default operand size is 64bit (in 64bit mode)
    - Add pextrd, pextrq
    - Add test cases for the above
2009-08-20 04:10:50 +05:30