When gdb loads an elf file of a newer or older version of the firmware
being debugged, or when the firmware is not running yet, there's a high
probability of FreeRTOS variables to be read incorrectly, thus leading to
an attempt to allocate an enourmous amount of memory. Without this check
OpenOCD simply crashes and that's mad confusing.
Change-Id: I404a072e886d2d47d9d942cfaea8417eb8bd4a5d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/520
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The {read,write}_mem32 interface functions was asking a 32 bits buffer
but they don't need 32 bits alignment.
This will change the interface to a 8 bits buffer to remove the
alignment mismatch warning. This was causing build errors on platforms
with strict aliasing rules.
Change-Id: I338be8df5686f07a64ddb4f17c1bb494af583999
Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Reviewed-on: http://openocd.zylin.com/483
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch checks the received register length with the local
configured register length and disconnect on a length missmatch.
Change-Id: I6b112c6b55a9ffb4526f582a384ffa91dc8b792f
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/517
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch add floating point register read/write
functionality through the SCS debug interface.
Change-Id: Id20e109dd7cccba00671d55ca8aabeb4936cceb9
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/512
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch determine all cpu types and not only
the cortex M3 and the stm32 target use the common
target examine function from the cortex_m sources.
Change-Id: If689dd994b3855284b927fc4b206f420cf32b6c7
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/511
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch fix the slow flash write issue on pflash only devices.
The Family Reference Manual says:
For devices with FlexNVM: FlexRAM
For devices with program flash only: Programming acceleration RAM
So the acceleration RAM is available for the flash section command on
this device.
Change-Id: If6541a23a4457c5ed8858848a145f35cac63138b
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/509
Tested-by: jenkins
Reviewed-by: Tomas Frydrych <tf+openocd@r-finger.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch prepend the v1 mass storage protocol to the command
buffer and simplify the usb read/write handling.
Change-Id: I709602600e93cd1eb5848fa9f4d15659ba85eb35
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/506
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This driver provides support for the P&E Micro OSBDM adapter (sometimes
named as OSJTAG), mounted on the Freescale TWRK60N512 bord. Thus, it
provides a quick start when working with this board. The driver doesn't
use BDM commands, but work with OSBDM adapter using only JTAG commands.
Change-Id: Ibc3779538e666e07651d3136431e5d44344f3b07
Signed-off-by: Jan Dakinevich <jan.dakinevich@gmail.com>
Reviewed-on: http://openocd.zylin.com/492
Tested-by: jenkins
Reviewed-by: Tomas Frydrych <tf+openocd@r-finger.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Atmel introduced 7 new Cortex-M3 processors on 2012-02-28
SAM3X4C - 256KB flash
SAM3X4E - 256KB flash
SAM3X8C - 512KB flash
SAM3X8E - 512KB flash
SAM3X8H (Only on dev-kit - not in production...) - 512KB flash
SAM3A4C - 256KB flash
SAM3A8C - 256KB flash
The SAM3X/A processors still suffer from the "6 waitstates needed
to program device" errata.
The CIDR address for the SAM3X/A processors are different from the
other SAM3 processors. Unfortunately, the chip identification register
is not at a constant address across all of the SAM3 series'. As a
consequence, a simple heuristic is used to find where it's
at... If the contents at the first address is zero, then we know
that the second address is where the chip id register is.
We can deduce this because for those SAM's that have the chip id @ 0x400e0940,
the first address, 0x400e0740, is located in the memory map of the Power
Management Controller (PMC). Furthermore, the address is not used by the PMC.
So when read, the memory controller returns zero.
Another interesting change is the flash bank address for flash bank 1.
It is not fixed at 0x00100000 like the Sam3U. Bank 1 of the at91sam3a/x
series starts at 0x00080000 + half the total flash size. Thus for the 256KB
devices Bank 1 is located at 0x000A0000, and for the 512KB devices Bank 1 is
located at 0x000C0000.
The configuration files for the SAM3X/A processors will follow
Change-Id: I6c3a707c00e05d993a2ad1d5a423f23b37ffd553
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/505
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
arm7_9_prepare_reset_halt is long since gone and the functionality
is implemented in the target's assert_reset handler.
Change-Id: Ib03c730cb39d68e5e3bb42f92af13daf8074e4e2
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/515
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
even the AT91EB40a's flash is covered by CFI and nobody ever submitted
any other drivers based on eCos code. It's just possible that this
idea was missing documentation and "marketing", but it's in git if
somebody wants to resurrect it.
Change-Id: I66449aa6e0997301f9d67f28098789bfc891d6e9
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/502
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
target_call_event_callbacks needs to be called after debug entry otherwise
we will get a console pc mismatch.
Change-Id: I278137736d5e85ca9662c306f6ac81336d8eb6cf
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/499
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
The SUPC (Supply Controller) registers are on different base addresses on different
SAM3 chips:
SAM3U: 0x400e1210
SAM3N: 0x400e1410
SAM3S: 0x400e1410
This creates a problem with the sam3_reg_list array which is const, but would need
to be changed at runtime to account for this variability. As this register is not
used anywhere, it's simplest to just remove it.
Change-Id: I987eb371648d826aa6d5e9de18d38c7bb66d6fca
Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/495
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Lock region count and sector sizes did not match datasheet.
(see 6500C-ATARM-8FE11 "SAM3S Series Datasheet", Table 7-1)
Change-Id: Ic511802f96ed03856467a24a6736349205a0576a
Signed-off-by: Attila Kinali <attila@kinali.ch>
Reviewed-on: http://openocd.zylin.com/493
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
