Also refuse 'flash protect' on any nRF52.
Fail protection check on nRF52840 until ACL protection is implemented.
Change-Id: I84fcf117427e4894147c3ad92e2a3597566b4fcf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4864
Tested-by: jenkins
nrf5 flash driver detected devices by looking up the HWID in the table
of known devices. Unfortunately chips are produced with many different
HWIDs for each type.
All nRF52 devices have FICR INFO field suitable for device identification
without need of HWID lookup.
Some newer nRF51 devices have FICR INFO too although undocumented.
Use this information to identify the device.
nrf5_info() is reworked to show just concise info.
Decoding FICR and UICR registers was moved from nrf5_info()
to a new command 'nrf5 info' without functional changes.
The flash bank for UICR page has the same size as program flash sector.
Change-Id: I900095b9ae23ee995f8e2bef8539b75d00300da5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4848
Tested-by: jenkins
nRF5 flash controller can write a word at a time. Ask flash
infrastructure to handle alignment and padding.
Fix mixing of offset and address in nrf5_ll_flash_write()
- the original code worked just because NRF5_FLASH_BASE is 0
Change-Id: Ibe8bdf899a1764cf4117b2deda1a4618eeb16697
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4819
Tested-by: jenkins
Starting from glibc 2.30, the header file sys/sysctl.h gets
deprecated on Linux, after the commit 744e82963716 ("Linux:
Deprecate <sys/sysctl.h> and sysctl")
https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=744e82963716
The associated NEWS reports
The Linux-specific <sys/sysctl.h> header and the sysctl
function have been deprecated and will be removed from a
future version of glibc.
Latest automake 1.16.1 still does not handle this case.
Current OpenOCD build fails with warning and requires configure
with "--disable-werror" to build.
Prevent including sys/sysctl.h on Linux build.
Change-Id: I5310976573352a96e5aef123352f73475f0c35fe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5317
Tested-by: jenkins
Reviewed-by: Moritz Fischer <moritz.fischer.private@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
OpenOCD can be targeted by a Cross Protocol Scripting attack from
a web browser running malicious code, such as the following PoC:
var x = new XMLHttpRequest();
x.open("POST", "http://127.0.0.1:4444", true);
x.send("exec xcalc\r\n");
This mitigation should provide some protection from browser-based
attacks and is based on the corresponding fix in Redis:
8075572207/src/networking.c (L1758)
Change-Id: Ia96ebe19b74b5805dc228bf7364c7971a90a4581
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reported-by: Josef Gajdusek <atx@atx.name>
Reviewed-on: http://openocd.zylin.com/4335
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
If a new JTAG command is added, then GCC will complain that
enumeration value not handled in switch. This is the only driver not
to have a default case, so add it.
Change-Id: Icb838087bb7525d057a911bd256300e256da1668
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://openocd.zylin.com/5333
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
If a new JTAG command is added, then GCC will complain that
enumeration value not handled in switch. Make this consistent with
other drivers, and add a 'default' case.
Change-Id: I66d6d0db3fcae93ea246f2d4882ffff5dec14693
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://openocd.zylin.com/5340
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
In preparation for supporting the ARM MCRR and MRRC commands which will
require using two 32-bit registers to read/write a 64-bit internal
register, extract the common logic to read/write from/to a register
to/from DCC and make that parameterized such that we can do this through
not just r0.
Change-Id: Iadb73f5cde8cf5961b5a18ddd198bf39d791e610
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/5227
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The variable gw16012_port is of type uint16_t.
There is no need for a cast to print it.
Change the format modifier to PRIx16
Change-Id: I16fe688b9d235bae46525635d07849a00fba9548
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5195
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
GDB uses the vRun packet if available to restart a running process in
extended remote mode. Support this like the R packet and set the
semihosting command-line to allow it to be specified from GDB.
Change-Id: I9cb812b22170630f782113c9927e46e0cd5b1f0f
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/5186
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Armv7a is able to read and write memory at un-aligned address, but
only when bit SCTLR.A (Alignment check enable) is zero and the
address belongs to a memory space with attribute "Normal" (see [1]
chapter A3.2.1 "Unaligned data access"). In all the other cases
the memory access will trigger an alignment fault data abort
exception.
Memory attributes are explained in [1] chapter A3.5 "Memory types
and attributes and the memory order model".
Disabling the MMU cause a change in memory attribute, as explained
in [1] chapter B3.2 "The effects of disabling MMUs on VMSA
behavior".
This can cause several issues. e.g. a SW breakpoint on un-aligned
4-byte Thumb instruction, set when MMU is on, can be impossible to
remove when MMU turns off.
While is possible to check all the possible conditions before an
un-aligned memory access, it's clearly more maintainable to skip
such complexity and only perform aligned accesses.
Check the alignment and eventually modify the data size before
calling the functions cortex_a_{read,write}_cpu_memory_slow().
Change the comment in the two functions above to comply with the
new behaviour.
[1] ARM DDI 0406C.d - "ARM Architecture Reference Manual, ARMv7-A
and ARMv7-R edition"
Change-Id: I57b4c11e7fa7e78aaaaee4406a5734b48db740ae
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5138
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Issue has been found when I tried to read 64 MiB QSPI flash bank.
Bank is memory mapped, default_flash_read() is used for 'flash read_bank'
command. OpenOCD consumed as much as 6.8 GiB of RAM during this
process. Investigation showed that this happens because JTAG queue
is not limited in any way. OpenOCD queues 16 millions of AP reads
allocating all corresponding data structures.
Most of this memory is allocated in:
cmd_queue_alloc (commands.c) - 4.2 GiB
dap_cmd_new (adi_v5_jtag.c) - 2.25GiB
This patch implements a pool of "struct dap_cmd" objects using
linked list. Objects are taken from a pool in "dap_cmd_new()" and
returned to the pool when they are not needed. Size of the pool
is limited to 64K of objects, JTAG queue is forcibly executed
when this limit is reached.
Checked with Valgrind and Clang analyzer - no new warnings.
Change-Id: I5aaaecce5ed71414f7965a2598f49742f6a6b2b5
Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com>
Reviewed-on: http://openocd.zylin.com/4948
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Correct check for end-of-region is:
$BASE + $LEN > $ADDRESS
And it is currently (wrongly) calculated as:
$ADDRESS > $BASE - $LEN
Change-Id: If10bfee19b0c7dbc085731ac1eda943f5d8a36a3
Signed-off-by: Piotr Kasprzyk <ciri@ciri.pl>
Reviewed-on: http://openocd.zylin.com/4798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Make driver_priv point directly into the corresponding chip bank structure
and add a pointer to it to get back to its chip when it's needed. This
removes the need to keep track of any bank number, either global or chip-
local.
In addition, it simplifies the cases where the chip structure was just used
to access the chip bank fields; now they are directly accessible.
Change-Id: Iaa353cd4fa7d8ff94c2ef69028c7cb32fade0420
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/4775
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The current code checks the count to determine whether to read bytes or
words. However it fails to consider whether the base address is suitably
aligned.
Instead use the target_read_buffer() function which is for exactly this
purpose and generates optimal accesses with natural alignment.
Change-Id: I32ab5417890ee2219902df1529bc220fe353b4c7
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3217
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
