This sets up a few of the core "struct arm" data structures so they
can be used with ARMv7-M cores. Specifically, it:
- defines new ARM core_modes to match the microcontroller modes
(e.g. HANDLER not IRQ, and two types of thread mode);
- Establishes a new microcontroller "core_type", which can be
used to make sure v7-M (and v6-M) cores are handled right;
- adds "struct arm" to "struct armv7m" and arranges for the
target_to_armv7m() converter to use it;
- sets up the arm.core_cache and arm.cpsr values
- makes the Cortex-M3 code maintain arm.map and arm.core_mode.
This is currently set up as a parallel data structure, primarily to
minimize special cases for the semihosting support with microcontroller
profile cores.
Later patches can rip out the duplicative ARMv7-M support and start
reusing core ARM code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Specifically the Linux issue of needing "udev" rules, and MS-Windows
needing driver configuration.
Also, update the existing udev note to use the correct name of that
rules file in the source tree.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The recent patch to fixbreakpoints and dcache handling added
a bunch of overlong lines (80+ chars) ... shrink them, and do
the same to a few lines which were already overlong.
Also add a few FIXME comments to nudge (a) replacement of some
magic numbers with opcode macros, which will be much better at
showing what's actually going on, and (b) correct return codes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Get rid of new nasty warning:
NOTE! Severe performance degradation without fast memory access enabled...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Fix an unused variable warning seen when building the parport driver
under FreeBSD.
Using information from Xiaofan Chen <xiaofanc@gmail.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Breakpoints did not work because the data cache was not flushed
properly.
As a bonus add capability to write to memory marked as read only
by the MMU, which allows software breakpoints in such memory
regions.
For folk who don't know the ARM920 JTAG interface very well, the
two modes of scan chain 15 access to CP15 are confusing.
Make those parts of the ARM920 code less opaque, by:
- Adding comments referencing the relevant parts of the TRM,
catching up to similar updates in the User's Guide.
- Replacing magic numbers in physical access clients with
symbolic equivalents.
No functional change.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Cortex-M targets don't support ARM instructions.
Leave the NVIC.VTOR setup alone, but comment how the whole
routine looks like one big bug...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
When a DSP563xx-aware GDB asks OpenOCD for target registers,
the result should be a GDB with register data ... not an
OpenOCD crash.
(Note that mainline GDB doesn't currently support this core,
so for now, this requires a GDB with FreeScale patches.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Removed remaining support for various commands, like advice for
migrating old-style TAP declarations.
The documentation no longer describes them either ... so if users have
been delaying config updates, they may need to consult older releases.
ALL this stuff has been clearly marked as "do not use" for at least a
year now, so anyone still using it hasn't been holding up their end.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Issue warning to user when unlocking or writing the option bytes.
The new settings will not take effect until a target reset.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Issue warning to user when unlocking or writing the option bytes.
The new settings will not take effect until a target reset.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
This is a copy and paste of arm926ejs. Not tested, but
ready for testing at least. There is a good chance that
it will work if the generic armv4_5 fn's are robust enough...
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Copy of the 926ejs function. I have tested it only using
my rtems application (where virtual address mapping == physical).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Sometimes MS-Windows users try to use filesystem names which include
the "#" character. That's generally unwise, since it begins Tcl
comments.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
reset init would get stuck in an infinite loop when
e.g. khz was too high. Added timeout. This is a copy
of paste of a number of such bugfixes in the arm11
code.
Arm11 code reviewed for further such infinite loop bugs
and I couldn't find any more. Xing fingers it's the last
one...
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Not all cores and boards support adaptive clocking, so qualify
all advice to use it to depend on core and board support.
It's primarily ARM cores which support this; and many of the
newer ones (like Cortex-M series) don't.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
