Add support for S6E2DH MainFlash. VFlash is not implemented.
Briefly tested with SK-FM4-176L-S6E2DH V110 board.
Change-Id: If7c523d8c75307bc1494bbf4cca3eed0272e8e01
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3158
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
These appear to be just additional flash size configurations.
Entirely based on manual, untested.
Change-Id: I4460dc1a588335df8fc0a385d24513a4e35b6951
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3157
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
On the ARM PB1176JZF-S the system comes up in secure monitor
mode after reset. However the modebits in CPSR form the value
28 (0x1c) and CPSR is 0x800001dc deeming it UNRECOGNIZED.
Define this mode to be synonymous to mode 22 (MON) and things
start to work like a charm.
Change-Id: I001f7773ee1076202c0c633e466d2d833f7a1413
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-on: http://openocd.zylin.com/3196
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This adds necessary code to obtain data from the Info region which is
not memory-mapped so can't be read the usual way.
With this "flash read_bank" and "flash verify_bank" commands should
start to work as expected for the Info memory block.
Change-Id: I57e4b80fff577500cfa85954b625fe9c9ff92aa5
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3227
Tested-by: jenkins
Reviewed-by: Eldar Khayrullin <eldar.khayrullin@mail.ru>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Instead of documenting the file path as a comment and inline-commenting
the THUMB bytecode, include the hex array via preprocessor.
This assures the path is actually up-to-date and facilitates updating
the code.
Change-Id: Ieb0a7cd0bc14882ac96750f524616d9768a0c6f5
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3134
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Instead of pointing to the assembler sources in a comment and
inline-commenting the THUMB bytecode, place the hex array alongside the
assembler sources and include it via preprocessor.
Originally inspired by a typo in the file path during driver development,
but it also facilitates making changes to the assembler sources.
A Makefile is provided to help automate updating the bytecode. It is not
integrated with the automake system to avoid forcing an ARM cross-compiler
onto every user, i.e. after modifying the sources they need to be rebuilt
in that directory before building the usual way. ARM_CROSS_COMPILE= can
be passed on the make command line to deal with native ARM toolchains
or with varying prefixes of cross-toolchains.
Change-Id: I00ceb980a68c8554a180dd13719ac77b677a8bcd
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3133
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The Spansion FM4 family of microcontrollers does not offer a way to
identify the chip model nor the flash size, except for Dual Flash vs.
regular layout. Therefore the family is passed as argument and
wildcard-matched - MB9BFx6x and S6E2CC families are supported.
Iterations showed that ...
1) Just doing the flash command sequence from SRAM loader code for each
half-word took 20 minutes for an 8 KB block.
2) Doing the busy-wait in the loader merely reduced the time to 19 minutes.
3) Significant performance gains were achieved by looping in loader code
rather than in OpenOCD and by maximizing the batch size across sectors,
getting us down to ~2 seconds for 8 KB and ~2.5 minutes for 1.1 MB.
(Tested with SK-FM4-176L-S6E2CC-ETH v11, CMSIS-DAP v23.)
gcc, objcopy -Obinary and bin2char.sh are used for automating the
integration of hand-written assembler snippets.
Change-Id: I092c81074662534f50b71b91d54eb8e0098fec76
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2190
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The Flash driver for at91sam4 cpu's has been enhanced to recognise and support the SAM4N family.
Change-Id: I50c471a6053b52edffd8efdd8abfe516cc5c55ee
Signed-off-by: Colin Helliwell <colin.helliwell@ln-systems.com>
Reviewed-on: http://openocd.zylin.com/3242
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The reset-init hook for this target speeds up the CPU clock and JTAG adapter
speed. When the target is reset running with high adapter speed, a series of
warnings "DAP transaction stalled (WAIT) - slowing down" will be generated
since the adapter speed is not reduced to fit the slower CPU speed.
Fix: reduction of the adapter speed before a reset is performed.
Change-Id: Iabfc8e3f70311e0e71c8eed09b8a37fcbed9c58d
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3365
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A copy-and-paste error in the arm_disassembler opcode evaluation
disabled the recognition of MRRC instructions.
According to the arm architecture ref. manual issue E or later, MRRC and MCRR
instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5.
Error found by static code analysis using a semantic pattern to
detect duplicated tests xand.cocci, see coccinellery.org
Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3363
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The flash info command on stellaris platformes
"TI/LMI Stellaris information ... rcc is ..., rcc2 is ..."
presented the actual RCC2 register as rcc and an uninitialized variable
as rcc2 due to a copy and paste error.
Found using the semantic pattern da/da.cocci, see coccinellery.org
Change-Id: I6f920fc3e07fdc085ea8e2248fbc9453eb8393dc
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3368
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A struct member has been initialized twice. Found using the semantic
pattern da/da.cocci, see coccinellery.org
Change-Id: I0320afd60f1ba505758cc5bc0adcf27f572492fb
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3369
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Obsolete C source code semicolons were removed using the semantic patch
semicolon/semicolon.cocci, see coccinellery.org
Change-Id: I153b4995a9e028ebaf5f58c947821dc78345a777
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3367
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Writing to Intel CFI flash with unaligned tail bytes raised a false
error message although all data was programmed successfully. e.g.:
> flash write_image image 0x602e0000 bin
> Programming at 0x602e0000, count 0x00000002 bytes remaining
> couldn't write word at base 0x60000000, address 0x602e0000
> error writing to flash at address 0x60000000 at offset 0x002e0000
Root cause for this false error was a mixup of two result variables
introduced with ecc8041c.
Change-Id: Ib6b85293dbed946a36a307e5b198c47b901145bf
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-on: http://openocd.zylin.com/3233
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Simplify by printing one component per call, instead of one complete ROM
Table per call. Print common information the same way for all components,
including ROM tables, because ROM tables (at least the top level) contain
useful information in their identification registers, such as the
manufacturer of the SoC.
Print component designer name using the JEP106 helper when available.
Change-Id: Ic51bccd98acfae6886243500153fbdd567be2fae
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3182
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: James Mastros <james@mastros.biz>
The cache is forced to zero to match the value expected by the DPIDR read
so the connect sequence is not destroyed by a SELECT update.
However, DPIDR and in fact all registers except address 4 are independent
of the current DPBANKSEL value. Change swd_queue_dp_bankselect() to use
this fact and avoid touching SELECT for those registers.
Change-Id: I0cd11925fb6adef481bbf45cc24ea2c6dab4b6fb
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3231
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Investigation:
- mem_ap_read_buf_u32() no longer exists.
- JTAG_DP_DPACC & JTAG_DP_APACC are defined in adi_v5_jtag.c now.
Change-Id: I136fc3f389a5a4eb9b68bc759ce653b6da7fa75e
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Reviewed-on: http://openocd.zylin.com/3243
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
