Commit Graph

4001 Commits

Author SHA1 Message Date
Øyvind Harboe
90efc404f3 zy1000: jtag_add_dr_scan() performance improvement
Reduce overhead in jtag_add_dr_scan() a bit.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-22 08:00:10 +01:00
David Brownell
c21c740a89 ft2232 table init cleanup
Use labeled initializers in the table of layouts instead of
positional ones.  This ls cleaner and less error prone, plus
it simplifies patches which add members to these structure.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 17:19:08 -08:00
David Brownell
dc342f45f6 Developer's Guide: refresh release procedures
Be a closer match to what I've actually done for the past few cycles.

In particular, hold off pushing repository updates until after the
packages are published, as part of opening the merge window, and
mention the utility commands which actually create the archives.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 16:55:17 -08:00
David Brownell
c8ea748dc2 ADIv5: relocate memacess_tck cycles
When using an AP to access a memory (or a memory-mapped register),
some extra TCK (assuming JTAG) cycles should be added to ensure
the AP has enugh time to complete that access before trying to
collect the response.

The previous code was adding these cycles *before* trying to
access (read or write) data to that address, not *after*.  Fix
by putting the delays in the right location.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:58:16 -08:00
David Brownell
3b68a708c2 ADIv5: remove ATOMIC/COMPOSITE interface mode
This removes context-sensitivity from the programming interface and makes
it possible to know what a block of code does without needing to know the
previous history (specifically, the DAP's "trans_mode" setting).

The mode was only set to ATOMIC briefly after DAP initialization, making
this patch be primarily cleanup; almost everything depends on COMPOSITE.
The transactions which shouldn't have been queued were already properly
flushing the queue.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:56:56 -08:00
David Brownell
ecff73043c ARM: ADIv5, deadcode cleanup
I have no idea what the scan_inout_check() was *expecting* to achieve by
issuing a read of the DP_RDBUFF register.  But in any case, that code was
clearly never being called ("invalue" always NULL) ... so remove it, and
the associated comment.

Also rename it as ap_write_check(), facilitating a cleanup of its single
call site by removing constant parameters.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:54:54 -08:00
David Brownell
39cfe62796 ARM: ADIv5 code shrinkage, cleanup
adi_jtag_dp_scan_u32() now wraps adi_jtag_dp_scan(), removing
code duplication.  Include doxygen for the former.  Comment
some particularly relevant points.  Minor fault handling fixes
for both routines:  don't register a callback that can't run,
or return ERROR_OK after an error.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:53:15 -08:00
David Brownell
a97bb67543 ADIv5 clean up AP fault handling
Pass up fault codes from various routines, so their callers
can clean up after failures, and remove the FIXME comments
highlighting those previously goofy code paths.

 dap_ap_{read,write}_reg_u32()
 dap_ap_write_reg()
 mem_ap_{read,write}_u32()
 mem_ap_{read,write}_atomic_u32()
 dap_setup_accessport()

Make dap_ap_write_reg_u32() just wrap dap_ap_write_reg(),
instead of cloning its core code (and broken fault handling).

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:51:19 -08:00
David Brownell
249263d29d ADIv5 clean up AP selection and register caching
Handling of AP (and AP register bank) selection, and cached AP
registers, is pretty loose ... start tightening it:

 - It's "AP bank" select support ... there are no DP banks.  Rename.
   + dap_dp_bankselect() becomes dap_ap_bankselect()
   + "dp_select_value" struct field becomes "ap_bank_value"

 - Remove duplicate AP cache init paths ... only use dap_ap_select(),
 and don't make Cortex (A8 or M3) cores roll their own code.

 - For dap_ap_bankselect(), pass up any fault code from writing
 the SELECT register.  (Nothing yet checks those codes.)

 - Add various bits of Doxygen

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:48:04 -08:00
David Brownell
1aac72d243 ARM: keep a handle to the PC
Keep a handle to the PC in "struct arm", and use it.
This register is used a fair amount, so this is a net
minor code shrink (other than some line length fixes),
but mostly it's to make things more readable.

For XScale, fix a dodgy sequence while stepping.  It
was initializing a variable to a non-NULL value, then
updating it to handle the step-over-active-breakpoint
case, and then later testing for non-NULL to see if
it should reverse that step-over-active logic.  It
should have done like ARM7/ARM9 does: init to NULL.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:34:33 -08:00
David Brownell
a299371a9e ARM DPM: support adding/removing HW breakpoints
Generalize the core of watchpoint setup so that it can handle
breakpoints too.  Create breakpoint add/remove routines which
will use that, and hook them up to target types which don't
provide their own breakpoint support (nothing, yet).

This suffices for hardware-only breakpoint support.  The ARM11
code will be able to switch over to this without much trouble,
since it doesn't yet handle software breakpoints.  Switching
Cortex-A8 will be a bit more involved.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:32:34 -08:00
David Brownell
27c068c1f8 ARM11: per-core options should not be global
Address some FIXME comments by getting rid of globals, moving
per-core parameters in the existing per-core data structure.

This will matter most whenever there are multiple ARM11 cores,
e.g. ARM11 MPcore chips, but in general is just cleanup.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:30:27 -08:00
David Brownell
ce1feaa732 ARMv7-M: start using "struct arm"
This sets up a few of the core "struct arm" data structures so they
can be used with ARMv7-M cores.  Specifically, it:

 - defines new ARM core_modes to match the microcontroller modes
   (e.g. HANDLER not IRQ, and two types of thread mode);

 - Establishes a new microcontroller "core_type", which can be
   used to make sure v7-M (and v6-M) cores are handled right;

 - adds "struct arm" to "struct armv7m" and arranges for the
   target_to_armv7m() converter to use it;

 - sets up the arm.core_cache and arm.cpsr values

 - makes the Cortex-M3 code maintain arm.map and arm.core_mode.

This is currently set up as a parallel data structure, primarily to
minimize special cases for the semihosting support with microcontroller
profile cores.

Later patches can rip out the duplicative ARMv7-M support and start
reusing core ARM code.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:28:53 -08:00
David Brownell
b853b9dbc0 Open the merge window for the 0.5.0 release cycle.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 13:27:37 -08:00
David Brownell
56e74908d1 Label builds as OpenOCD v0.4.0
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
v0.4.0
2010-02-21 12:20:13 -08:00
David Brownell
4aa0a4d811 User's Guide mentions OS-specific installation
Specifically the Linux issue of needing "udev" rules, and MS-Windows
needing driver configuration.

Also, update the existing udev note to use the correct name of that
rules file in the source tree.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 09:29:24 -08:00
David Brownell
bb4cb7935e arm920t line length cleanup
The recent patch to fixbreakpoints and dcache handling added
a bunch of overlong lines (80+ chars) ... shrink them, and do
the same to a few lines which were already overlong.

Also add a few FIXME comments to nudge (a) replacement of some
magic numbers with opcode macros, which will be much better at
showing what's actually going on, and (b) correct return codes.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-20 20:47:38 -08:00
David Brownell
57d5673dea CSB337 board cleanup (quasi-regression)
Get rid of new nasty warning:

NOTE! Severe performance degradation without fast memory access enabled...

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-20 20:47:38 -08:00
David Brownell
d2a2c14d20 FreeBSD buildfix
Fix an unused variable warning seen when building the parport driver
under FreeBSD.

Using information from Xiaofan Chen <xiaofanc@gmail.com>

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-20 11:11:43 -08:00
Marc Pignat
3f30563c88 atm920t : fix breakpoints and data cache handling
Breakpoints did not work because the data cache was not flushed
properly.

As a bonus add capability to write to memory marked as read only
by the MMU, which allows software breakpoints in such memory
regions.
2010-02-19 08:18:12 +01:00
David Brownell
aa8db989b9 ARM920T scanchain 15 comments/cleanup
For folk who don't know the ARM920 JTAG interface very well, the
two modes of scan chain 15 access to CP15 are confusing.

Make those parts of the ARM920 code less opaque, by:

 - Adding comments referencing the relevant parts of the TRM,
   catching up to similar updates in the User's Guide.

 - Replacing magic numbers in physical access clients with
   symbolic equivalents.

No functional change.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-16 18:50:16 -08:00
Øyvind Harboe
fa1cfc2d4d gpl: fix GPL startup message
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-15 22:59:41 +01:00
David Brownell
5869992314 LPC1768.cfg -- partial fixes for bogus reset-init handler
Cortex-M targets don't support ARM instructions.

Leave the NVIC.VTOR setup alone, but comment how the whole
routine looks like one big bug...

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-15 13:39:16 -08:00
Mathias Kuester
52d4ba3467 fix crash with DSP563XX
When a DSP563xx-aware GDB asks OpenOCD for target registers,
the result should be a GDB with register data ... not an
OpenOCD crash.

(Note that mainline GDB doesn't currently support this core,
so for now, this requires a GDB with FreeScale patches.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-14 12:59:10 -08:00
David Brownell
a2ce3a51df NEWS: mention removal of obsolete commands
Removed remaining support for various commands, like advice for
migrating old-style TAP declarations.

The documentation no longer describes them either ... so if users have
been delaying config updates, they may need to consult older releases.

ALL this stuff has been clearly marked as "do not use" for at least a
year now, so anyone still using it hasn't been holding up their end.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-13 20:14:49 -08:00