Hello,
this patch add commands to access to x,y and p memory. For run time optimization some local jtag
function was changed to static inline.
Regards,
Mathias
Also i have checked the input of this function and in many cases
a simple byte copy is possible.
I have added this check now and is it possible the buffer is
copied byte by byte and not bit by bit.
With byte boundary input the test looks like this:
buf_set_buf 0x02000000 iteration test:
runtime (seconds): old: 6.828559 new: 0.436191 diff: 6.392368
runtime (seconds): old: 6.853636 new: 0.430389 diff: 6.423247
runtime (seconds): old: 6.794985 new: 0.423065 diff: 6.371920
Without:
buf_set_buf 0x02000000 iteration test:
runtime (seconds): old: 6.370869 new: 5.552624 diff: 0.818245
runtime (seconds): old: 6.420730 new: 5.665887 diff: 0.754843
runtime (seconds): old: 6.583306 new: 5.599021 diff: 0.984285
Regards,
Mathias
Hello,
this patch adds the missing cpu registers and the correct read/write register functions and fixed
most of the halt/step/resume issues. The complete missing error propagation was added.
+ fix tab/spaces
Regards,
Mathias
* Write to the PRM reset control register should have been 'phys';
* Setup empty reset-assert handlers for the M3's, since the board-level reset
takes care of them;
* Remove the dbginit cruft, because it gets called implicitly on reset.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
If a handler for the reset-assert event it present, skip the usual reset
handling. This is needed, for example, for board-level resets.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
ARM11 broke with aa61a3b3d8
as the code only checked for arm 7/9.
CFI probably needs work for non-ARM targets but perhaps
not adding working area memory to e.g. MIPS will give
the default slow CFI support.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
ARM Cortex-A9 multi-core chips expose a single TAP/DAP which connects
to both cores. The '-coreid' option selects which core the target
should connect to.
Note that at present, OpenOCD can connect to either core, but not both
simulatenously, until ADI contexts can be shared.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
ahbap_debugport_init was queueing reads to a local stack variable but
didn't execute the queue before returning. Since the result of the reads
are not used anyway, it's better to pass NULL as the destination instead of
a dummy variable. I changed this throughout the function, even for the
reads that were actually executed.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Added a Perl script to contrib that uses the header files in StellarisWare complete Firmware Development Package provided by TI/Luminary to generate a new list of device IDs
Used Perl script and revision 6734 of TI/Luminary StellarisWare to update device IDs
Hi,
I took the stm32x NOR flash driver and adapted it for the Ember EM357
chip. This chip is very similar to em351 and stm32w so the driver
should be easily extended to support those as well if anyone can get
their hands on some of those for testing.
changelog:
Added NOR flash driver em357
Best regards,
Erik Botö
Find the flash controller by position since it is before the core,
not after it.
This fixes the problem that str9xpec enable_turbo (or any other
str9xpec command) did not work. (See my post in
http://forum.sparkfun.com/viewtopic.php?f=18&t=25542)
Signed-off-by: Santeri Salko <santeri.salko@gmail.com>
